source: firmware/FAD/FACT_FAD_lib/hdl/trigger_manager_beha.vhd@ 18342

Last change on this file since 18342 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 2.2 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.trigger_manager.beha
3--
4-- Created:
5-- by - daqct3.UNKNOWN (IHP110)
6-- at - 11:26:52 14.01.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12USE ieee.std_logic_arith.all;
13
14ENTITY trigger_manager IS
15 port (
16 clk : in std_logic;
17
18 trigger_in : in std_logic;
19 trigger_out : out std_logic := '0';
20
21 drs_write : out std_logic := '1';
22
23 drs_readout_ready : in std_logic;
24 drs_readout_ready_ack : out std_logic := '0'
25
26 );
27END ENTITY trigger_manager;
28
29--
30ARCHITECTURE beha OF trigger_manager IS
31
32 type trigger_in_state_type is (T_IN_MAIN, T_IN_END);
33 type trigger_out_state_type is (T_OUT_MAIN, T_OUT_TSTART, T_OUT_TEND);
34
35 signal trigger_in_state : trigger_in_state_type := T_IN_MAIN;
36 signal trigger_out_state : trigger_out_state_type := T_OUT_MAIN;
37
38 signal drs_write_flag, drs_write_flag_int : std_logic := '0';
39
40BEGIN
41
42 trigger_in_proc : process (trigger_in, trigger_in_state) begin
43 case trigger_in_state is
44 when T_IN_MAIN =>
45 if rising_edge (trigger_in) then
46 -- stop drs
47 drs_write <= '0';
48 -- set flag
49 drs_write_flag <= '1';
50 end if;
51 when T_IN_END =>
52 drs_write <= '1';
53 drs_write_flag <= '0';
54 end case; -- trigger_in_state
55 end process trigger_in_proc;
56
57 trigger_out_proc : process (clk) begin
58 if rising_edge (clk) then
59
60 drs_write_flag_int <= drs_write_flag;
61
62 case trigger_out_state is
63 when T_OUT_MAIN =>
64 if (drs_write_flag_int = '1') then
65 trigger_out <= '1';
66 drs_readout_ready_ack <= '0';
67 trigger_out_state <= T_OUT_TSTART;
68 end if;
69 when T_OUT_TSTART =>
70 if (drs_readout_ready = '1') then
71 trigger_out <= '0';
72 trigger_in_state <= T_IN_END;
73 trigger_out_state <= T_OUT_TEND;
74 end if;
75 when T_OUT_TEND =>
76 drs_readout_ready_ack <= '1';
77 trigger_in_state <= T_IN_MAIN;
78 trigger_out_state <= T_OUT_MAIN;
79 end case; -- trigger_out_state
80 end if;
81 end process trigger_out_proc;
82
83END ARCHITECTURE beha;
84
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