source: firmware/FAD/FACT_FAD_lib/hdl/w5300_modul.vhd@ 19695

Last change on this file since 19695 was 11801, checked in by neise, 14 years ago
hex: v214; dec: v220. FAD operates with socket 0 and 1 only. (TX MEM 60kb)
File size: 63.3 KB
Line 
1-- Module Name: w5300_modul - Behavioral
2library IEEE;
3use IEEE.STD_LOGIC_1164.ALL;
4use IEEE.STD_LOGIC_ARITH.ALL;
5use IEEE.STD_LOGIC_UNSIGNED.ALL;
6library FACT_FAD_lib;
7use FACT_FAD_lib.fad_definitions.ALL;
8
9ENTITY w5300_modul IS
10 generic(
11 RAM_ADDR_WIDTH : integer := 14
12 );
13 PORT(
14 state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging.
15 debug_data_ram_empty : OUT std_logic;
16 debug_data_valid : OUT std_logic;
17 data_generator_idle_i : IN std_logic;
18 data_ram_not_full :in std_logic;
19
20 socket_tx_free_out : out std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true
21
22 clk : IN std_logic;
23 wiz_reset : OUT std_logic := '1';
24 addr : OUT std_logic_vector (9 DOWNTO 0);
25 data : INOUT std_logic_vector (15 DOWNTO 0);
26 cs : OUT std_logic := '1';
27 wr : OUT std_logic := '1';
28 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
29 rd : OUT std_logic := '1';
30 int : IN std_logic;
31 write_length : IN std_logic_vector (16 DOWNTO 0);
32 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
33 ram_data : IN std_logic_vector (15 DOWNTO 0);
34 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
35 data_valid : IN std_logic;
36 data_valid_ack : OUT std_logic := '0';
37 busy : OUT std_logic := '1';
38 write_header_flag, write_end_flag : IN std_logic;
39 fifo_channels : IN std_logic_vector (3 downto 0);
40 -- softtrigger:
41 s_trigger : OUT std_logic := '0';
42 c_trigger_enable: out std_logic := '0';
43 c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject to changes
44
45
46
47 -- FAD configuration signals:
48 ------------------------------------------------------------------------------
49 memory_manager_config_start_o : out std_logic := '0';
50 memory_manager_config_valid_i : in std_logic;
51
52 spi_interface_config_start_o : out std_logic := '0';
53 spi_interface_config_valid_i : in std_logic;
54
55 --data_generator_config_start_o : out std_logic := '0';
56 --data_generator_config_valid_i : in std_logic;
57
58 dac_setting : out dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd
59 roi_setting : out roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd
60
61 runnumber : out std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,32);
62 reset_trigger_id : out std_logic := '0';
63
64 data_ram_empty : IN std_logic;
65
66 ------------------------------------------------------------------------------
67
68 -- MAC/IP calculation signals:
69 ------------------------------------------------------------------------------
70 MAC_jumper : in std_logic_vector (1 downto 0);
71 BoardID : in std_logic_vector (3 downto 0);
72 CrateID : in std_logic_vector (1 downto 0);
73 ------------------------------------------------------------------------------
74
75 -- user controllable enable signals
76 ------------------------------------------------------------------------------
77 trigger_enable : out std_logic;
78
79 denable : out std_logic := '0'; -- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override.
80 dwrite_enable : out std_logic := '1'; -- default DWRITE low.
81 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH.
82 srclk_enable : out std_logic := '1'; -- default SRCLK on.
83 busy_enable : out std_logic := '1';
84 socket_send_mode_out : out std_logic;
85 busy_manual : out std_logic := '0';
86 ------------------------------------------------------------------------------
87
88 -- ADC CLK generator, is able to shift phase with respect to X_50M
89 -- these signals control the behavior of the digital clock manager (DCM)
90 ------------------------------------------------------------------------------
91 ps_direction : out std_logic := '1'; -- default phase shift upwards
92 ps_do_phase_shift : out std_logic := '0'; --pulse this to phase shift once
93 ps_reset : out std_logic := '0'; -- pulse this to reset the variable phase shift
94 ps_ready : in std_logic;
95 ------------------------------------------------------------------------------
96
97 -- signals used to control FAD LED bahavior:
98 -- one of the three LEDs is used for com-status info
99 ------------------------------------------------------------------------------
100 socks_waiting : out std_logic;
101 socks_connected: out std_logic
102 ------------------------------------------------------------------------------
103
104
105
106 );
107END w5300_modul ;
108
109architecture Behavioral of w5300_modul is
110
111type single_trigger_gen_state_type is ( IDLE, TRIGGERED);
112signal single_trigger_gen_state : single_trigger_gen_state_type := IDLE;
113signal trigger_input_sr : std_logic_vector ( 1 downto 0) := (others => '0') ;
114signal single_triggers_to_produce : natural range 0 to 1023 := 0;
115signal data_ram_not_full_sr : std_logic_vector (1 downto 0) := (others => '0');
116signal single_trigger_sig : std_logic := '0';
117
118type state_init_type is (
119 INTERRUPT, RESET, WAIT_AFTER_RESET, WRITE_REG, READ_REG, WRITE_DATA,
120 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1,
121 TIMEOUT,
122 --RETRY,
123 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1,
124 SEND_1ST_KEEP, SET_Sn_KPALVTR,
125 INITIAL_CONNECTION_MESSAGE_TO_FIFO, INITIAL_CONNECTION_MESSAGE_SET_SIZE_HIGH_BYTE, INITIAL_CONNECTION_MESSAGE_SET_SIZE_LOW_BYTE, INITIAL_CONNECTION_MESSAGE_SEND,
126
127 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE,
128 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER,
129 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR,
130 CONFIG_DAC_ONLY, WAIT_FOR_CONFIG_DAC_ONLY,
131
132 GENERATE_1ST_TRIGGER_AFTER_ESTABLISHED,
133 WAIT_AFTER_1ST_TRIGGER_AFTER_ESTABLISHED,
134
135 MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA
136);
137type state_write_type is (
138 WR_START,
139 WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2,
140 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7,
141 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04,
142 WR_05, WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO,
143 WR_05a, WR_05b, WR_06,
144 WR_07,
145 WR_ACK, WR_WAIT_FOR_ACK, WAIT_FOR_DATA_VALID_HIGH_AGAIN,
146 WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
147 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3
148);
149type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
150type state_interrupt_2_type is (
151 IR2_01, IR2_02, IR2_03, IR2_04, IR2_05,
152 IR2_CHECK_SOCKET_STATE, IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE,
153 WAIT_BEFORE_IR2_06,
154 IR2_06);
155
156type state_read_data_type is (
157 RD_1,
158 RD_2,
159 RD_3,
160 RD_4,
161 STATUS_OUT_START ,
162 STATUS_OUT_CHECK_IF_FIFO_FREE_01 ,
163 STATUS_OUT_CHECK_IF_FIFO_FREE_02 ,
164 STATUS_OUT_CHECK_IF_FIFO_FREE_03 ,
165 STATUS_OUT_CHECK_IF_FIFO_FREE_04 ,
166 STATUS_OUT_WRITE_HEAD ,
167 STATUS_OUT_WRITE_CMD_COUNTER ,
168 STATUS_OUT_SET_MESSAGE_LENGTH_01 ,
169 STATUS_OUT_SET_MESSAGE_LENGTH_02 ,
170 STATUS_OUT_ISSUE_SEND_COMMAND ,
171 WAIT_AFTER_SINGLE_TRIGGER,
172 RD_5,
173 WAIT_FOR_TRIGGER_ID_RESET_1, WAIT_FOR_TRIGGER_ID_RESET_2,
174 RD_6,
175 READ_COMMAND_DATA_SECTION,
176 PUT_COMMAND_DATA_SECTION,
177 EXECUTE,
178 RD_END
179);
180
181--signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
182signal RST_TIME : std_logic_vector(23 downto 0) := X"4C4B40";
183
184signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
185signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
186signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
187signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
188
189signal state_init, next_state , next_state_tmp : state_init_type := RESET;
190signal state_after_config : state_init_type := MAIN;
191signal count : std_logic_vector (2 downto 0) := "000";
192signal state_write : state_write_type := WR_START;
193signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
194signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
195signal state_read_data : state_read_data_type := RD_1;
196
197signal interrupt_ignore : std_logic := '1';
198signal int_flag : std_logic := '0';
199signal ram_access : std_logic := '0';
200
201--signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
202signal zaehler : std_logic_vector (23 downto 0) := (OTHERS => '0');
203signal data_cnt : integer := 0;
204signal drs_cnt : integer :=0;
205signal channel_cnt : integer range 0 to 9 :=0;
206signal socket_cnt : std_logic_vector (2 downto 0) := "000";
207signal roi_max : std_logic_vector (10 downto 0);
208signal data_end : integer := 0;
209
210signal socket_tx_free : std_logic_vector (16 downto 0) := (others => '0');
211signal write_length_bytes : std_logic_vector (16 downto 0);
212
213signal socket_rx_received : std_logic_vector (16 downto 0) := (others => '0');
214signal chk_recv_cntr : integer range 0 to 10000 := 0;
215
216-- --
217signal wait_cntr : integer range 0 to 10000 := 0;
218-- --
219
220signal rx_packets_cnt : std_logic_vector (15 downto 0);
221
222signal update_of_rois : std_logic := '1';
223signal update_of_lessimportant : std_logic := '1';
224
225
226signal trigger_enable_sig : std_logic := '0';
227signal trigger_enable_storage_sig : std_logic;
228
229signal local_write_length : std_logic_vector (16 DOWNTO 0);
230signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
231signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
232signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
233signal local_write_header_flag, local_write_end_flag : std_logic;
234signal local_fifo_channels : std_logic_vector (3 downto 0);
235
236signal wait_100ns_sig : std_logic_vector (5 downto 0) := "000000";
237
238constant config_addr_max : integer := 47;
239signal config_addr : integer range 0 to config_addr_max;
240type config_data_type is array (0 to config_addr_max) of std_logic_vector(15 downto 0);
241signal config_setting : config_data_type := (
242-- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY
243-- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY
244-- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY
245-- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY
246
247 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024
248 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024
249 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024
250 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs = 1024
251
252 X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs
253 X"0000",
254 X"0000", X"0000", -- MSword // LSword
255 X"0000" -- this is a dummy address; this address is used only, if the user sent an invalid address within a WRITE command
256 );
257
258
259
260-- signals used for MAC/IP calculation:
261-- these 2 synch in, the jumper state.
262signal FAD_in_cam : std_logic := '0';
263signal FAD_at_ETHZ : std_logic := '0';
264-- these 2 synch in the FMP lines encoding the FAD position in the cam.
265signal bid : std_logic_vector (3 downto 0);
266signal cid : std_logic_vector (1 downto 0);
267
268-- for 'send'-serialization
269signal FADid : integer range 0 to 39 := 0; -- 39 = number of FADs in camera minus 1
270constant MICROSEC_TO_WAIT_BEFORE_SEND : integer := 25;
271signal wait_before_send_counter : integer range 0 to 50*39*MICROSEC_TO_WAIT_BEFORE_SEND := 0;
272signal wait_before_send_counter_goal : integer range 0 to 50*39*MICROSEC_TO_WAIT_BEFORE_SEND := 0;
273
274-- these are just used as local variables, to make reading easier.
275signal mac_loc : mac_type;
276signal ip_loc : ip_type;
277signal gateway_loc : ip_type;
278signal netmask_loc : ip_type;
279
280 -- signals for synching in asynchronous input signals
281 ------------------------------------------------------------------------------
282 signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11";
283 signal data_valid_sr : std_logic_vector(1 downto 0) := "00";
284 ------------------------------------------------------------------------------
285 -- synch in CONFIG inputs
286 signal memory_manager_config_valid_i_sr : std_logic_vector(1 downto 0) := "00";
287 signal spi_interface_config_valid_i_sr : std_logic_vector(1 downto 0) := "00";
288 --signal data_generator_config_valid_i_sr : std_logic_vector(1 downto 0) := "00";
289 signal data_ram_empty_sr : std_logic_vector(1 downto 0) := (OTHERS => '0');
290
291
292 signal data_generator_idle_sr : std_logic_vector(2 downto 0) := "000";
293
294-- only for debugging
295--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
296--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
297signal DG_run_mode_temp_storage_signal : std_logic;
298signal data_generator_run_mode_signal : std_logic := '1'; -- default triggers will be accepted
299-- signals for different socket modes: DN 04.01.11
300signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets.
301-- signals for Sockek Number calculation
302signal event_number : std_logic_vector(31 downto 0);
303signal mod7_start : std_logic := '0';
304signal mod7_started : std_logic;
305signal mod7_valid : std_logic;
306signal mod7_result : std_logic_vector(2 downto 0);
307
308
309signal state_sig : std_logic_vector(7 downto 0) := X"FF";
310
311signal number_of_words_written_to_fifo : std_logic_vector(15 downto 0) := (others => '0');
312signal number_of_bytes_written_to_fifo : std_logic_vector(16 downto 0) := (others => '0');
313
314
315
316signal wait_for_sockets_closed_counter_overflow : std_logic := '0';
317signal wait_for_sockets_closed_counter_enable : std_logic := '0';
318signal wfscc_1 : integer range 0 to 50000 := 0;
319signal wfscc_2 : integer range 0 to 20000 := 0;
320
321constant wait_after_reset_max : integer := 200000000; -- this is 4sec at 50Mhz
322signal wait_after_reset_sig : integer := 0;
323
324constant initial_message_counter_max : integer := 60;
325signal initial_message_counter : integer range 0 to initial_message_counter_max := 0;
326
327constant wait_before_ir2_06_counter_max : integer := 100000;
328signal wait_before_ir2_06_counter : integer range 0 to wait_before_ir2_06_counter_max := 0;
329
330signal cmd_counter : std_logic_vector (15 downto 0) := (others => '0');
331
332
333COMPONENT mod7
334 PORT (
335 clk : IN std_logic;
336 number : IN std_logic_vector (31 DOWNTO 0);
337 start : IN std_logic;
338 remainder : OUT std_logic_vector (2 DOWNTO 0) := (others => '0');
339 started : OUT std_logic := '0';
340 valid : OUT std_logic := '0'
341 );
342 END COMPONENT;
343
344
345
346begin
347
348 mod7_calculator : mod7
349 PORT MAP (
350 clk =>clk ,
351 number =>event_number ,
352 start =>mod7_start ,
353 remainder =>mod7_result ,
354 started =>mod7_started ,
355 valid =>mod7_valid
356 );
357
358
359 --synthesis translate_off
360 RST_TIME <= X"00120";
361 --synthesis translate_on
362
363-- concurrent statemnets
364state <= (others => '0');
365debug_data_valid <= '0';
366
367-- output config settings as DAC and ROI arrays.
368roi_mapping : for i in 0 to 35 generate
369 roi_setting(i) <= conv_integer(config_setting(i)) when (conv_integer(config_setting(i)) < 1025) else 1024;
370end generate roi_mapping;
371dac_mapping : for i in 0 to 7 generate
372 dac_setting(i) <= conv_integer(config_setting(i+36));
373end generate dac_mapping;
374c_trigger_mult <= config_setting(44);
375
376
377
378trigger_enable <= trigger_enable_sig;
379
380socket_send_mode_out <= socket_send_mode;
381
382 w5300_proc : process (clk)
383 begin
384 if rising_edge (clk) then
385 --socket_tx_free_out <= socket_tx_free;
386
387
388 -- synch asynchronous inputs in:
389 memory_manager_config_valid_i_sr <= memory_manager_config_valid_i_sr(0) & memory_manager_config_valid_i;
390 spi_interface_config_valid_i_sr <= spi_interface_config_valid_i_sr(0) & spi_interface_config_valid_i;
391 --data_generator_config_valid_i_sr <= data_generator_config_valid_i_sr(0) & data_generator_config_valid_i;
392 data_ram_empty_sr <= data_ram_empty_sr(0) & data_ram_empty;
393 data_generator_idle_sr <= data_generator_idle_sr( 1 downto 0 ) & data_generator_idle_i;
394 data_ram_not_full_sr <= data_ram_not_full_sr(0) & data_ram_not_full;
395
396 w5300_interrupt_sr <= w5300_interrupt_sr(0) & int;
397 data_valid_sr <= data_valid_sr(0) & data_valid;
398
399 -- interrupt is handled synchronously
400 -- W5300 pulls low its interrpt line in case of:
401 -- When Sockets time out and
402 -- When sockets receive disconnection request.
403
404 if (w5300_interrupt_sr(1) = '0') and (interrupt_ignore = '0') then
405 case state_interrupt_1 is
406 when IR1_01 =>
407 state_sig <= X"FF";
408 int_flag <= '1';
409 busy <= '1';
410 state_interrupt_1 <= IR1_02; --wait one cycle
411 when IR1_02 =>
412 state_sig <= X"FE";
413 state_interrupt_1 <= IR1_03;
414 when IR1_03 =>
415 state_sig <= X"FD";
416 state_init <= INTERRUPT;
417 socket_cnt <= "000";
418 ram_access <= '0';
419 zaehler <= conv_std_logic_vector(0, zaehler'length);
420 count <= "000"; --what is this count counting?
421 int_flag <= '0';
422 interrupt_ignore <= '1';
423 state_interrupt_1 <= IR1_04; --this state is not existing? bad coding habit???
424 when others =>
425 state_sig <= X"FC";
426 null;
427 end case;
428 end if; -- int = '0'
429
430 if int_flag = '0' then
431 case state_init is
432 -- Interrupt
433 when INTERRUPT =>
434 case state_interrupt_2 is
435 when IR2_01 =>
436 state_sig <= X"FB";
437 par_addr <= W5300_IR;
438 state_init <= READ_REG;
439 next_state <= INTERRUPT;
440 state_interrupt_2 <= IR2_02;
441
442 -- check if it was a Sx Interrupt of Socket n
443 -- therfor: loop over all channel.
444 -- if the loop ended but no Sx Interrupt was found --> IR2_06
445 -- if an Sx Interrupt was found go to --> IR2_03 and check what happened.
446 when IR2_02 =>
447 state_sig <= X"FA";
448 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
449 state_interrupt_2 <= IR2_03;
450 else
451 socket_cnt <= socket_cnt + 1;
452 if (socket_cnt = 1) then
453 state_interrupt_2 <= IR2_05;
454 else
455 state_interrupt_2 <= IR2_02; -- go on with loop
456 end if;
457 end if;
458
459 -- check the Interrupt register of the Socket, which caused the Interrupt.
460 when IR2_03 =>
461 state_sig <= X"F9";
462 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
463 state_init <= READ_REG;
464 next_state <= INTERRUPT;
465 state_interrupt_2 <= IR2_04;
466 -- before checking what happened, clear the Interrupt register, so we can proceed.
467 when IR2_04 =>
468 state_sig <= X"F8";
469 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
470 par_data <= data_read; -- clear Interrupts
471 state_init <= WRITE_REG;
472 next_state <= INTERRUPT;
473 state_interrupt_2 <= IR2_05;
474 -- send the command to close this socket
475 -- then go back and read the main Interrupt register again,
476 -- if this was not Socket 7 ... if it was Socket 7, we're done anyway.
477 when IR2_05 =>
478 state_sig <= X"F7";
479 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
480 --par_data <= X"0010"; -- CLOSE
481 par_data <= X"0008"; -- DISCON
482 state_init <= WRITE_REG;
483 next_state <= INTERRUPT;
484 socket_cnt <= socket_cnt + 1;
485 if (socket_cnt = 1) then
486 socket_cnt <= "000";
487 --state_interrupt_2 <= IR2_06;
488 state_interrupt_2 <= WAIT_BEFORE_IR2_06;
489 else
490 state_interrupt_2 <= IR2_01;
491 end if;
492
493 when IR2_CHECK_SOCKET_STATE =>
494 wait_for_sockets_closed_counter_enable <= '1';
495
496 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; -- READ Socket Status Register
497 state_init <= READ_REG;
498 next_state <= INTERRUPT;
499 state_interrupt_2 <= IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE;
500
501 when IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE =>
502 if ( wait_for_sockets_closed_counter_overflow = '1') then
503 wait_for_sockets_closed_counter_enable <= '0';
504 socket_cnt <= "000";
505 state_interrupt_2 <= IR2_06;
506 else
507 if ( data_read(7 downto 0) = SOCKET_CLOSED ) then
508 if ( socket_cnt = 1 ) then
509 socket_cnt <= "000";
510 state_interrupt_2 <= IR2_06;
511 else
512 socket_cnt <= socket_cnt + 1;
513 state_interrupt_2 <= IR2_CHECK_SOCKET_STATE;
514 end if;
515 else
516 state_interrupt_2 <= IR2_CHECK_SOCKET_STATE;
517 end if;
518 end if;
519
520 when WAIT_BEFORE_IR2_06 =>
521 state_interrupt_2 <= WAIT_BEFORE_IR2_06;
522 wait_before_ir2_06_counter <= wait_before_ir2_06_counter + 1;
523 if (wait_before_ir2_06_counter = wait_before_ir2_06_counter_max) then
524 wait_before_ir2_06_counter <= 0;
525 state_interrupt_2 <= IR2_06;
526 end if;
527
528
529 -- we go on and reset, the W5300 and this entire state machine.
530 when IR2_06 =>
531 state_sig <= X"F6";
532 state_interrupt_1 <= IR1_01;
533 state_interrupt_2 <= IR2_01;
534 socket_cnt <= "000";
535 state_init <= RESET;
536 when others =>
537 state_interrupt_1 <= IR1_01;
538 state_interrupt_2 <= IR2_01;
539 socket_cnt <= "000";
540 state_init <= RESET;
541 end case;
542
543 -- reset W5300
544 when RESET =>
545 state_sig <= X"01";
546 c_trigger_enable <= '0';
547 trigger_enable_sig <= '0';
548 busy_enable <= '1';
549 busy_manual <= '0';
550 socket_send_mode <= '0';
551 busy <= '1';
552 zaehler <= zaehler + 1;
553 socks_waiting <= '0';
554 socks_connected <= '0';
555 wiz_reset <= '0';
556 --led <= X"FF";
557 if (zaehler >= conv_std_logic_vector(200, zaehler'length) ) then -- wait 2µs
558 wiz_reset <= '1';
559 end if;
560 if (zaehler = RST_TIME) then -- wait 10ms
561 zaehler <= conv_std_logic_vector (0, zaehler'length);
562 socket_cnt <= "000";
563 count <= "000";
564 ram_access <= '0';
565 interrupt_ignore <= '0';
566 rd <= '1';
567 wr <= '1';
568 cs <= '1';
569 state_write <= WR_START;
570 --state_init <= INIT;
571
572 -- I do this early configuration here, in order to get rid of all events in RAM.
573 -- in order to end up, with disabled trigger lines, I set trigger enable to 0.
574 -- So busy should vanish, once we are here.
575
576
577 state_init <= CONFIG;
578 state_after_config <= INIT;
579 --state_init <= WAIT_AFTER_RESET;
580 end if;
581
582 when WAIT_AFTER_RESET => -- waits macroscopic time ... 4sec currently.
583 wait_after_reset_sig <= wait_after_reset_sig + 1;
584 if (wait_after_reset_sig = wait_after_reset_max) then
585 wait_after_reset_sig <= 0;
586 state_init <= CONFIG;
587 state_after_config <= INIT;
588 end if;
589
590
591 -- Init
592 when INIT =>
593 state_sig <= X"02";
594 -- status of MAC jumpers is synched in
595 -- and Board- and CrateID are synched in
596 FAD_in_cam <= MAC_jumper(1); -- see position of jumpers in FACT logbook
597 FAD_at_ETHZ <= MAC_jumper(0); -- MAC_jumper(1) is where D_T(7) was; MAC_jumper(0) is where D_T(6) was;
598 bid <= BoardID;
599 cid <= CrateID;
600 par_addr <= W5300_MR;
601 par_data <= X"0000";
602 state_init <= WRITE_REG;
603 next_state <= LOCATE;
604
605 when LOCATE =>
606 state_sig <= X"03";
607 state_init <= IM;
608
609 -- calculate FADid for 'send'-ing serialization
610 FADid <= conv_integer(cid)*10+conv_integer(bid);
611
612 if (FAD_in_cam = '1') then
613 if (bid = "1111" and cid="11") then
614 -- if BID = "1111" and CID="11" then FAD is not really in cam
615 -- I don't know what to do now.
616 -- I could wait a long time, and then just assume, I was not in cam.
617 -- this should never happen!!!!!
618 -- impossible to find this out, if in cam
619 gateway_loc <= ETHZ_GATEWAY;
620 netmask_loc <= ETHZ_NETMASK;
621 mac_loc <= MAC_FAD2;
622 ip_loc <= IP_ETHZ_FAD2;
623 --state_init <= INIT;
624 else -- everything is fine
625 -- IP & MAC are calculated from BID & CID
626 -- code here
627 gateway_loc <= CAM_GATEWAY;
628 netmask_loc <= CAM_NETMASK;
629 mac_loc <= (CAM_MAC_prefix (0), CAM_MAC_prefix (1) , conv_std_logic_vector ( conv_integer(cid)*10+conv_integer(bid) , 16) );
630 ip_loc <= ( CAM_IP_PREFIX(0) , CAM_IP_PREFIX(1) , IP_offset + conv_integer(cid) , IP_offset + conv_integer(bid) );
631 end if;
632 else -- FAD is tested, either at ETHZ or at TUDO AND either with FMP or without.
633 if ( FAD_at_ETHZ = '0' ) then
634 -- easy FAD is at TUDO -> only one choice.
635 mac_loc <= MAC_FAD0;
636 ip_loc <= IP_TUDO;
637 gateway_loc <= TUDO_GATEWAY;
638 netmask_loc <= TUDO_NETMASK;
639 else -- FAD is at ETHZ but not in cam --> IP lookup table is needed.
640 if (bid = "1111" and cid="11") then -- FAD is not in crate
641 mac_loc <= MAC_FAD0;
642 ip_loc <= IP_ETHZ_FAD0;
643 gateway_loc <= ETHZ_GATEWAY;
644 netmask_loc <= ETHZ_NETMASK;
645 else
646 -- FAD is at ETHZ and in crate:
647 -- crate ID is not of importance.
648 -- we only have 3 MACs and IPs so far, so only the first boardIDs are allowed.
649 if ( conv_integer(bid) < MAC_LIST'length) then
650 gateway_loc <= ETHZ_GATEWAY;
651 netmask_loc <= ETHZ_NETMASK;
652 mac_loc <= MAC_LIST(conv_integer(bid));
653 ip_loc <= IP_LIST(conv_integer(bid));
654 end if; -- conv_integer
655 end if; -- bid=1111 & cid=11
656 end if; --FAD_at_ETHZ = 0
657 end if; --FAD_in_cam = 1
658
659 -- Interrupt Mask
660 when IM =>
661 state_sig <= X"04";
662 par_addr <= W5300_IMR;
663 par_data <= X"00FF"; -- S0-S7 Interrupts
664 state_init <= WRITE_REG;
665 next_state <= MT;
666
667 -- Memory Type
668 when MT =>
669 par_addr <= W5300_MTYPER;
670 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
671 state_init <= WRITE_REG;
672 next_state <= STX;
673
674 -- Socket TX Memory Size
675 when STX =>
676 par_data <= X"3C3C"; -- 60K TX
677 par_addr <= W5300_TMS01R;
678 state_init <=WRITE_REG;
679 next_state <= STX1;
680 when STX1 =>
681 par_data <= X"0000"; --- nothing
682 par_addr <= W5300_TMS23R;
683 state_init <=WRITE_REG;
684 next_state <= STX2;
685 when STX2 =>
686 par_data <= X"0000"; --- nothing
687 par_addr <= W5300_TMS45R;
688 state_init <=WRITE_REG;
689 next_state <= STX3;
690 when STX3 =>
691 par_data <= X"0000"; --- nothing
692 par_addr <= W5300_TMS67R;
693 state_init <=WRITE_REG;
694 next_state <= SRX;
695
696 -- Socket RX Memory Size
697 when SRX =>
698 par_data <= X"0404"; -- 4K RX
699 par_addr <= W5300_RMS01R;
700 state_init <=WRITE_REG;
701 next_state <= SRX1;
702 when SRX1 =>
703 par_data <= X"0000"; --- nothing
704 par_addr <= W5300_RMS23R;
705 state_init <=WRITE_REG;
706 next_state <= SRX2;
707 when SRX2 =>
708 par_data <= X"0000"; --- nothing
709 par_addr <= W5300_RMS45R;
710 state_init <=WRITE_REG;
711 next_state <= SRX3;
712 when SRX3 =>
713 par_data <= X"0000"; --- nothing
714 par_addr <= W5300_RMS67R;
715 state_init <=WRITE_REG;
716 next_state <= MAC;
717
718 -- MAC
719 when MAC =>
720 par_addr <= W5300_SHAR;
721 par_data <= mac_loc(0);
722 state_init <= WRITE_REG;
723 next_state <= MAC1;
724 when MAC1 =>
725 par_addr <= W5300_SHAR + 2;
726 par_data <= mac_loc(1);
727 state_init <= WRITE_REG;
728 next_state <= MAC2;
729 when MAC2 =>
730 par_addr <= W5300_SHAR + 4;
731 par_data <= mac_loc(2);
732 state_init <= WRITE_REG;
733 next_state <= GW;
734
735 -- Gateway
736 when GW =>
737 par_addr <= W5300_GAR;
738 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8);
739 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8);
740 state_init <= WRITE_REG;
741 next_state <= GW1;
742 when GW1 =>
743 par_addr <= W5300_GAR + 2;
744 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8);
745 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8);
746 state_init <= WRITE_REG;
747 next_state <= SNM;
748
749 -- Subnet Mask
750 when SNM =>
751 par_addr <= W5300_SUBR;
752 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8);
753 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8);
754 state_init <= WRITE_REG;
755 next_state <= SNM1;
756 when SNM1 =>
757 par_addr <= W5300_SUBR + 2;
758 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8);
759 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8);
760 state_init <= WRITE_REG;
761 next_state <= IP;
762 -- Own IP-Address
763 when IP =>
764 par_addr <= W5300_SIPR;
765 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);
766 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8);
767 state_init <= WRITE_REG;
768 next_state <= IP1;
769 when IP1 =>
770 par_addr <= W5300_SIPR + 2;
771 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8);
772 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8);
773 state_init <= WRITE_REG;
774 --next_state <= SI;
775 next_state <= TIMEOUT;
776 when TIMEOUT =>
777 par_addr <= W5300_RTR;
778 --par_data <= X"07D0"; -- 0x07D0 = 200ms
779 par_data <= X"07D0"; -- unit is 100us, so 0x000A = 10 stands for 1ms.
780 state_init <= WRITE_REG;
781 next_state <= SI;
782-- when RETRY =>
783-- par_addr <= W5300_RCR;
784-- par_data <= X"0008";
785-- state_init <= WRITE_REG;
786-- next_state <= SI;
787--
788
789 -- Socket Init
790 when SI =>
791 state_sig <= X"05";
792 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
793 par_data <= X"0101"; -- ALIGN, TCP
794 state_init <= WRITE_REG;
795 next_state <= SI1;
796 -- Sx Interrupt Mask
797 when SI1 =>
798 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
799 par_data <= X"000A"; -- TIMEOUT, DISCON
800 state_init <= WRITE_REG;
801 next_state <= SI1b;
802 when SI1b =>
803 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC;
804 par_data <= X"0200"; -- set KPALVTR to 0 so the manual SEND_KEEP is enabled.
805 state_init <= WRITE_REG;
806 next_state <= SI2;
807 when SI2 =>
808 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
809 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
810 state_init <= WRITE_REG;
811 next_state <= SI3;
812 when SI3 =>
813 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
814 par_data <= X"0001"; -- OPEN
815 state_init <= WRITE_REG;
816 next_state <= SI4;
817 when SI4 =>
818 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
819 state_init <= READ_REG;
820 next_state <= SI5;
821 when SI5 =>
822 if (data_read (7 downto 0) = X"13") then -- is open?
823 state_init <= SI6;
824 else
825 state_init <= SI4;
826 end if;
827 when SI6 =>
828 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
829 par_data <= X"0002"; -- LISTEN
830 state_init <= WRITE_REG;
831 socket_cnt <= socket_cnt + 1;
832 if (socket_cnt = 1) then
833 socket_cnt <= "000";
834 next_state <= ESTABLISH; -- All Sockets open
835 else
836 next_state <= SI; -- Next Socket
837 end if;
838 -- End Socket Init
839
840 when ESTABLISH =>
841 state_sig <= X"07";
842 socks_waiting <= '1';
843 socks_connected <= '0';
844 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
845 state_init <= READ_REG;
846 next_state <= EST1;
847 when EST1 =>
848 state_sig <= X"08";
849 case data_read (7 downto 0) is
850 when X"17" => -- established
851 if (socket_cnt = 1) then
852 socket_cnt <= "000";
853 busy <= '0';
854 state_init <= MAIN;
855 --state_init <= SEND_1ST_KEEP;
856 --state_init <= INITIAL_CONNECTION_MESSAGE_TO_FIFO;
857 --state_init <= CONFIG_MEMORY_MANAGER;
858 else
859 socket_cnt <= socket_cnt + 1;
860 state_init <= ESTABLISH;
861 end if;
862 when others =>
863 state_init <= ESTABLISH;
864 end case;
865
866 -- the following two states were intended to get the W5300 to send
867 --a first keep alive package after the connection was established.
868 -- The reason was, that the W5300 is not sending any keep alive messages before not a single byte was send to the peer.
869 -- --
870 -- But this did not work.
871 -- the next idea is, to send a single message of 60 bytes, all 0x00 to the peer.
872 -- this is done for each of the 7 seockets.
873 --
874 --
875 when SEND_1ST_KEEP =>
876 next_state <= SEND_1ST_KEEP; -- Next Socket
877 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
878 par_data <= X"0022"; -- SEND_KEEP
879 state_init <= WRITE_REG;
880 socket_cnt <= socket_cnt + 1;
881 if (socket_cnt = 1) then
882 socket_cnt <= "000";
883 next_state <= SET_Sn_KPALVTR;
884 end if;
885
886 when SET_Sn_KPALVTR => -- send automatic KEEP ALIVE every 10s.
887 next_state <= SET_Sn_KPALVTR;
888 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC;
889 par_data <= X"0200"; -- send automatic KEEP ALIVE every 10s.
890 state_init <= WRITE_REG;
891
892 socket_cnt <= socket_cnt + 1;
893 if (socket_cnt = 1) then
894 socket_cnt <= "000";
895 next_state <= MAIN;
896 end if;
897
898 when INITIAL_CONNECTION_MESSAGE_TO_FIFO =>
899 -- the state is only reached, when just resetted the W5300 so the TX_FIFO is empty.
900 -- additionally not SEND action can take place right now.
901 -- so I can start writing 0x00 into the fifo
902 par_addr <= W5300_S0_TX_FIFOR + socket_cnt * W5300_S_INC;
903 par_data <= conv_std_logic_vector(initial_message_counter, 13)&socket_cnt;
904 ram_access <= '0';
905 state_init <= WRITE_REG;
906 next_state <= INITIAL_CONNECTION_MESSAGE_TO_FIFO;
907 initial_message_counter <= initial_message_counter + 1;
908 if (initial_message_counter = initial_message_counter_max) then
909 initial_message_counter <= 0;
910 socket_cnt <= socket_cnt + 1;
911 if (socket_cnt = 1) then
912 socket_cnt <= "000";
913 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_HIGH_BYTE;
914 end if;
915 end if;
916
917 when INITIAL_CONNECTION_MESSAGE_SET_SIZE_HIGH_BYTE =>
918 ram_access <= '0';
919 par_addr <= W5300_S0_TX_WRSR + socket_cnt * W5300_S_INC;
920 par_data <= (others => '0');
921 state_init <= WRITE_REG;
922 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_HIGH_BYTE;
923 socket_cnt <= socket_cnt + 1;
924 if (socket_cnt = 1) then
925 socket_cnt <= "000";
926 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_LOW_BYTE;
927 end if;
928
929 when INITIAL_CONNECTION_MESSAGE_SET_SIZE_LOW_BYTE =>
930 ram_access <= '0';
931 par_addr <= W5300_S0_TX_WRSR + (socket_cnt * W5300_S_INC) + X"2";
932 par_data <= conv_std_logic_vector(initial_message_counter_max+40, 16);
933 state_init <= WRITE_REG;
934 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_LOW_BYTE;
935 socket_cnt <= socket_cnt + 1;
936 if (socket_cnt = 1) then
937 socket_cnt <= "000";
938 next_state <= INITIAL_CONNECTION_MESSAGE_SEND;
939 end if;
940
941
942 when INITIAL_CONNECTION_MESSAGE_SEND =>
943 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
944 par_data <= X"0020"; -- Send
945 state_init <= WRITE_REG;
946 next_state <= INITIAL_CONNECTION_MESSAGE_SEND;
947 socket_cnt <= socket_cnt + 1;
948 if (socket_cnt = 1) then
949 socket_cnt <= "000";
950 next_state <= MAIN;
951 end if;
952
953 when CONFIG => -- Triggers are disabled here!
954 state_sig <= X"06";
955 trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal.
956 trigger_enable_sig <= '0'; --no triggers must occur, while configurating.
957 state_init <= WAIT_100NS;
958
959 when WAIT_100NS =>
960 state_sig <= X"15";
961 wait_100ns_sig <= wait_100ns_sig + 1;
962 if (wait_100ns_sig = "110010") then
963 wait_100ns_sig <= "000000";
964 state_init <= WAIT_UNTIL_DG_IDLE;
965 end if;
966
967 when WAIT_UNTIL_DG_IDLE =>
968 state_sig <= X"16";
969 if (data_generator_idle_sr = "111") then
970 state_init <= CONFIG_MEMORY_MANAGER;
971 end if;
972
973
974 when CONFIG_MEMORY_MANAGER =>
975 state_sig <= X"18";
976 memory_manager_config_start_o <= '1';
977 if (memory_manager_config_valid_i_sr = "00") then
978 state_init <= WAIT_FOR_CONFIG_MEMORY_MANAGER;
979 end if;
980
981 when WAIT_FOR_CONFIG_MEMORY_MANAGER =>
982 state_sig <= X"19";
983 memory_manager_config_start_o <= '0';
984 if (memory_manager_config_valid_i_sr(1) = '1') then
985 --state_init <= CONFIG_DATA_GENERATOR;
986 trigger_enable_sig <= trigger_enable_storage_sig;
987 state_init <= state_after_config;
988 --state_init <= MAIN;
989 end if;
990
991
992 when CONFIG_DAC_ONLY =>
993 state_sig <= X"1C";
994 spi_interface_config_start_o <= '1';
995 if (spi_interface_config_valid_i_sr ="00") then
996 state_init <= WAIT_FOR_CONFIG_DAC_ONLY;
997 end if;
998
999 when WAIT_FOR_CONFIG_DAC_ONLY =>
1000 state_sig <= X"1D";
1001 spi_interface_config_start_o <= '0';
1002 if (spi_interface_config_valid_i_sr ="11") then
1003 state_init <= MAIN;
1004 end if;
1005
1006----------------------------------------------------------------------------------
1007-- MAIN "loop" -------------------------------------------------------------------
1008----------------------------------------------------------------------------------
1009
1010 when GENERATE_1ST_TRIGGER_AFTER_ESTABLISHED =>
1011 zaehler <= conv_std_logic_vector(0, zaehler'length);
1012 single_trigger_sig <= '1';
1013 state_init <= WAIT_AFTER_1ST_TRIGGER_AFTER_ESTABLISHED;
1014
1015 when WAIT_AFTER_1ST_TRIGGER_AFTER_ESTABLISHED =>
1016 zaehler <= zaehler + 1;
1017 if (zaehler = conv_std_logic_vector(3, zaehler'length) ) then
1018 single_trigger_sig <= '0';
1019 state_init <= MAIN;
1020 end if;
1021 state_init <= WAIT_AFTER_1ST_TRIGGER_AFTER_ESTABLISHED;
1022
1023
1024
1025 when MAIN =>
1026 state_sig <= X"20";
1027 socks_waiting <= '0';
1028 socks_connected <= '1';
1029 ps_do_phase_shift <= '0';
1030 ps_reset <= '0';
1031 data_valid_ack <= '0';
1032
1033
1034 if (update_of_rois = '1') then
1035 update_of_rois <= '0';
1036
1037 state_after_config <= MAIN; --this needs to be set to main, in order to return here, after configuration
1038 state_init <= CONFIG;
1039-- if (trigger_enable_sig = '1') then
1040-- trigger_enable_storage_sig <= trigger_enable_sig;
1041-- end if;
1042-- trigger_enable_sig <= '0';
1043--
1044-- update_of_rois <= '0';
1045-- state_init <= CONFIG_MEMORY_MANAGER;
1046-- if (data_ram_empty_sr(1) = '1') then
1047-- update_of_rois <= '0';
1048-- state_init <= CONFIG_MEMORY_MANAGER;
1049-- else
1050-- state_init <= MAIN2;
1051-- end if;
1052
1053 elsif (update_of_lessimportant = '1') then
1054 update_of_lessimportant <= '0';
1055 state_init <= CONFIG_DAC_ONLY;
1056 else -- update_of_rois='0' and update_of_lessimportant='0'
1057 state_init <= MAIN1;
1058 --data_valid_int <= data_valid;
1059 end if;
1060
1061 when MAIN1 =>
1062 state_sig <= X"21";
1063 if (chk_recv_cntr = 1000) then
1064 chk_recv_cntr <= 0;
1065 state_read_data <= RD_1;
1066 state_init <= READ_DATA;
1067 busy <= '1';
1068 else
1069 chk_recv_cntr <= chk_recv_cntr + 1;
1070 state_init <= MAIN2;
1071 end if;
1072 when MAIN2 =>
1073 state_sig <= X"22";
1074 busy <= '0';
1075 --if (data_valid = '1') then
1076 if (data_valid_sr(1) = '1') then
1077 --data_valid_int <= '0';
1078 busy <= '1';
1079 local_write_length <= write_length;
1080 local_ram_start_addr <= ram_start_addr;
1081 local_ram_addr <= (others => '0');
1082 local_write_header_flag <= write_header_flag;
1083 local_write_end_flag <= write_end_flag;
1084 local_fifo_channels <= fifo_channels;
1085 -- data_valid_ack <= '1';
1086 -- next_state <= MAIN;
1087 -- state_init <= WRITE_DATA;
1088 state_init <= MAIN3;
1089 else
1090 state_init <= MAIN1;
1091 end if;
1092 when MAIN3 =>
1093 debug_data_ram_empty <= local_write_end_flag;
1094 state_sig <= X"23";
1095 -- needed for the check: if there is enough space in W5300 FIFO
1096 write_length_bytes <= (local_write_length (15 downto 0) & '0') ; -- shift left (*2)
1097
1098 next_state <= MAIN;
1099 state_init <= WRITE_DATA;
1100
1101
1102----------------------------------------------------------------------------------
1103-- END OF MAIN -----------------------------------------------------------
1104----------------------------------------------------------------------------------
1105
1106 -- read data from socket 0
1107 when READ_DATA =>
1108 case state_read_data is
1109 when RD_1 =>
1110 state_sig <= X"30";
1111 par_addr <= W5300_S0_RX_RSR;
1112 state_init <= READ_REG;
1113 next_state <= READ_DATA;
1114 state_read_data <= RD_2;
1115 when RD_2 =>
1116 state_sig <= X"31";
1117 socket_rx_received (16) <= data_read(0);
1118 par_addr <= W5300_S0_RX_RSR + X"2";
1119 state_init <= READ_REG;
1120 next_state <= READ_DATA;
1121 state_read_data <= RD_3;
1122 when RD_3 =>
1123 state_sig <= X"32";
1124 socket_rx_received (15 downto 0) <= data_read;
1125 state_read_data <= RD_4;
1126 when RD_4 =>
1127 state_sig <= X"33";
1128 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
1129 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
1130 state_read_data <= RD_5;
1131 else
1132 busy <= '0';
1133 state_init <= MAIN;
1134 end if;
1135 when RD_5 =>
1136 state_sig <= X"34";
1137 s_trigger <='0';
1138 single_trigger_sig <= '0';
1139 ps_do_phase_shift <= '0';
1140 reset_trigger_id <= '0';
1141
1142 if (rx_packets_cnt > 0) then
1143 rx_packets_cnt <= rx_packets_cnt - '1';
1144 par_addr <= W5300_S0_RX_FIFOR;
1145 state_init <= READ_REG;
1146 next_state <= READ_DATA;
1147 state_read_data <= RD_6;
1148 else
1149 state_read_data <= RD_END;
1150 end if;
1151
1152 when RD_6 =>
1153 state_sig <= X"35";
1154 -- The next 16bit word is assumed to contain a 'command' so it is
1155 -- beeing parsed in this state
1156 case data_read (15 downto 8) is
1157 when CMD_START =>
1158
1159 state_read_data <= RD_5;
1160 when CMD_STOP =>
1161
1162 state_read_data <= RD_5;
1163 when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7
1164 socket_send_mode <= '1';
1165 state_read_data <= RD_5;
1166 when CMD_MODE_COMMAND => -- all data will be send via socket 0
1167 socket_send_mode <= '0';
1168 state_read_data <= RD_5;
1169 when CMD_TRIGGER =>
1170 zaehler <= conv_std_logic_vector(0, zaehler'length);
1171 s_trigger <= '1';
1172 single_trigger_sig <= '1';
1173 state_read_data <= RD_5;
1174 --state_read_data <= WAIT_AFTER_SINGLE_TRIGGER;
1175 when CMD_DWRITE_RUN =>
1176 dwrite_enable <= '1';
1177 state_read_data <= RD_5;
1178 when CMD_DWRITE_STOP =>
1179 dwrite_enable <= '0';
1180 state_read_data <= RD_5;
1181 when CMD_SCLK_ON =>
1182 sclk_enable <= '1';
1183 state_read_data <= RD_5;
1184 when CMD_SCLK_OFF =>
1185 sclk_enable <= '0';
1186 state_read_data <= RD_5;
1187
1188
1189 when CMD_MANUAL_BUSY_ON =>
1190 busy_manual <= '1';
1191 state_read_data <= RD_5;
1192 when CMD_MANUAL_BUSY_OFF =>
1193 busy_manual <= '0';
1194 state_read_data <= RD_5;
1195
1196 when CMD_DENABLE =>
1197 denable <= '1';
1198 state_read_data <= RD_5;
1199 when CMD_DDISABLE =>
1200 denable <= '0';
1201 state_read_data <= RD_5;
1202
1203 when CMD_BUSY_FIX_OFF_TRUE =>
1204 busy_enable <= '1';
1205 state_read_data <= RD_5;
1206 when CMD_BUSY_FIX_OFF_FALSE =>
1207 busy_enable <= '0';
1208 state_read_data <= RD_5;
1209
1210 when CMD_STATUS =>
1211 state_read_data <= STATUS_OUT_START;
1212
1213
1214 when CMD_TRIGGER_C =>
1215 c_trigger_enable <= '1';
1216 state_read_data <= RD_5;
1217 when CMD_TRIGGER_S =>
1218 c_trigger_enable <= '0';
1219 state_read_data <= RD_5;
1220
1221 -- phase shift commands here:
1222 when CMD_PS_DO =>
1223 ps_do_phase_shift <= '1';
1224 state_read_data <= RD_5;
1225 when CMD_PS_DIRINC =>
1226 ps_direction <= '1';
1227 state_read_data <= RD_5;
1228 when CMD_PS_RESET =>
1229 ps_reset <= '1';
1230 state_read_data <= RD_5;
1231 when CMD_SRCLK_ON =>
1232 srclk_enable <= '1';
1233 state_read_data <= RD_5;
1234 when CMD_SRCLK_OFF =>
1235 srclk_enable <= '0';
1236 state_read_data <= RD_5;
1237 when CMD_TRIGGERS_ON =>
1238 trigger_enable_sig <= '1';
1239 state_read_data <= RD_5;
1240 when CMD_TRIGGERS_OFF =>
1241 trigger_enable_sig <= '0';
1242 state_read_data <= RD_5;
1243 when CMD_PS_DIRDEC =>
1244 ps_direction <= '0';
1245 state_read_data <= RD_5;
1246
1247 when CMD_RESET_TRIGGER_ID =>
1248 reset_trigger_id <= '1';
1249 state_read_data <= WAIT_FOR_TRIGGER_ID_RESET_1;
1250
1251 when CMD_WRITE =>
1252 if ( (conv_integer(data_read (7 downto 0)) >= 0) and (conv_integer(data_read (7 downto 0)) <= config_addr_max-1) ) then
1253 config_addr <= conv_integer(data_read (7 downto 0));
1254 state_read_data <= READ_COMMAND_DATA_SECTION;
1255 else
1256 config_addr <= config_addr_max;
1257 state_read_data <= READ_COMMAND_DATA_SECTION;
1258 end if;
1259
1260 when CMD_EXECUTE =>
1261 state_read_data <= EXECUTE;
1262
1263 when others =>
1264 state_read_data <= RD_5;
1265 end case;
1266 -- read data
1267
1268 when WAIT_FOR_TRIGGER_ID_RESET_1 =>
1269 state_sig <= X"36";
1270 state_read_data <= WAIT_FOR_TRIGGER_ID_RESET_2;
1271 when WAIT_FOR_TRIGGER_ID_RESET_2 =>
1272 state_sig <= X"37";
1273 state_read_data <= RD_5;
1274
1275 when WAIT_AFTER_SINGLE_TRIGGER =>
1276 zaehler <= zaehler + 1;
1277 if (zaehler = conv_std_logic_vector(3, zaehler'length) ) then
1278 single_trigger_sig <= '0';
1279 state_read_data <= RD_5;
1280 end if;
1281 state_read_data <= WAIT_AFTER_SINGLE_TRIGGER;
1282
1283 -- these states are beeing processed, if the 'command' was a 'write command'
1284 -- so it is assumed, that some data in config RAM changed, and we need full (re)config
1285 when READ_COMMAND_DATA_SECTION =>
1286 state_sig <= X"38";
1287 if (rx_packets_cnt > 0) then
1288 rx_packets_cnt <= rx_packets_cnt - '1';
1289 par_addr <= W5300_S0_RX_FIFOR;
1290 state_init <= READ_REG;
1291 next_state <= READ_DATA;
1292 state_read_data <= PUT_COMMAND_DATA_SECTION;
1293 else
1294 state_read_data <= RD_END;
1295 end if;
1296
1297 when PUT_COMMAND_DATA_SECTION =>
1298 state_sig <= X"39";
1299 config_setting(config_addr) <= data_read;
1300
1301-- if (config_addr < 36) then
1302-- update_of_rois <= '1';
1303-- else
1304-- if (config_addr < 45 ) then
1305-- update_of_lessimportant <= '1';
1306-- end if;
1307-- end if;
1308
1309 state_read_data <= RD_5;
1310
1311 when EXECUTE =>
1312 update_of_rois <= '1';
1313 update_of_lessimportant <= '1';
1314 runnumber <= config_setting(45) & config_setting(46);
1315
1316 state_read_data <= RD_5;
1317
1318 when RD_END =>
1319 state_sig <= X"3A";
1320 par_addr <= W5300_S0_CR;
1321 par_data <= X"0040"; -- RECV
1322 state_init <= WRITE_REG;
1323 next_state <= MAIN;
1324
1325
1326 when STATUS_OUT_START =>
1327 number_of_words_written_to_fifo <= (others => '0');
1328 state_read_data <= STATUS_OUT_CHECK_IF_FIFO_FREE_01;
1329 when STATUS_OUT_CHECK_IF_FIFO_FREE_01 =>
1330 par_addr <= W5300_S0_TX_FSR;
1331 state_init <= READ_REG;
1332 next_state <= READ_DATA;
1333 state_read_data <= STATUS_OUT_CHECK_IF_FIFO_FREE_02;
1334 when STATUS_OUT_CHECK_IF_FIFO_FREE_02 =>
1335 socket_tx_free (16) <= data_read(0);
1336 par_addr <= W5300_S0_TX_FSR + X"2";
1337 state_init <= READ_REG;
1338 next_state <= READ_DATA;
1339 state_read_data <= STATUS_OUT_CHECK_IF_FIFO_FREE_03;
1340 when STATUS_OUT_CHECK_IF_FIFO_FREE_03 =>
1341 socket_tx_free (15 downto 0) <= data_read;
1342 state_read_data <= STATUS_OUT_CHECK_IF_FIFO_FREE_04;
1343 when STATUS_OUT_CHECK_IF_FIFO_FREE_04 =>
1344 socket_tx_free_out <= socket_tx_free;
1345 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
1346 state_read_data <= STATUS_OUT_CHECK_IF_FIFO_FREE_01;
1347 else
1348 state_read_data <= STATUS_OUT_WRITE_HEAD;
1349 end if;
1350 when STATUS_OUT_WRITE_HEAD =>
1351 par_addr <= W5300_S0_TX_FIFOR;
1352 par_data <= X"fb02";
1353 state_init <= WRITE_REG;
1354 next_state <= READ_DATA;
1355 state_read_data <= STATUS_OUT_WRITE_CMD_COUNTER;
1356 when STATUS_OUT_WRITE_CMD_COUNTER =>
1357 par_addr <= W5300_S0_TX_FIFOR;
1358 par_data <= cmd_counter;
1359 state_init <= WRITE_REG;
1360 cmd_counter <= cmd_counter +1;
1361 next_state <= READ_DATA;
1362 state_read_data <= STATUS_OUT_SET_MESSAGE_LENGTH_01;
1363 when STATUS_OUT_SET_MESSAGE_LENGTH_01 =>
1364 par_addr <= W5300_S0_TX_WRSR;
1365 par_data <= (others => '0');
1366 state_init <= WRITE_REG;
1367 next_state <= READ_DATA;
1368 state_read_data <= STATUS_OUT_SET_MESSAGE_LENGTH_02;
1369 when STATUS_OUT_SET_MESSAGE_LENGTH_02 =>
1370 par_addr <= W5300_S0_TX_WRSR + X"2";
1371 par_data <= conv_std_logic_vector(4,16);
1372 state_init <= WRITE_REG;
1373 next_state <= READ_DATA;
1374 state_read_data <= STATUS_OUT_ISSUE_SEND_COMMAND;
1375 when STATUS_OUT_ISSUE_SEND_COMMAND =>
1376 par_addr <= W5300_S0_CR;
1377 par_data <= X"0020"; -- Send
1378 state_init <= WRITE_REG;
1379 next_state <= READ_DATA;
1380 state_read_data <= RD_5;
1381
1382
1383
1384 when others =>
1385 state_sig <= X"3F";
1386
1387 end case; -- state_data_read
1388
1389
1390
1391 when WRITE_DATA =>
1392 case state_write is
1393
1394 when WR_START =>
1395 state_sig <= X"40";
1396 if (local_write_header_flag = '1') then
1397 ram_addr <= local_ram_start_addr + 6; -- Address of HIGH word of Event ID
1398 state_write <= WR_GET_EVT_ID_WAIT1;
1399 else
1400 state_write <= WR_CHECK_FOR_FIFO_SPACE_01;
1401 end if;
1402
1403 when WR_GET_EVT_ID_WAIT1 =>
1404 state_sig <= X"41";
1405 state_write <= WR_GET_EVT_ID1;
1406 when WR_GET_EVT_ID1 =>
1407 state_sig <= X"42";
1408 event_number(31 downto 16) <= ram_data;
1409 ram_addr <= local_ram_start_addr + 9; -- Address of LOW word of Event ID
1410 state_write <= WR_GET_EVT_ID_WAIT2;
1411 when WR_GET_EVT_ID_WAIT2 =>
1412 state_write <= WR_GET_EVT_ID2;
1413 when WR_GET_EVT_ID2 =>
1414 state_sig <= X"43";
1415 event_number(15 downto 0) <= ram_data;
1416 mod7_start <= '1';
1417 if (mod7_valid = '0') then
1418 state_write <= WR_MOD7_STARTED;
1419 else
1420 state_write <= WR_GET_EVT_ID2;
1421 end if;
1422
1423 when WR_MOD7_STARTED =>
1424 state_sig <= X"44";
1425 if (mod7_started = '1') then
1426 mod7_start <= '0';
1427 state_write <= WR_WAIT_FOR_MOD7;
1428 end if;
1429
1430 when WR_WAIT_FOR_MOD7 =>
1431 state_sig <= X"45";
1432 next_state_tmp <= next_state;
1433 if (mod7_valid = '1') then
1434 if (socket_send_mode = '1') then -- send via all sockets
1435 local_socket_nr <= "001";
1436 else -- only send via socket 0\
1437 local_socket_nr <= "000";
1438 end if;
1439
1440 data_cnt <= 0;
1441 state_write <= WR_CHECK_FOR_FIFO_SPACE_01;
1442 else
1443 state_write <= WR_WAIT_FOR_MOD7;
1444 end if;
1445
1446 -- Check FIFO Size
1447 when WR_CHECK_FOR_FIFO_SPACE_01 =>
1448 state_sig <= X"46";
1449 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
1450 state_init <= READ_REG;
1451 next_state <= WRITE_DATA;
1452 state_write <= WR_CHECK_FOR_FIFO_SPACE_02;
1453 when WR_CHECK_FOR_FIFO_SPACE_02 =>
1454 state_sig <= X"47";
1455 socket_tx_free (16) <= data_read(0);
1456 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
1457 state_init <= READ_REG;
1458 next_state <= WRITE_DATA;
1459 state_write <= WR_CHECK_FOR_FIFO_SPACE_03;
1460 when WR_CHECK_FOR_FIFO_SPACE_03 =>
1461 state_sig <= X"48";
1462 socket_tx_free (15 downto 0) <= data_read;
1463 state_write <= WR_CHECK_FOR_FIFO_SPACE_04;
1464 when WR_CHECK_FOR_FIFO_SPACE_04 =>
1465 state_sig <= X"49";
1466 socket_tx_free_out <= socket_tx_free;
1467-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
1468 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
1469
1470 state_write <= WR_CHECK_FOR_FIFO_SPACE_01;
1471 else
1472 if (local_write_header_flag = '1') then
1473 state_write <= WR_FIFO;
1474 else
1475 state_write <= WR_ADC;
1476 end if;
1477 end if;
1478
1479 -- Fill FIFO
1480
1481 -- Write Header
1482 when WR_FIFO =>
1483 state_sig <= X"4A";
1484 ram_addr <= local_ram_start_addr + local_ram_addr;
1485 state_write <= WR_FIFO1;
1486 when WR_FIFO1 =>
1487 state_sig <= X"4B";
1488 data_cnt <= data_cnt + 1;
1489 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
1490 local_ram_addr <= local_ram_addr + 1;
1491-- if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
1492-- local_ram_addr <= local_ram_addr + 2;
1493-- end if;
1494-- if (data_cnt = 9) then -- skip empty words
1495-- local_ram_addr <= local_ram_addr + 4;
1496-- end if;
1497 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1498 ram_access <= '1';
1499 state_init <= WRITE_REG;
1500 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1;
1501 next_state <= WRITE_DATA;
1502 state_write <= WR_FIFO;
1503 else
1504 state_write <= WR_ADC;
1505 end if;
1506 -- End Write Header
1507
1508 -- Write ADC-Data
1509 ---- Start...
1510 when WR_ADC =>
1511 state_sig <= X"4C";
1512 adc_data_addr <= local_ram_start_addr + local_ram_addr;
1513 drs_cnt <= 0;
1514 channel_cnt <= 1;
1515 data_cnt <= 0;
1516 roi_max <= (others => '0');
1517 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER;
1518 state_write <= WR_ADC1;
1519
1520 ---- Write Channel
1521 when WR_ADC1 =>
1522 state_sig <= X"4D";
1523 -- read ROI and set end of Channel-Data
1524 if (data_cnt = POSITION_OF_ROI_IN_CHANNEL_HEADER) then
1525 data_end <= conv_integer (ram_data) + CHANNEL_HEADER_SIZE;
1526 if (ram_data > roi_max) then
1527 roi_max <= ram_data (10 downto 0);
1528 end if;
1529 end if;
1530 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
1531 state_write <= WR_ADC2;
1532 when WR_ADC2 =>
1533
1534 if (data_cnt < data_end) then
1535 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1536 ram_access <= '1';
1537 state_init <= WRITE_REG;
1538 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1;
1539 next_state <= WRITE_DATA;
1540 data_cnt <= data_cnt + 1;
1541 state_write <= WR_ADC1;
1542 else
1543 -- Next DRS
1544 if (drs_cnt < 3) then
1545 drs_cnt <= drs_cnt + 1;
1546 data_cnt <= 0;
1547 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER;
1548 state_write <= WR_ADC1;
1549 else
1550 -- Next Channel
1551 if (channel_cnt < local_fifo_channels) then
1552 channel_cnt <= channel_cnt + 1;
1553 roi_max <= (others => '0');
1554 drs_cnt <= 0;
1555 data_cnt <= 0;
1556 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER;
1557 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4);
1558 state_write <= WR_ADC1;
1559 else
1560 -- Ready
1561 if (local_write_end_flag = '1') then
1562 state_write <= WR_ENDFLAG;
1563 else
1564 state_write <= WR_05a;
1565 end if;
1566 end if;
1567 end if;
1568 end if;
1569 -- End Write ADC-Data
1570
1571 -- Write End Package Flag
1572 when WR_ENDFLAG =>
1573 state_sig <= X"4F";
1574 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4);
1575 state_write <= WR_ENDFLAG1;
1576 when WR_ENDFLAG1 =>
1577 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1578 ram_access <= '1';
1579 state_init <= WRITE_REG;
1580 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1;
1581 next_state <= WRITE_DATA;
1582 state_write <= WR_ENDFLAG2;
1583 when WR_ENDFLAG2 =>
1584 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1;
1585 state_write <= WR_ENDFLAG3;
1586 when WR_ENDFLAG3 =>
1587 state_init <= WRITE_REG;
1588 next_state <= WRITE_DATA;
1589 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1;
1590 state_write <= WR_05a;
1591
1592 -- End Write End Package Flag
1593
1594 -- Wait????
1595 when WR_05a =>
1596 state_sig <= X"4E";
1597 if (wait_cntr < 10) then -- 3000 works???
1598 wait_cntr <= wait_cntr + 1;
1599 else
1600 wait_cntr <= 0;
1601 state_write <= WR_05b;
1602 end if;
1603 when WR_05b =>
1604 state_write <= WR_05_PREPARE_LENGTH_INFO;
1605
1606 --Send FIFO
1607 when WR_05_PREPARE_LENGTH_INFO =>
1608 --number_of_words_written_to_fifo <= number_of_words_written_to_fifo - 1;
1609 state_init <= WRITE_DATA;
1610 state_write <= WR_05_POSTPREPARE_LENGTH_INFO;
1611
1612
1613 when WR_05_POSTPREPARE_LENGTH_INFO =>
1614 number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0';
1615 state_init <= WRITE_DATA;
1616 state_write <= WR_05;
1617
1618 when WR_05 =>
1619 ram_access <= '0';
1620 state_sig <= X"50";
1621 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
1622 par_data <= (0 => write_length_bytes (16), others => '0');
1623 --par_data <= (0 => number_of_bytes_written_to_fifo(16), others => '0');
1624 state_init <= WRITE_REG;
1625 state_write <= WR_06;
1626 when WR_06 =>
1627 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
1628 par_data <= write_length_bytes (15 downto 0);
1629 --par_data <= number_of_bytes_written_to_fifo(15 downto 0);
1630
1631 -- prepare this value here, so I have it in the next state.
1632 wait_before_send_counter_goal <= FADid*50*MICROSEC_TO_WAIT_BEFORE_SEND;
1633
1634 state_init <= WRITE_REG;
1635 state_write <= WR_07;
1636
1637 when WR_07 =>
1638 number_of_words_written_to_fifo <= (others => '0');
1639 state_sig <= X"51";
1640 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
1641 par_data <= X"0020"; -- Send
1642 state_init <= WRITE_REG;
1643 state_write <= WR_ACK;
1644 when WR_ACK => -- handshake with MM
1645 data_valid_ack <= '1';
1646 state_write <= WR_WAIT_FOR_ACK;
1647 when WR_WAIT_FOR_ACK => -- handshake ACK with MM
1648 state_write <= WR_WAIT_FOR_ACK;
1649 if (data_valid_sr(1) = '0') then
1650 data_valid_ack <= '0';
1651
1652 if (local_write_end_flag = '1') then
1653 -- the last package was just written, and we can go back to the main state
1654 state_init <= MAIN;
1655 state_write <= WR_START;
1656 else
1657 -- we just wrote, a part of an event and should not go back to main, in order to avoid
1658 -- intermediate reconfiguration of the MM, in case an 'EXECUTE' command just arrived.
1659 -- but neither we should not go back to MAIN2, because data_valid is still low, as part of the MM-handshake.
1660 -- so we have to wait, until data_valid goes back high.
1661 -- if it never goes high, this can be a deadlock again, but it MUST go high,
1662 -- because we did not send away the entire event, yet.
1663 state_init <= WRITE_DATA;
1664 state_write <= WAIT_FOR_DATA_VALID_HIGH_AGAIN;
1665 end if;
1666
1667
1668 end if;
1669
1670 when WAIT_FOR_DATA_VALID_HIGH_AGAIN =>
1671 if (data_valid_sr(1) = '1') then
1672 state_init <= MAIN2;
1673 state_write <= WR_START;
1674 end if;
1675
1676 when others =>
1677 state_sig <= X"4F";
1678 end case;
1679 -- End WRITE_DATA
1680
1681 when READ_REG =>
1682 --state_sig <= X"50";
1683 case count is
1684 when "000" =>
1685 cs <= '0';
1686 rd <= '0';
1687 wr <= '1';
1688 data <= (others => 'Z'); -- !!!!!!!!!!
1689 count <= "001";
1690 addr <= par_addr;
1691 when "001" =>
1692 count <= "010";
1693 when "010" =>
1694 count <= "100";
1695 when "100" =>
1696 data_read <= data;
1697 count <= "110";
1698 when "110" =>
1699 count <= "111";
1700 when "111" =>
1701 cs <= '1';
1702 rd <= '1';
1703 count <= "000";
1704 state_init <= next_state;
1705 when others =>
1706 null;
1707 end case;
1708
1709 when WRITE_REG =>
1710 --state_sig <= X"60";
1711 case count is
1712 when "000" =>
1713 cs <= '0';
1714 wr <= '0';
1715 rd <= '1';
1716 addr <= par_addr;
1717 if (ram_access = '1') then
1718 data <= ram_data;
1719 else
1720 data <= par_data;
1721 end if;
1722 count <= "100";
1723 when "100" =>
1724 count <= "101";
1725 when "101" =>
1726 count <= "110";
1727 when "110" =>
1728 cs <= '1';
1729 wr <= '1';
1730 state_init <= next_state;
1731 count <= "000";
1732 when others =>
1733 state_sig <= X"E0";
1734 null;
1735 end case;
1736
1737 when others =>
1738 state_sig <= X"F0";
1739 null;
1740 end case;
1741 end if; -- int_flag = '0'
1742
1743 end if; -- rising_edge (clk)
1744
1745 end process w5300_proc;
1746
1747
1748
1749 --signal wait_for_sockets_closed_counter_overflow : std_logic := '0';
1750 --signal wait_for_sockets_closed_counter_enable : std_logic := '0';
1751 --signal wfscc_1 : integer range 0 to 50000 := 0;
1752 --signal wfscc_2 : integer range 0 to 2000 := 0;
1753 counter_before_reset_proc : process (clk)
1754 begin
1755 if rising_edge (clk) then
1756 if (wait_for_sockets_closed_counter_enable = '1') then
1757 wait_for_sockets_closed_counter_overflow <= '0';
1758 if (wfscc_1 = 50000) then
1759 if (wfscc_2 = 20000) then
1760 wait_for_sockets_closed_counter_overflow <= '1';
1761 wfscc_2 <= 20000;
1762 wfscc_1 <= 50000;
1763 else
1764 wfscc_2 <= wfscc_2 + 1;
1765 wfscc_1 <= 0;
1766 end if;
1767 else
1768 wfscc_1 <= wfscc_1 + 1;
1769 end if;
1770 else
1771 wfscc_1 <= 0;
1772 wfscc_2 <= 0;
1773 wait_for_sockets_closed_counter_overflow <= '0';
1774 end if;
1775
1776 end if;
1777 end process counter_before_reset_proc;
1778
1779 single_trigger_gen : process (clk)
1780 begin
1781 if (rising_edge(clk)) then
1782
1783 trigger_input_sr <= trigger_input_sr(0) & single_trigger_sig;
1784
1785 if (trigger_input_sr = "01" and single_triggers_to_produce < 1023) then
1786 single_triggers_to_produce <= single_triggers_to_produce + 1;
1787 end if;
1788
1789
1790 case single_trigger_gen_state is
1791 when IDLE =>
1792 if ( (data_generator_idle_sr(1) = '1') and (data_ram_not_full_sr(1) = '1') and (single_triggers_to_produce > 0) ) then
1793 --s_trigger <= '1';
1794 -- if just at the same moment a trigger is produces a new one comes in, the number of triggers to be produced is not decreased.
1795 if (trigger_input_sr = "01") then
1796 single_triggers_to_produce <= single_triggers_to_produce;
1797 else
1798 single_triggers_to_produce <= single_triggers_to_produce - 1;
1799 end if;
1800 single_trigger_gen_state <= TRIGGERED;
1801 end if;
1802
1803 when TRIGGERED =>
1804 if ( (data_generator_idle_sr(1) = '0') or (data_ram_not_full_sr(1) = '0' ) ) then
1805 --s_trigger <= '0';
1806 single_trigger_gen_state <= IDLE;
1807 end if;
1808
1809 when others =>
1810 --s_trigger <= '0';
1811
1812 end case; --single_trigger_gen_state
1813
1814 end if; -- rising edge clk
1815
1816 end process single_trigger_gen;
1817
1818
1819
1820end Behavioral;
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