source: firmware/FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd@ 18341

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*28 (Net
uid 2407,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 40
suid 57,0
i "'0'"
)
declText (MLText
uid 2408,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,35000,71500,35800"
st "RSRLOAD               : std_logic                      := '0'"
)
)
*29 (PortIoOut
uid 2415,0
shape (CompositeShape
uid 2416,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2417,0
sl 0
ro 90
xt "19000,110625,20500,111375"
)
(Line
uid 2418,0
sl 0
ro 90
xt "20500,111000,21000,111000"
pts [
"21000,111000"
"20500,111000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2419,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2420,0
va (VaSet
)
xt "13800,110500,18000,111500"
st "RSRLOAD"
ju 2
blo "18000,111300"
tm "WireNameMgr"
)
)
)
*30 (Net
uid 3025,0
decl (Decl
n "DAC_CS"
t "std_logic"
o 22
suid 66,0
)
declText (MLText
uid 3026,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,20600,57000,21400"
st "DAC_CS                : std_logic"
)
)
*31 (PortIoOut
uid 3153,0
shape (CompositeShape
uid 3154,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3155,0
sl 0
ro 90
xt "-3000,70625,-1500,71375"
)
(Line
uid 3156,0
sl 0
ro 90
xt "-1500,71000,-1000,71000"
pts [
"-1000,71000"
"-1500,71000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3157,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3158,0
va (VaSet
)
xt "-6900,70500,-4000,71500"
st "A_CLK"
ju 2
blo "-4000,71300"
tm "WireNameMgr"
)
)
)
*32 (Net
uid 3216,0
decl (Decl
n "X_50M"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 17
suid 67,0
)
declText (MLText
uid 3217,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,16600,57000,17400"
st "X_50M                 : STD_LOGIC"
)
)
*33 (Net
uid 3226,0
decl (Decl
n "TRG"
t "STD_LOGIC"
o 15
suid 68,0
)
declText (MLText
uid 3227,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,15000,57000,15800"
st "TRG                   : STD_LOGIC"
)
)
*34 (HdlText
uid 3248,0
optionalChildren [
*35 (EmbeddedText
uid 3254,0
commentText (CommentText
uid 3255,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 3256,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "-14000,63000,12000,69000"
)
oxt "0,0,18000,5000"
text (MLText
uid 3257,0
va (VaSet
)
xt "-13800,63200,-8900,69200"
st "
A_CLK <= (
ADC_CLK,
ADC_CLK,
ADC_CLK,
ADC_CLK
);

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 6000
visibleWidth 26000
)
)
)
]
shape (Rectangle
uid 3249,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "5000,70000,13000,73000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3250,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*36 (Text
uid 3251,0
va (VaSet
font "Arial,8,1"
)
xt "6150,70000,10350,71000"
st "ADC_CLK"
blo "6150,70800"
tm "HdlTextNameMgr"
)
*37 (Text
uid 3252,0
va (VaSet
font "Arial,8,1"
)
xt "6150,71000,6950,72000"
st "2"
blo "6150,71800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 3253,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "5250,71250,6750,72750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*38 (Net
uid 3266,0
decl (Decl
n "A_CLK"
t "std_logic_vector"
b "(3 downto 0)"
o 21
suid 71,0
)
declText (MLText
uid 3267,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,19800,67000,20600"
st "A_CLK                 : std_logic_vector(3 downto 0)"
)
)
*39 (PortIoOut
uid 3284,0
shape (CompositeShape
uid 3285,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3286,0
sl 0
ro 90
xt "19000,89625,20500,90375"
)
(Line
uid 3287,0
sl 0
ro 90
xt "20500,90000,21000,90000"
pts [
"21000,90000"
"20500,90000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3288,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3289,0
va (VaSet
)
xt "14300,89500,18000,90500"
st "OE_ADC"
ju 2
blo "18000,90300"
tm "WireNameMgr"
)
)
)
*40 (Net
uid 3290,0
decl (Decl
n "OE_ADC"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 32
suid 73,0
)
declText (MLText
uid 3291,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,28600,57000,29400"
st "OE_ADC                : STD_LOGIC"
)
)
*41 (PortIoIn
uid 3292,0
shape (CompositeShape
uid 3293,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3294,0
sl 0
ro 270
xt "19000,88625,20500,89375"
)
(Line
uid 3295,0
sl 0
ro 270
xt "20500,89000,21000,89000"
pts [
"20500,89000"
"21000,89000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3296,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3297,0
va (VaSet
)
xt "14900,88500,18000,89500"
st "A_OTR"
ju 2
blo "18000,89300"
tm "WireNameMgr"
)
)
)
*42 (Net
uid 3298,0
decl (Decl
n "A_OTR"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 74,0
)
declText (MLText
uid 3299,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,7000,67000,7800"
st "A_OTR                 : std_logic_vector(3 DOWNTO 0)"
)
)
*43 (HdlText
uid 3300,0
optionalChildren [
*44 (EmbeddedText
uid 3306,0
commentText (CommentText
uid 3307,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 3308,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "19000,99000,38000,101000"
)
oxt "0,0,18000,5000"
text (MLText
uid 3309,0
va (VaSet
)
xt "19200,99200,37300,100200"
st "
adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 19000
)
)
)
]
shape (Rectangle
uid 3301,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "24000,94000,30000,99000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3302,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*45 (Text
uid 3303,0
va (VaSet
font "Arial,8,1"
)
xt "27150,95000,31750,96000"
st "ADC_DATA"
blo "27150,95800"
tm "HdlTextNameMgr"
)
*46 (Text
uid 3304,0
va (VaSet
font "Arial,8,1"
)
xt "27150,96000,27950,97000"
st "3"
blo "27150,96800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 3305,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "24250,97250,25750,98750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*47 (PortIoIn
uid 3310,0
shape (CompositeShape
uid 3311,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3312,0
sl 0
ro 270
xt "19000,94625,20500,95375"
)
(Line
uid 3313,0
sl 0
ro 270
xt "20500,95000,21000,95000"
pts [
"20500,95000"
"21000,95000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3314,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3315,0
va (VaSet
)
xt "15400,94500,18000,95500"
st "A0_D"
ju 2
blo "18000,95300"
tm "WireNameMgr"
)
)
)
*48 (PortIoIn
uid 3332,0
shape (CompositeShape
uid 3333,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3334,0
sl 0
ro 270
xt "19000,95625,20500,96375"
)
(Line
uid 3335,0
sl 0
ro 270
xt "20500,96000,21000,96000"
pts [
"20500,96000"
"21000,96000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3336,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3337,0
va (VaSet
)
xt "15500,95500,18000,96500"
st "A1_D"
ju 2
blo "18000,96300"
tm "WireNameMgr"
)
)
)
*49 (PortIoIn
uid 3338,0
shape (CompositeShape
uid 3339,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3340,0
sl 0
ro 270
xt "19000,96625,20500,97375"
)
(Line
uid 3341,0
sl 0
ro 270
xt "20500,97000,21000,97000"
pts [
"20500,97000"
"21000,97000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3342,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3343,0
va (VaSet
)
xt "15400,96500,18000,97500"
st "A2_D"
ju 2
blo "18000,97300"
tm "WireNameMgr"
)
)
)
*50 (PortIoIn
uid 3344,0
shape (CompositeShape
uid 3345,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3346,0
sl 0
ro 270
xt "19000,97625,20500,98375"
)
(Line
uid 3347,0
sl 0
ro 270
xt "20500,98000,21000,98000"
pts [
"20500,98000"
"21000,98000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3348,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3349,0
va (VaSet
)
xt "15400,97500,18000,98500"
st "A3_D"
ju 2
blo "18000,98300"
tm "WireNameMgr"
)
)
)
*51 (Net
uid 3374,0
decl (Decl
n "A0_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 1
suid 79,0
)
declText (MLText
uid 3375,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,3800,67500,4600"
st "A0_D                  : std_logic_vector(11 DOWNTO 0)"
)
)
*52 (Net
uid 3376,0
decl (Decl
n "A1_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 2
suid 80,0
)
declText (MLText
uid 3377,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,4600,67500,5400"
st "A1_D                  : std_logic_vector(11 DOWNTO 0)"
)
)
*53 (Net
uid 3378,0
decl (Decl
n "A2_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 3
suid 81,0
)
declText (MLText
uid 3379,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,5400,67500,6200"
st "A2_D                  : std_logic_vector(11 DOWNTO 0)"
)
)
*54 (Net
uid 3380,0
decl (Decl
n "A3_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 4
suid 82,0
)
declText (MLText
uid 3381,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,6200,67500,7000"
st "A3_D                  : std_logic_vector(11 DOWNTO 0)"
)
)
*55 (PortIoIn
uid 3476,0
shape (CompositeShape
uid 3477,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3478,0
sl 0
ro 270
xt "19000,104625,20500,105375"
)
(Line
uid 3479,0
sl 0
ro 270
xt "20500,105000,21000,105000"
pts [
"20500,105000"
"21000,105000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3480,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3481,0
va (VaSet
)
xt "13200,104500,18000,105500"
st "D0_SROUT"
ju 2
blo "18000,105300"
tm "WireNameMgr"
)
)
)
*56 (PortIoIn
uid 3482,0
shape (CompositeShape
uid 3483,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3484,0
sl 0
ro 270
xt "19000,105625,20500,106375"
)
(Line
uid 3485,0
sl 0
ro 270
xt "20500,106000,21000,106000"
pts [
"20500,106000"
"21000,106000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3486,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3487,0
va (VaSet
)
xt "13300,105500,18000,106500"
st "D1_SROUT"
ju 2
blo "18000,106300"
tm "WireNameMgr"
)
)
)
*57 (PortIoIn
uid 3488,0
shape (CompositeShape
uid 3489,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3490,0
sl 0
ro 270
xt "19000,106625,20500,107375"
)
(Line
uid 3491,0
sl 0
ro 270
xt "20500,107000,21000,107000"
pts [
"20500,107000"
"21000,107000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3492,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3493,0
va (VaSet
)
xt "13200,106500,18000,107500"
st "D2_SROUT"
ju 2
blo "18000,107300"
tm "WireNameMgr"
)
)
)
*58 (PortIoIn
uid 3494,0
shape (CompositeShape
uid 3495,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3496,0
sl 0
ro 270
xt "19000,107625,20500,108375"
)
(Line
uid 3497,0
sl 0
ro 270
xt "20500,108000,21000,108000"
pts [
"20500,108000"
"21000,108000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3498,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3499,0
va (VaSet
)
xt "13200,107500,18000,108500"
st "D3_SROUT"
ju 2
blo "18000,108300"
tm "WireNameMgr"
)
)
)
*59 (Net
uid 3500,0
decl (Decl
n "D0_SROUT"
t "std_logic"
o 6
suid 91,0
)
declText (MLText
uid 3501,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,7800,57000,8600"
st "D0_SROUT              : std_logic"
)
)
*60 (Net
uid 3502,0
decl (Decl
n "D1_SROUT"
t "std_logic"
o 7
suid 92,0
)
declText (MLText
uid 3503,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,8600,57000,9400"
st "D1_SROUT              : std_logic"
)
)
*61 (Net
uid 3504,0
decl (Decl
n "D2_SROUT"
t "std_logic"
o 8
suid 93,0
)
declText (MLText
uid 3505,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,9400,57000,10200"
st "D2_SROUT              : std_logic"
)
)
*62 (Net
uid 3506,0
decl (Decl
n "D3_SROUT"
t "std_logic"
o 9
suid 94,0
)
declText (MLText
uid 3507,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,10200,57000,11000"
st "D3_SROUT              : std_logic"
)
)
*63 (PortIoOut
uid 3508,0
shape (CompositeShape
uid 3509,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3510,0
sl 0
ro 90
xt "19000,108625,20500,109375"
)
(Line
uid 3511,0
sl 0
ro 90
xt "20500,109000,21000,109000"
pts [
"21000,109000"
"20500,109000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3512,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3513,0
va (VaSet
)
xt "15900,108500,18000,109500"
st "D_A"
ju 2
blo "18000,109300"
tm "WireNameMgr"
)
)
)
*64 (Net
uid 3514,0
decl (Decl
n "D_A"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 26
suid 95,0
i "(others => '0')"
)
declText (MLText
uid 3515,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,23800,77500,24600"
st "D_A                   : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
)
)
*65 (PortIoOut
uid 3516,0
shape (CompositeShape
uid 3517,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3518,0
sl 0
ro 90
xt "19000,109625,20500,110375"
)
(Line
uid 3519,0
sl 0
ro 90
xt "20500,110000,21000,110000"
pts [
"21000,110000"
"20500,110000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3520,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3521,0
va (VaSet
)
xt "14200,109500,18000,110500"
st "DWRITE"
ju 2
blo "18000,110300"
tm "WireNameMgr"
)
)
)
*66 (Net
uid 3522,0
decl (Decl
n "DWRITE"
t "std_logic"
o 25
suid 96,0
i "'0'"
)
declText (MLText
uid 3523,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,23000,71500,23800"
st "DWRITE                : std_logic                      := '0'"
)
)
*67 (PortIoOut
uid 3536,0
shape (CompositeShape
uid 3537,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3538,0
sl 0
ro 270
xt "97500,83625,99000,84375"
)
(Line
uid 3539,0
sl 0
ro 270
xt "97000,84000,97500,84000"
pts [
"97000,84000"
"97500,84000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3540,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3541,0
va (VaSet
)
xt "100000,83500,103700,84500"
st "DAC_CS"
blo "100000,84300"
tm "WireNameMgr"
)
)
)
*68 (PortIoOut
uid 3624,0
shape (CompositeShape
uid 3625,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3626,0
sl 0
ro 270
xt "99500,96625,101000,97375"
)
(Line
uid 3627,0
sl 0
ro 270
xt "99000,97000,99500,97000"
pts [
"99000,97000"
"99500,97000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3628,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3629,0
va (VaSet
)
xt "101750,96500,104650,97500"
st "S_CLK"
blo "101750,97300"
tm "WireNameMgr"
)
)
)
*69 (Net
uid 3630,0
decl (Decl
n "S_CLK"
t "std_logic"
o 42
suid 105,0
)
declText (MLText
uid 3631,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,36600,57000,37400"
st "S_CLK                 : std_logic"
)
)
*70 (Net
uid 3632,0
decl (Decl
n "W_A"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 45
suid 106,0
)
declText (MLText
uid 3633,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,39000,67000,39800"
st "W_A                   : std_logic_vector(9 DOWNTO 0)"
)
)
*71 (Net
uid 3634,0
decl (Decl
n "W_D"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 52
suid 107,0
)
declText (MLText
uid 3635,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,44600,67500,45400"
st "W_D                   : std_logic_vector(15 DOWNTO 0)"
)
)
*72 (Net
uid 3636,0
decl (Decl
n "W_RES"
t "std_logic"
o 48
suid 108,0
i "'1'"
)
declText (MLText
uid 3637,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,41400,71500,42200"
st "W_RES                 : std_logic                      := '1'"
)
)
*73 (Net
uid 3638,0
decl (Decl
n "W_RD"
t "std_logic"
o 47
suid 109,0
i "'1'"
)
declText (MLText
uid 3639,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,40600,71500,41400"
st "W_RD                  : std_logic                      := '1'"
)
)
*74 (Net
uid 3640,0
decl (Decl
n "W_WR"
t "std_logic"
o 50
suid 110,0
i "'1'"
)
declText (MLText
uid 3641,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,43000,71500,43800"
st "W_WR                  : std_logic                      := '1'"
)
)
*75 (Net
uid 3642,0
decl (Decl
n "W_INT"
t "std_logic"
o 16
suid 111,0
)
declText (MLText
uid 3643,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,15800,57000,16600"
st "W_INT                 : std_logic"
)
)
*76 (Net
uid 3644,0
decl (Decl
n "W_CS"
t "std_logic"
o 46
suid 112,0
i "'1'"
)
declText (MLText
uid 3645,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,39800,71500,40600"
st "W_CS                  : std_logic                      := '1'"
)
)
*77 (PortIoInOut
uid 3674,0
shape (CompositeShape
uid 3675,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
uid 3676,0
sl 0
xt "90500,98625,92000,99375"
)
(Line
uid 3677,0
sl 0
xt "90000,99000,90500,99000"
pts [
"90000,99000"
"90500,99000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3678,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3679,0
va (VaSet
)
xt "93000,98500,95700,99500"
st "MISO"
blo "93000,99300"
tm "WireNameMgr"
)
)
)
*78 (Net
uid 3680,0
decl (Decl
n "MOSI"
t "std_logic"
o 31
suid 113,0
i "'0'"
)
declText (MLText
uid 3681,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,27800,71500,28600"
st "MOSI                  : std_logic                      := '0'"
)
)
*79 (PortIoOut
uid 3688,0
shape (CompositeShape
uid 3689,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3690,0
sl 0
ro 270
xt "99500,99625,101000,100375"
)
(Line
uid 3691,0
sl 0
ro 270
xt "99000,100000,99500,100000"
pts [
"99000,100000"
"99500,100000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3692,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3693,0
va (VaSet
)
xt "102000,99500,104700,100500"
st "MOSI"
blo "102000,100300"
tm "WireNameMgr"
)
)
)
*80 (Net
uid 3694,0
decl (Decl
n "MISO"
t "std_logic"
preAdd 0
posAdd 0
o 51
suid 114,0
)
declText (MLText
uid 3695,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,43800,57000,44600"
st "MISO                  : std_logic"
)
)
*81 (PortIoOut
uid 3716,0
shape (CompositeShape
uid 3717,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3718,0
sl 0
ro 270
xt "137500,130625,139000,131375"
)
(Line
uid 3719,0
sl 0
ro 270
xt "137000,131000,137500,131000"
pts [
"137000,131000"
"137500,131000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3720,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3721,0
va (VaSet
)
xt "140000,130500,146100,131500"
st "RS485_C_DE"
blo "140000,131300"
tm "WireNameMgr"
)
)
)
*82 (PortIoOut
uid 3722,0
shape (CompositeShape
uid 3723,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3724,0
sl 0
ro 270
xt "137500,131625,139000,132375"
)
(Line
uid 3725,0
sl 0
ro 270
xt "137000,132000,137500,132000"
pts [
"137000,132000"
"137500,132000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3726,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3727,0
va (VaSet
)
xt "140000,131500,146200,132500"
st "RS485_C_DO"
blo "140000,132300"
tm "WireNameMgr"
)
)
)
*83 (PortIoOut
uid 3728,0
shape (CompositeShape
uid 3729,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3730,0
sl 0
ro 270
xt "85500,147625,87000,148375"
)
(Line
uid 3731,0
sl 0
ro 270
xt "85000,148000,85500,148000"
pts [
"85000,148000"
"85500,148000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3732,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3733,0
va (VaSet
)
xt "88000,147500,94000,148500"
st "RS485_E_RE"
blo "88000,148300"
tm "WireNameMgr"
)
)
)
*84 (PortIoOut
uid 3734,0
shape (CompositeShape
uid 3735,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3736,0
sl 0
ro 270
xt "85500,146625,87000,147375"
)
(Line
uid 3737,0
sl 0
ro 270
xt "85000,147000,85500,147000"
pts [
"85000,147000"
"85500,147000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3738,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3739,0
va (VaSet
)
xt "88000,146500,94100,147500"
st "RS485_E_DE"
blo "88000,147300"
tm "WireNameMgr"
)
)
)
*85 (PortIoOut
uid 3740,0
shape (CompositeShape
uid 3741,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3742,0
sl 0
ro 270
xt "82500,120625,84000,121375"
)
(Line
uid 3743,0
sl 0
ro 270
xt "82000,121000,82500,121000"
pts [
"82000,121000"
"82500,121000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3744,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3745,0
va (VaSet
)
xt "85000,120500,89100,121500"
st "DENABLE"
blo "85000,121300"
tm "WireNameMgr"
)
)
)
*86 (PortIoOut
uid 3752,0
shape (CompositeShape
uid 3753,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3754,0
sl 0
ro 270
xt "137500,138625,139000,139375"
)
(Line
uid 3755,0
sl 0
ro 270
xt "137000,139000,137500,139000"
pts [
"137000,139000"
"137500,139000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3756,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3757,0
va (VaSet
)
xt "140000,138500,143000,139500"
st "EE_CS"
blo "140000,139300"
tm "WireNameMgr"
)
)
)
*87 (Net
uid 3866,0
decl (Decl
n "RS485_C_RE"
t "std_logic"
o 36
suid 127,0
)
declText (MLText
uid 3867,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,31800,57000,32600"
st "RS485_C_RE            : std_logic"
)
)
*88 (Net
uid 3868,0
decl (Decl
n "RS485_C_DE"
t "std_logic"
o 34
suid 128,0
)
declText (MLText
uid 3869,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,30200,57000,31000"
st "RS485_C_DE            : std_logic"
)
)
*89 (Net
uid 3870,0
decl (Decl
n "RS485_E_RE"
t "std_logic"
o 39
suid 129,0
)
declText (MLText
uid 3871,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,34200,57000,35000"
st "RS485_E_RE            : std_logic"
)
)
*90 (Net
uid 3872,0
decl (Decl
n "RS485_E_DE"
t "std_logic"
o 37
suid 130,0
)
declText (MLText
uid 3873,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,32600,57000,33400"
st "RS485_E_DE            : std_logic"
)
)
*91 (Net
uid 3874,0
decl (Decl
n "DENABLE"
t "std_logic"
o 23
suid 131,0
i "'0'"
)
declText (MLText
uid 3875,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,21400,71500,22200"
st "DENABLE               : std_logic                      := '0'"
)
)
*92 (Net
uid 3878,0
decl (Decl
n "EE_CS"
t "std_logic"
o 29
suid 133,0
)
declText (MLText
uid 3879,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,26200,57000,27000"
st "EE_CS                 : std_logic"
)
)
*93 (PortIoOut
uid 4916,0
shape (CompositeShape
uid 4917,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4918,0
sl 0
ro 270
xt "137500,117625,139000,118375"
)
(Line
uid 4919,0
sl 0
ro 270
xt "137000,118000,137500,118000"
pts [
"137000,118000"
"137500,118000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4920,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4921,0
va (VaSet
)
xt "140000,117500,142000,118500"
st "D_T"
blo "140000,118300"
tm "WireNameMgr"
)
)
)
*94 (Net
uid 5320,0
decl (Decl
n "D_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 27
suid 141,0
i "(OTHERS => '0')"
)
declText (MLText
uid 5321,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,24600,77500,25400"
st "D_T                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
)
)
*95 (PortIoOut
uid 6874,0
shape (CompositeShape
uid 6875,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6876,0
sl 0
ro 270
xt "137500,127625,139000,128375"
)
(Line
uid 6877,0
sl 0
ro 270
xt "137000,128000,137500,128000"
pts [
"137000,128000"
"137500,128000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6878,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6879,0
va (VaSet
)
xt "140000,127500,142500,128500"
st "D_T2"
blo "140000,128300"
tm "WireNameMgr"
)
)
)
*96 (Net
uid 6886,0
decl (Decl
n "D_T2"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 28
suid 154,0
i "(others => '0')"
)
declText (MLText
uid 6887,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,25400,77500,26200"
st "D_T2                  : std_logic_vector(1 DOWNTO 0)   := (others => '0')"
)
)
*97 (PortIoOut
uid 7138,0
shape (CompositeShape
uid 7139,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 7140,0
sl 0
ro 270
xt "137500,120625,139000,121375"
)
(Line
uid 7141,0
sl 0
ro 270
xt "137000,121000,137500,121000"
pts [
"137000,121000"
"137500,121000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 7142,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7143,0
va (VaSet
)
xt "140000,120500,142400,121500"
st "A1_T"
blo "140000,121300"
tm "WireNameMgr"
)
)
)
*98 (Net
uid 7150,0
decl (Decl
n "A1_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 19
suid 155,0
i "(OTHERS => '0')"
)
declText (MLText
uid 7151,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,18200,77500,19000"
st "A1_T                  : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
)
)
*99 (Net
uid 9500,0
decl (Decl
n "CLK_50"
t "std_logic"
o 54
suid 163,0
)
declText (MLText
uid 9501,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,47200,61000,48000"
st "SIGNAL CLK_50                : std_logic"
)
)
*100 (PortIoOut
uid 10296,0
shape (CompositeShape
uid 10297,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 10298,0
sl 0
ro 270
xt "137500,119625,139000,120375"
)
(Line
uid 10299,0
sl 0
ro 270
xt "137000,120000,137500,120000"
pts [
"137000,120000"
"137500,120000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 10300,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10301,0
va (VaSet
)
xt "140000,119500,142500,120500"
st "A0_T"
blo "140000,120300"
tm "WireNameMgr"
)
)
)
*101 (Net
uid 10308,0
decl (Decl
n "A0_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 18
suid 166,0
i "(others => '0')"
)
declText (MLText
uid 10309,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,17400,77500,18200"
st "A0_T                  : std_logic_vector(7 DOWNTO 0)   := (others => '0')"
)
)
*102 (HdlText
uid 10310,0
optionalChildren [
*103 (EmbeddedText
uid 10316,0
commentText (CommentText
uid 10317,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 10318,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "109000,64000,141000,106000"
)
oxt "0,0,18000,5000"
text (MLText
uid 10319,0
va (VaSet
)
xt "109200,64200,128500,106200"
st "
-- testpins D_T2 are used as MAX3485 outputs.

--D_T <= (others => '0');
D_T <= w5300_state;
--D_T2(0) <= debug_data_valid;
D_T2(0) <= debug_data_ram_empty;
--D_T2(1) <= socket_tx_free_out(16);

D_T2(1) <= TRG_V;
--D_T2 <= ( others => '0' );


A0_T <= (others => '0');
A1_T <= (others => '1');


--A0_T <= DG_state;
W_T(3 downto 0) <= mem_manager_state;
--A1_T(7 downto 4) <= \"1100\";

--A0_T <= socket_tx_free_out(7 downto 0);
--A0_T <= spi_debug_16bit(7 downto 0);
--A1_T <= spi_debug_16bit(15 downto 8);
--A1_T <= socket_tx_free_out(15 downto 8);

-- check SPI interfac
--A1_T(7) <= sclk;
--A1_T(6) <= MISO;
--A1_T(5) <= mosi1;

--A1_T(4) <= dac_cs1;
--A1_T( 3 downto 0) <= sensor_cs;


--D_T(3 downto 0) <=  counter_result ( 11 downto 8);
--D_T(4) <= alarm_refclk_too_low;
--D_T(5) <= alarm_refclk_too_high;
--D_T(6) <= '0';
--D_T(7) <= '0';



-- additional MAX3485 is switched to shutdown mode
RS485_C_RE <= '1';  --inverted logic
RS485_C_DE <= '0';   
RS485_C_DO <= '0';
-- MAX3485 receiver out pit is fed out... should be HIGH-Z


-- EEPROM is not used on FAD. CS is always high.
EE_CS <= '1';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 42000
visibleWidth 32000
)
)
)
]
shape (Rectangle
uid 10311,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "126000,107000,132000,143000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 10312,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*104 (Text
uid 10313,0
va (VaSet
font "Arial,8,1"
)
xt "129150,110000,130850,111000"
st "eb3"
blo "129150,110800"
tm "HdlTextNameMgr"
)
*105 (Text
uid 10314,0
va (VaSet
font "Arial,8,1"
)
xt "129150,111000,129950,112000"
st "9"
blo "129150,111800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 10315,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "126250,141250,127750,142750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*106 (PortIoOut
uid 11104,0
shape (CompositeShape
uid 11105,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 11106,0
sl 0
ro 270
xt "137500,132625,139000,133375"
)
(Line
uid 11107,0
sl 0
ro 270
xt "137000,133000,137500,133000"
pts [
"137000,133000"
"137500,133000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 11108,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11109,0
va (VaSet
)
xt "140000,132500,146000,133500"
st "RS485_C_RE"
blo "140000,133300"
tm "WireNameMgr"
)
)
)
*107 (Net
uid 11116,0
decl (Decl
n "RS485_C_DO"
t "std_logic"
o 35
suid 198,0
)
declText (MLText
uid 11117,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,31000,57000,31800"
st "RS485_C_DO            : std_logic"
)
)
*108 (PortIoIn
uid 11508,0
shape (CompositeShape
uid 11509,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 11510,0
sl 0
ro 90
xt "85500,149625,87000,150375"
)
(Line
uid 11511,0
sl 0
ro 90
xt "85000,150000,85500,150000"
pts [
"85500,150000"
"85000,150000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 11512,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11513,0
va (VaSet
)
xt "88000,149500,94000,150500"
st "RS485_E_DI"
blo "88000,150300"
tm "WireNameMgr"
)
)
)
*109 (Net
uid 11520,0
decl (Decl
n "RS485_E_DI"
t "std_logic"
o 14
suid 200,0
)
declText (MLText
uid 11521,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,14200,57000,15000"
st "RS485_E_DI            : std_logic"
)
)
*110 (Net
uid 11534,0
decl (Decl
n "RS485_E_DO"
t "std_logic"
o 38
suid 201,0
)
declText (MLText
uid 11535,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,33400,57000,34200"
st "RS485_E_DO            : std_logic"
)
)
*111 (PortIoOut
uid 12326,0
shape (CompositeShape
uid 12327,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12328,0
sl 0
ro 270
xt "87500,139625,89000,140375"
)
(Line
uid 12329,0
sl 0
ro 270
xt "87000,140000,87500,140000"
pts [
"87000,140000"
"87500,140000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 12330,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12331,0
va (VaSet
)
xt "89000,139500,91500,140500"
st "SRIN"
blo "89000,140300"
tm "WireNameMgr"
)
)
)
*112 (Net
uid 12334,0
decl (Decl
n "SRIN"
t "std_logic"
o 41
suid 203,0
i "'0'"
)
declText (MLText
uid 12335,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,35800,71500,36600"
st "SRIN                  : std_logic                      := '0'"
)
)
*113 (PortIoOut
uid 12539,0
shape (CompositeShape
uid 12540,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12541,0
sl 0
ro 270
xt "87500,134625,89000,135375"
)
(Line
uid 12542,0
sl 0
ro 270
xt "87000,135000,87500,135000"
pts [
"87000,135000"
"87500,135000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 12543,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12544,0
va (VaSet
)
xt "90000,134500,95200,135500"
st "AMBER_LED"
blo "90000,135300"
tm "WireNameMgr"
)
)
)
*114 (PortIoOut
uid 12553,0
shape (CompositeShape
uid 12554,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12555,0
sl 0
ro 270
xt "87500,133625,89000,134375"
)
(Line
uid 12556,0
sl 0
ro 270
xt "87000,134000,87500,134000"
pts [
"87000,134000"
"87500,134000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 12557,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12558,0
va (VaSet
)
xt "90000,133500,95000,134500"
st "GREEN_LED"
blo "90000,134300"
tm "WireNameMgr"
)
)
)
*115 (PortIoOut
uid 12567,0
shape (CompositeShape
uid 12568,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12569,0
sl 0
ro 270
xt "87500,135625,89000,136375"
)
(Line
uid 12570,0
sl 0
ro 270
xt "87000,136000,87500,136000"
pts [
"87000,136000"
"87500,136000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 12571,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12572,0
va (VaSet
)
xt "90000,135500,94000,136500"
st "RED_LED"
blo "90000,136300"
tm "WireNameMgr"
)
)
)
*116 (Net
uid 12762,0
decl (Decl
n "AMBER_LED"
t "std_logic"
o 20
suid 207,0
)
declText (MLText
uid 12763,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,19000,57000,19800"
st "AMBER_LED             : std_logic"
)
)
*117 (Net
uid 12764,0
decl (Decl
n "GREEN_LED"
t "std_logic"
o 30
suid 208,0
)
declText (MLText
uid 12765,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,27000,57000,27800"
st "GREEN_LED             : std_logic"
)
)
*118 (Net
uid 12766,0
decl (Decl
n "RED_LED"
t "std_logic"
o 33
suid 209,0
)
declText (MLText
uid 12767,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,29400,57000,30200"
st "RED_LED               : std_logic"
)
)
*119 (PortIoIn
uid 13516,0
shape (CompositeShape
uid 13517,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 13518,0
sl 0
ro 270
xt "20000,80625,21500,81375"
)
(Line
uid 13519,0
sl 0
ro 270
xt "21500,81000,22000,81000"
pts [
"21500,81000"
"22000,81000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 13520,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13521,0
va (VaSet
)
xt "16700,80500,19000,81500"
st "LINE"
ju 2
blo "19000,81300"
tm "WireNameMgr"
)
)
)
*120 (Net
uid 13528,0
decl (Decl
n "LINE"
t "std_logic_vector"
b "( 5 DOWNTO 0 )"
o 12
suid 210,0
)
declText (MLText
uid 13529,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,12600,68000,13400"
st "LINE                  : std_logic_vector( 5 DOWNTO 0 )"
)
)
*121 (PortIoIn
uid 13628,0
shape (CompositeShape
uid 13629,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 13630,0
sl 0
ro 270
xt "47000,132625,48500,133375"
)
(Line
uid 13631,0
sl 0
ro 270
xt "48500,133000,49000,133000"
pts [
"48500,133000"
"49000,133000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 13632,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13633,0
va (VaSet
)
xt "42700,132500,46000,133500"
st "REFCLK"
ju 2
blo "46000,133300"
tm "WireNameMgr"
)
)
)
*122 (Net
uid 13640,0
decl (Decl
n "REFCLK"
t "std_logic"
o 13
suid 211,0
)
declText (MLText
uid 13641,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,13400,57000,14200"
st "REFCLK                : std_logic"
)
)
*123 (PortIoIn
uid 14322,0
shape (CompositeShape
uid 14323,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14324,0
sl 0
ro 270
xt "47000,131625,48500,132375"
)
(Line
uid 14325,0
sl 0
ro 270
xt "48500,132000,49000,132000"
pts [
"48500,132000"
"49000,132000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 14326,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14327,0
va (VaSet
)
xt "42900,131500,46000,132500"
st "D_T_in"
ju 2
blo "46000,132300"
tm "WireNameMgr"
)
)
)
*124 (Net
uid 14334,0
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 213,0
)
declText (MLText
uid 14335,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,11800,67000,12600"
st "D_T_in                : std_logic_vector(1 DOWNTO 0)"
)
)
*125 (Net
uid 15173,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 65
suid 215,0
i "(OTHERS => '0')"
)
declText (MLText
uid 15174,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,57600,81000,58400"
st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
)
)
*126 (PortIoOut
uid 15557,0
shape (CompositeShape
uid 15558,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 15559,0
sl 0
ro 270
xt "85500,148625,87000,149375"
)
(Line
uid 15560,0
sl 0
ro 270
xt "85000,149000,85500,149000"
pts [
"85000,149000"
"85500,149000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 15561,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15562,0
va (VaSet
)
xt "88000,148500,94200,149500"
st "RS485_E_DO"
blo "88000,149300"
tm "WireNameMgr"
)
)
)
*127 (PortIoIn
uid 15706,0
shape (CompositeShape
uid 15707,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 15708,0
sl 0
ro 270
xt "47000,136625,48500,137375"
)
(Line
uid 15709,0
sl 0
ro 270
xt "48500,137000,49000,137000"
pts [
"48500,137000"
"49000,137000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 15710,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15711,0
va (VaSet
)
xt "41900,136500,46000,137500"
st "D_PLLLCK"
ju 2
blo "46000,137300"
tm "WireNameMgr"
)
)
)
*128 (Net
uid 15718,0
decl (Decl
n "D_PLLLCK"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 216,0
)
declText (MLText
uid 15719,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,11000,67000,11800"
st "D_PLLLCK              : std_logic_vector(3 DOWNTO 0)"
)
)
*129 (PortIoOut
uid 15845,0
shape (CompositeShape
uid 15846,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 15847,0
sl 0
ro 270
xt "95500,87625,97000,88375"
)
(Line
uid 15848,0
sl 0
ro 270
xt "95000,88000,95500,88000"
pts [
"95000,88000"
"95500,88000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 15849,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15850,0
va (VaSet
)
xt "98000,87500,100000,88500"
st "TCS"
blo "98000,88300"
tm "WireNameMgr"
)
)
)
*130 (Net
uid 15857,0
decl (Decl
n "TCS"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 217,0
)
declText (MLText
uid 15858,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,37400,67000,38200"
st "TCS                   : std_logic_vector(3 DOWNTO 0)"
)
)
*131 (PortIoOut
uid 16057,0
shape (CompositeShape
uid 16058,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 16059,0
sl 0
ro 90
xt "19000,112625,20500,113375"
)
(Line
uid 16060,0
sl 0
ro 90
xt "20500,113000,21000,113000"
pts [
"21000,113000"
"20500,113000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 16061,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16062,0
va (VaSet
)
xt "14500,112500,18000,113500"
st "DSRCLK"
ju 2
blo "18000,113300"
tm "WireNameMgr"
)
)
)
*132 (Net
uid 16069,0
decl (Decl
n "DSRCLK"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 222,0
i "(others => '0')"
)
declText (MLText
uid 16070,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,22200,77500,23000"
st "DSRCLK                : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
)
)
*133 (Net
uid 16245,0
decl (Decl
n "SRCLK"
t "std_logic"
o 56
suid 225,0
i "'0'"
)
declText (MLText
uid 16246,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,49600,75000,50400"
st "SIGNAL SRCLK                 : std_logic                      := '0'"
)
)
*134 (HdlText
uid 16336,0
optionalChildren [
*135 (EmbeddedText
uid 16342,0
commentText (CommentText
uid 16343,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 16344,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "23000,116000,42000,118000"
)
oxt "0,0,18000,5000"
text (MLText
uid 16345,0
va (VaSet
)
xt "23200,116200,41200,117200"
st "
DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 19000
)
)
)
]
shape (Rectangle
uid 16337,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "30000,112000,34000,116000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 16338,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*136 (Text
uid 16339,0
va (VaSet
font "Arial,8,1"
)
xt "30150,112000,33350,113000"
st "SRCLK"
blo "30150,112800"
tm "HdlTextNameMgr"
)
*137 (Text
uid 16340,0
va (VaSet
font "Arial,8,1"
)
xt "30150,113000,30950,114000"
st "1"
blo "30150,113800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 16341,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "30250,114250,31750,115750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*138 (Net
uid 16536,0
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 58
suid 226,0
i "'0'"
)
declText (MLText
uid 16537,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,51200,75000,52000"
st "SIGNAL alarm_refclk_too_high : std_logic                      := '0'"
)
)
*139 (Net
uid 16544,0
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
o 59
suid 227,0
i "'0'"
)
declText (MLText
uid 16545,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,52000,75000,52800"
st "SIGNAL alarm_refclk_too_low  : std_logic                      := '0'"
)
)
*140 (Net
uid 16574,0
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 downto 0)"
o 61
suid 230,0
i "(others => '0')"
)
declText (MLText
uid 16575,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,53600,81000,54400"
st "SIGNAL counter_result        : std_logic_vector(11 downto 0)  := (others => '0')"
)
)
*141 (SaComponent
uid 17195,0
optionalChildren [
*142 (CptPort
uid 17027,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17028,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,70625,80750,71375"
)
tg (CPTG
uid 17029,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17030,0
va (VaSet
)
xt "74800,70500,79000,71500"
st "wiz_reset"
ju 2
blo "79000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 50
suid 2,0
i "'1'"
)
)
)
*143 (CptPort
uid 17031,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17032,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,119625,80750,120375"
)
tg (CPTG
uid 17033,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17034,0
va (VaSet
)
xt "74600,119500,79000,120500"
st "led : (7:0)"
ju 2
blo "79000,120300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 7,0
i "(OTHERS => '0')"
)
)
)
*144 (CptPort
uid 17035,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17036,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,77625,52000,78375"
)
tg (CPTG
uid 17037,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17038,0
va (VaSet
)
xt "53000,77500,56000,78500"
st "trigger"
blo "53000,78300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 18,0
)
)
)
*145 (CptPort
uid 17039,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17040,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,89625,52000,90375"
)
tg (CPTG
uid 17041,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17042,0
va (VaSet
)
xt "53000,89500,56500,90500"
st "adc_oeb"
blo "53000,90300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 21,0
i "'1'"
)
)
)
*146 (CptPort
uid 17043,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17044,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,80625,52000,81375"
)
tg (CPTG
uid 17045,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17046,0
va (VaSet
)
xt "53000,80500,59700,81500"
st "board_id : (3:0)"
blo "53000,81300"
)
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 24,0
)
)
)
*147 (CptPort
uid 17047,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17048,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,81625,52000,82375"
)
tg (CPTG
uid 17049,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17050,0
va (VaSet
)
xt "53000,81500,59400,82500"
st "crate_id : (1:0)"
blo "53000,82300"
)
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 25,0
)
)
)
*148 (CptPort
uid 17051,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17052,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,67625,80750,68375"
)
tg (CPTG
uid 17053,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17054,0
va (VaSet
)
xt "72100,67500,79000,68500"
st "wiz_addr : (9:0)"
ju 2
blo "79000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 47
suid 26,0
)
)
)
*149 (CptPort
uid 17055,0
ps "OnEdgeStrategy"
shape (Diamond
uid 17056,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,68625,80750,69375"
)
tg (CPTG
uid 17057,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17058,0
va (VaSet
)
xt "71800,68500,79000,69500"
st "wiz_data : (15:0)"
ju 2
blo "79000,69300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 53
suid 27,0
)
)
)
*150 (CptPort
uid 17059,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17060,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,74625,80750,75375"
)
tg (CPTG
uid 17061,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17062,0
va (VaSet
)
xt "76000,74500,79000,75500"
st "wiz_cs"
ju 2
blo "79000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 48
suid 28,0
i "'1'"
)
)
)
*151 (CptPort
uid 17063,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17064,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,72625,80750,73375"
)
tg (CPTG
uid 17065,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17066,0
va (VaSet
)
xt "75800,72500,79000,73500"
st "wiz_wr"
ju 2
blo "79000,73300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 51
suid 29,0
i "'1'"
)
)
)
*152 (CptPort
uid 17067,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17068,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,71625,80750,72375"
)
tg (CPTG
uid 17069,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17070,0
va (VaSet
)
xt "75900,71500,79000,72500"
st "wiz_rd"
ju 2
blo "79000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 49
suid 30,0
i "'1'"
)
)
)
*153 (CptPort
uid 17071,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17072,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,73625,80750,74375"
)
tg (CPTG
uid 17073,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17074,0
va (VaSet
)
xt "75800,73500,79000,74500"
st "wiz_int"
ju 2
blo "79000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 31,0
)
)
)
*154 (CptPort
uid 17075,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17076,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,73625,52000,74375"
)
tg (CPTG
uid 17077,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17078,0
va (VaSet
)
xt "53000,73500,57800,74500"
st "CLK_25_PS"
blo "53000,74300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 35,0
)
)
)
*155 (CptPort
uid 17079,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17080,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,115625,80750,116375"
)
tg (CPTG
uid 17081,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17082,0
va (VaSet
)
xt "75700,115500,79000,116500"
st "CLK_50"
ju 2
blo "79000,116300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 37,0
)
)
)
*156 (CptPort
uid 17083,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17084,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,67625,52000,68375"
)
tg (CPTG
uid 17085,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17086,0
va (VaSet
)
xt "53000,67500,54900,68500"
st "CLK"
blo "53000,68300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*157 (CptPort
uid 17087,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17088,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,88625,52000,89375"
)
tg (CPTG
uid 17089,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17090,0
va (VaSet
)
xt "53000,88500,62300,89500"
st "adc_otr_array : (3:0)"
blo "53000,89300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 40,0
)
)
)
*158 (CptPort
uid 17091,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17092,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,94625,52000,95375"
)
tg (CPTG
uid 17093,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17094,0
va (VaSet
)
xt "53000,94500,59900,95500"
st "adc_data_array"
blo "53000,95300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 41,0
)
)
)
*159 (CptPort
uid 17095,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17096,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,108625,52000,109375"
)
tg (CPTG
uid 17097,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17098,0
va (VaSet
)
xt "53000,108500,62500,109500"
st "drs_channel_id : (3:0)"
blo "53000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 48,0
i "(others => '0')"
)
)
)
*160 (CptPort
uid 17099,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17100,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,109625,52000,110375"
)
tg (CPTG
uid 17101,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17102,0
va (VaSet
)
xt "53000,109500,58200,110500"
st "drs_dwrite"
blo "53000,110300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 49,0
i "'1'"
)
)
)
*161 (CptPort
uid 17103,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17104,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,104625,52000,105375"
)
tg (CPTG
uid 17105,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17106,0
va (VaSet
)
xt "53000,104500,58800,105500"
st "SROUT_in_0"
blo "53000,105300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 52,0
)
)
)
*162 (CptPort
uid 17107,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17108,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,105625,52000,106375"
)
tg (CPTG
uid 17109,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17110,0
va (VaSet
)
xt "53000,105500,58700,106500"
st "SROUT_in_1"
blo "53000,106300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 53,0
)
)
)
*163 (CptPort
uid 17111,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17112,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,106625,52000,107375"
)
tg (CPTG
uid 17113,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17114,0
va (VaSet
)
xt "53000,106500,58800,107500"
st "SROUT_in_2"
blo "53000,107300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 54,0
)
)
)
*164 (CptPort
uid 17115,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17116,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,107625,52000,108375"
)
tg (CPTG
uid 17117,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17118,0
va (VaSet
)
xt "53000,107500,58800,108500"
st "SROUT_in_3"
blo "53000,108300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 55,0
)
)
)
*165 (CptPort
uid 17119,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17120,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,110625,52000,111375"
)
tg (CPTG
uid 17121,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17122,0
va (VaSet
)
xt "53000,110500,57200,111500"
st "RSRLOAD"
blo "53000,111300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 56,0
i "'0'"
)
)
)
*166 (CptPort
uid 17123,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17124,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,112625,52000,113375"
)
tg (CPTG
uid 17125,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17126,0
va (VaSet
)
xt "53000,112500,55900,113500"
st "SRCLK"
blo "53000,113300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 57,0
i "'0'"
)
)
)
*167 (CptPort
uid 17127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,97625,80750,98375"
)
tg (CPTG
uid 17129,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17130,0
va (VaSet
)
xt "77100,97500,79000,98500"
st "sclk"
ju 2
blo "79000,98300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 62,0
)
)
)
*168 (CptPort
uid 17131,0
ps "OnEdgeStrategy"
shape (Diamond
uid 17132,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,98625,80750,99375"
)
tg (CPTG
uid 17133,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17134,0
va (VaSet
)
xt "77600,98500,79000,99500"
st "sio"
ju 2
blo "79000,99300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 63,0
)
)
)
*169 (CptPort
uid 17135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,86625,80750,87375"
)
tg (CPTG
uid 17137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17138,0
va (VaSet
)
xt "76000,86500,79000,87500"
st "dac_cs"
ju 2
blo "79000,87300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 64,0
)
)
)
*170 (CptPort
uid 17139,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17140,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,88625,80750,89375"
)
tg (CPTG
uid 17141,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17142,0
va (VaSet
)
xt "72000,88500,79000,89500"
st "sensor_cs : (3:0)"
ju 2
blo "79000,89300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 65,0
)
)
)
*171 (CptPort
uid 17143,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17144,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,99625,80750,100375"
)
tg (CPTG
uid 17145,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17146,0
va (VaSet
)
xt "77000,99500,79000,100500"
st "mosi"
ju 2
blo "79000,100300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 66,0
i "'0'"
)
)
)
*172 (CptPort
uid 17147,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17148,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,120625,80750,121375"
)
tg (CPTG
uid 17149,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17150,0
va (VaSet
)
xt "75800,120500,79000,121500"
st "denable"
ju 2
blo "79000,121300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 67,0
i "'0'"
)
)
)
*173 (CptPort
uid 17151,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17152,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,139625,80750,140375"
)
tg (CPTG
uid 17153,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17154,0
va (VaSet
)
xt "74800,139500,79000,140500"
st "SRIN_out"
ju 2
blo "79000,140300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 85,0
i "'0'"
)
)
)
*174 (CptPort
uid 17155,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17156,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,133625,80750,134375"
)
tg (CPTG
uid 17157,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17158,0
va (VaSet
)
xt "76600,133500,79000,134500"
st "green"
ju 2
blo "79000,134300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 86,0
)
)
)
*175 (CptPort
uid 17159,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17160,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,134625,80750,135375"
)
tg (CPTG
uid 17161,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17162,0
va (VaSet
)
xt "76300,134500,79000,135500"
st "amber"
ju 2
blo "79000,135300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 87,0
)
)
)
*176 (CptPort
uid 17163,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17164,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,135625,80750,136375"
)
tg (CPTG
uid 17165,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17166,0
va (VaSet
)
xt "77300,135500,79000,136500"
st "red"
ju 2
blo "79000,136300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 88,0
)
)
)
*177 (CptPort
uid 17167,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17168,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,131625,52000,132375"
)
tg (CPTG
uid 17169,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17170,0
va (VaSet
)
xt "53000,131500,58500,132500"
st "D_T_in : (1:0)"
blo "53000,132300"
)
)
thePort (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 91,0
)
)
)
*178 (CptPort
uid 17171,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17172,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,132625,52000,133375"
)
tg (CPTG
uid 17173,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17174,0
va (VaSet
)
xt "53000,132500,59100,133500"
st "drs_refclk_in"
blo "53000,133300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 92,0
)
)
)
*179 (CptPort
uid 17175,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17176,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,136625,52000,137375"
)
tg (CPTG
uid 17177,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17178,0
va (VaSet
)
xt "53000,136500,59700,137500"
st "plllock_in : (3:0)"
blo "53000,137300"
)
)
thePort (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 93,0
)
)
)
*180 (CptPort
uid 17179,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17180,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,131625,80750,132375"
)
tg (CPTG
uid 17181,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17182,0
va (VaSet
)
xt "69400,131500,79000,132500"
st "counter_result : (11:0)"
ju 2
blo "79000,132300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 94,0
)
)
)
*181 (CptPort
uid 17183,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17184,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,129625,80750,130375"
)
tg (CPTG
uid 17185,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17186,0
va (VaSet
)
xt "69000,129500,79000,130500"
st "alarm_refclk_too_high"
ju 2
blo "79000,130300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 95,0
)
)
)
*182 (CptPort
uid 17187,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17188,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,130625,80750,131375"
)
tg (CPTG
uid 17189,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17190,0
va (VaSet
)
xt "69400,130500,79000,131500"
st "alarm_refclk_too_low"
ju 2
blo "79000,131300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 96,0
)
)
)
*183 (CptPort
uid 17191,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17192,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51250,70625,52000,71375"
)
tg (CPTG
uid 17193,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17194,0
va (VaSet
)
xt "53000,70500,57000,71500"
st "ADC_CLK"
blo "53000,71300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 97,0
)
)
)
*184 (CptPort
uid 17620,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17621,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,143625,80750,144375"
)
tg (CPTG
uid 17622,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17623,0
va (VaSet
)
xt "73400,143500,79000,144500"
st "trigger_veto"
ju 2
blo "79000,144300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 98,0
i "'1'"
)
)
)
*185 (CptPort
uid 17711,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17712,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,149625,80750,150375"
)
tg (CPTG
uid 17713,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17714,0
va (VaSet
)
xt "70900,149500,79000,150500"
st "FTM_RS485_rx_d"
ju 2
blo "79000,150300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 99,0
)
)
)
*186 (CptPort
uid 17715,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17716,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,147625,80750,148375"
)
tg (CPTG
uid 17717,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17718,0
va (VaSet
)
xt "70600,147500,79000,148500"
st "FTM_RS485_rx_en"
ju 2
blo "79000,148300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 101,0
)
)
)
*187 (CptPort
uid 17719,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17720,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,148625,80750,149375"
)
tg (CPTG
uid 17721,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17722,0
va (VaSet
)
xt "70900,148500,79000,149500"
st "FTM_RS485_tx_d"
ju 2
blo "79000,149300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 100,0
)
)
)
*188 (CptPort
uid 17723,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17724,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,146625,80750,147375"
)
tg (CPTG
uid 17725,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17726,0
va (VaSet
)
xt "70600,146500,79000,147500"
st "FTM_RS485_tx_en"
ju 2
blo "79000,147300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 102,0
)
)
)
*189 (CptPort
uid 17842,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17843,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,105625,80750,106375"
)
tg (CPTG
uid 17844,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17845,0
va (VaSet
)
xt "70600,105500,79000,106500"
st "w5300_state : (7:0)"
ju 2
blo "79000,106300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 103,0
)
)
)
*190 (CptPort
uid 18058,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18059,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,106625,80750,107375"
)
tg (CPTG
uid 18060,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18061,0
va (VaSet
)
xt "68600,106500,79000,107500"
st "debug_data_ram_empty"
ju 2
blo "79000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 104,0
)
)
)
*191 (CptPort
uid 18062,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18063,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,107625,80750,108375"
)
tg (CPTG
uid 18064,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18065,0
va (VaSet
)
xt "71500,107500,79000,108500"
st "debug_data_valid"
ju 2
blo "79000,108300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 105,0
)
)
)
*192 (CptPort
uid 18187,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18188,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,104625,80750,105375"
)
tg (CPTG
uid 18189,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18190,0
va (VaSet
)
xt "67600,104500,79000,105500"
st "mem_manager_state : (3:0)"
ju 2
blo "79000,105300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 106,0
)
)
)
*193 (CptPort
uid 18322,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18323,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,108625,80750,109375"
)
tg (CPTG
uid 18324,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18325,0
va (VaSet
)
xt "72100,108500,79000,109500"
st "DG_state : (7:0)"
ju 2
blo "79000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 108,0
)
)
)
*194 (CptPort
uid 18471,0
ps "OnEdgeStrategy"
shape (Triangle
uid 18472,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80000,150625,80750,151375"
)
tg (CPTG
uid 18473,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 18474,0
va (VaSet
)
xt "67100,150500,79000,151500"
st "socket_tx_free_out : (16:0)"
ju 2
blo "79000,151300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 109,0
)
)
)
]
shape (Rectangle
uid 17196,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "52000,66000,80000,153000"
)
oxt "15000,-8000,43000,70000"
ttg (MlTextGroup
uid 17197,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*195 (Text
uid 17198,0
va (VaSet
font "Arial,8,1"
)
xt "55200,141000,61400,142000"
st "FACT_FAD_lib"
blo "55200,141800"
tm "BdLibraryNameMgr"
)
*196 (Text
uid 17199,0
va (VaSet
font "Arial,8,1"
)
xt "55200,142000,59400,143000"
st "FAD_main"
blo "55200,142800"
tm "CptNameMgr"
)
*197 (Text
uid 17200,0
va (VaSet
font "Arial,8,1"
)
xt "55200,143000,61000,144000"
st "I_board_main"
blo "55200,143800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 17201,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 17202,0
text (MLText
uid 17203,0
va (VaSet
font "Courier New,8,0"
)
xt "52000,65200,81500,66000"
st "RAMADDRWIDTH64b = LOG2_OF_RAM_SIZE_64B    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "LOG2_OF_RAM_SIZE_64B"
)
]
)
viewicon (ZoomableIcon
uid 17204,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "52250,151250,53750,152750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*198 (Net
uid 17294,0
lang 2
decl (Decl
n "ADC_CLK"
t "std_logic"
o 53
suid 231,0
)
declText (MLText
uid 17295,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,46400,61000,47200"
st "SIGNAL ADC_CLK               : std_logic"
)
)
*199 (PortIoOut
uid 17401,0
shape (CompositeShape
uid 17402,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 17403,0
sl 0
ro 270
xt "100500,143625,102000,144375"
)
(Line
uid 17404,0
sl 0
ro 270
xt "100000,144000,100500,144000"
pts [
"100000,144000"
"100500,144000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 17405,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17406,0
va (VaSet
)
xt "103000,143500,105900,144500"
st "TRG_V"
blo "103000,144300"
tm "WireNameMgr"
)
)
)
*200 (Net
uid 17413,0
lang 2
decl (Decl
n "TRG_V"
t "std_logic"
o 44
suid 232,0
i "'0'"
)
declText (MLText
uid 17414,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,38200,71500,39000"
st "TRG_V                 : std_logic                      := '0'"
)
)
*201 (Net
uid 17846,0
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 68
suid 233,0
)
declText (MLText
uid 17847,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,63200,96000,64000"
st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
)
)
*202 (Net
uid 18066,0
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 63
suid 234,0
)
declText (MLText
uid 18067,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,56000,61000,56800"
st "SIGNAL debug_data_ram_empty  : std_logic"
)
)
*203 (Net
uid 18074,0
decl (Decl
n "debug_data_valid"
t "std_logic"
o 64
suid 235,0
)
declText (MLText
uid 18075,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,56800,61000,57600"
st "SIGNAL debug_data_valid      : std_logic"
)
)
*204 (Net
uid 18205,0
lang 2
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 66
suid 237,0
)
declText (MLText
uid 18206,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,58400,96000,59200"
st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
)
)
*205 (Net
uid 18326,0
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 55
suid 238,0
)
declText (MLText
uid 18327,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,48000,70500,49600"
st "-- for debugging
SIGNAL DG_state              : std_logic_vector(7 downto 0)"
)
)
*206 (Net
uid 18475,0
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 67
suid 239,0
)
declText (MLText
uid 18476,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,61600,86000,62400"
st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
)
)
*207 (PortIoOut
uid 18802,0
shape (CompositeShape
uid 18803,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18804,0
sl 0
ro 270
xt "137500,121625,139000,122375"
)
(Line
uid 18805,0
sl 0
ro 270
xt "137000,122000,137500,122000"
pts [
"137000,122000"
"137500,122000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 18806,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18807,0
va (VaSet
)
xt "140000,121500,142300,122500"
st "W_T"
blo "140000,122300"
tm "WireNameMgr"
)
)
)
*208 (Net
uid 18814,0
decl (Decl
n "W_T"
t "std_logic_vector"
b "( 3 DOWNTO 0 )"
o 49
suid 240,0
i "(others => '0')"
)
declText (MLText
uid 18815,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,42200,77500,43000"
st "W_T                   : std_logic_vector( 3 DOWNTO 0 ) := (others => '0')"
)
)
*209 (MWC
uid 19427,0
optionalChildren [
*210 (CptPort
uid 19407,0
optionalChildren [
*211 (Line
uid 19411,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "82000,85000,82000,85000"
pts [
"82000,85000"
"82000,85000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 19408,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "81250,84625,82000,85375"
)
tg (CPTG
uid 19409,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19410,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "475200,46500,476000,47500"
st "s"
blo "475200,47300"
)
s (Text
uid 19436,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "475200,47500,475200,47500"
blo "475200,47500"
)
)
thePort (LogicalPort
decl (Decl
n "s"
t "std_logic"
o 69
suid 1,0
)
)
)
*212 (CptPort
uid 19412,0
optionalChildren [
*213 (Line
uid 19416,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "85000,85000,85000,85000"
pts [
"85000,85000"
"85000,85000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 19413,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "85000,84625,85750,85375"
)
tg (CPTG
uid 19414,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 19415,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "473000,44500,473600,45500"
st "t"
ju 2
blo "473600,45300"
)
s (Text
uid 19437,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "473600,45500,473600,45500"
ju 2
blo "473600,45500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "t"
t "std_logic"
o 22
suid 2,0
)
)
)
*214 (CommentGraphic
uid 19417,0
shape (PolyLine2D
pts [
"82000,85000"
"83000,84000"
]
uid 19418,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "82000,84000,83000,85000"
)
oxt "6000,6000,7000,7000"
)
*215 (CommentGraphic
uid 19419,0
shape (PolyLine2D
pts [
"82000,85000"
"83000,86000"
]
uid 19420,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "82000,85000,83000,86000"
)
oxt "6000,7000,7000,8000"
)
*216 (CommentGraphic
uid 19421,0
shape (PolyLine2D
pts [
"82988,85329"
"83988,85329"
]
uid 19422,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "82988,85329,83988,85329"
)
oxt "6988,7329,7988,7329"
)
*217 (CommentGraphic
uid 19423,0
shape (PolyLine2D
pts [
"84000,85000"
"85000,85000"
]
uid 19424,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "84000,85000,85000,85000"
)
oxt "8000,7000,9000,7000"
)
*218 (CommentGraphic
uid 19425,0
shape (PolyLine2D
pts [
"82976,84730"
"83976,84730"
]
uid 19426,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "82976,84730,83976,84730"
)
oxt "6976,6730,7976,6730"
)
]
shape (Rectangle
uid 19428,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "82000,84000,85000,86000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 19429,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*219 (Text
uid 19430,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "82350,85100,87150,86100"
st "moduleware"
blo "82350,85900"
)
*220 (Text
uid 19431,0
va (VaSet
font "arial,8,0"
)
xt "82350,86100,87050,87100"
st "assignment"
blo "82350,86900"
)
*221 (Text
uid 19432,0
va (VaSet
font "arial,8,0"
)
xt "82350,87100,83350,88100"
st "I0"
blo "82350,87900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 19433,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 19434,0
text (MLText
uid 19435,0
va (VaSet
font "arial,8,0"
)
xt "77000,64400,77000,64400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*222 (MWC
uid 19438,0
optionalChildren [
*223 (CptPort
uid 19447,0
optionalChildren [
*224 (Line
uid 19452,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "82000,90000,82000,90000"
pts [
"82000,90000"
"82000,90000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 19448,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "81250,89625,82000,90375"
)
tg (CPTG
uid 19449,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19450,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
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"95976,143730"
"96976,143730"
]
uid 20218,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "95976,143730,96976,143730"
)
oxt "6976,6730,7976,6730"
)
]
shape (Rectangle
uid 20189,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "95000,143000,98000,145000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 20190,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*275 (Text
uid 20191,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "95350,144100,100150,145100"
st "moduleware"
blo "95350,144900"
)
*276 (Text
uid 20192,0
va (VaSet
font "arial,8,0"
)
xt "95350,145100,100050,146100"
st "assignment"
blo "95350,145900"
)
*277 (Text
uid 20193,0
va (VaSet
font "arial,8,0"
)
xt "95350,146100,96350,147100"
st "I4"
blo "95350,146900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 20194,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 20195,0
text (MLText
uid 20196,0
va (VaSet
font "arial,8,0"
)
xt "90000,123400,90000,123400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*278 (Net
uid 20219,0
decl (Decl
n "trigger_veto"
t "std_logic"
o 73
suid 249,0
i "'1'"
)
declText (MLText
uid 20220,0
va (VaSet
font "Courier New,8,0"
)
xt "39000,62400,75000,63200"
st "SIGNAL trigger_veto          : std_logic                      := '1'"
)
)
*279 (Wire
uid 245,0
shape (OrthoPolyLine
uid 246,0
va (VaSet
vasetType 3
)
xt "21000,68000,51250,68000"
pts [
"51250,68000"
"21000,68000"
]
)
start &156
end &13
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 249,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 250,0
va (VaSet
isHidden 1
)
xt "53250,67000,56450,68000"
st "X_50M"
blo "53250,67800"
tm "WireNameMgr"
)
)
on &32
)
*280 (Wire
uid 277,0
shape (OrthoPolyLine
uid 278,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32000,81000,51250,81000"
pts [
"51250,81000"
"32000,81000"
]
)
start &146
end &14
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 281,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 282,0
va (VaSet
)
xt "44000,80000,50700,81000"
st "board_id : (3:0)"
blo "44000,80800"
tm "WireNameMgr"
)
)
on &18
)
*281 (Wire
uid 285,0
shape (OrthoPolyLine
uid 286,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "32000,82000,51250,82000"
pts [
"51250,82000"
"32000,82000"
]
)
start &147
end &14
sat 32
eat 2
sty 1
st 0
sf 1
si 0
tg (WTG
uid 289,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 290,0
va (VaSet
)
xt "44000,81000,50400,82000"
st "crate_id : (1:0)"
blo "44000,81800"
tm "WireNameMgr"
)
)
on &19
)
*282 (Wire
uid 362,0
shape (OrthoPolyLine
uid 363,0
va (VaSet
vasetType 3
)
xt "21000,90000,51250,90000"
pts [
"21000,90000"
"51250,90000"
]
)
start &39
end &145
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 364,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 365,0
va (VaSet
isHidden 1
)
xt "22000,89000,25700,90000"
st "OE_ADC"
blo "22000,89800"
tm "WireNameMgr"
)
)
on &40
)
*283 (Wire
uid 418,0
shape (OrthoPolyLine
uid 419,0
va (VaSet
vasetType 3
)
xt "80750,71000,90000,71000"
pts [
"80750,71000"
"90000,71000"
]
)
start &142
end &20
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 422,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 423,0
va (VaSet
isHidden 1
)
xt "82000,70000,85400,71000"
st "W_RES"
blo "82000,70800"
tm "WireNameMgr"
)
)
on &72
)
*284 (Wire
uid 426,0
shape (OrthoPolyLine
uid 427,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,68000,90000,68000"
pts [
"80750,68000"
"90000,68000"
]
)
start &148
end &21
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 430,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 431,0
va (VaSet
isHidden 1
)
xt "82000,67000,84400,68000"
st "W_A"
blo "82000,67800"
tm "WireNameMgr"
)
)
on &70
)
*285 (Wire
uid 434,0
shape (OrthoPolyLine
uid 435,0
va (VaSet
vasetType 3
)
xt "80750,75000,90000,75000"
pts [
"80750,75000"
"90000,75000"
]
)
start &150
end &22
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 438,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 439,0
va (VaSet
isHidden 1
)
xt "82000,74000,84900,75000"
st "W_CS"
blo "82000,74800"
tm "WireNameMgr"
)
)
on &76
)
*286 (Wire
uid 442,0
shape (OrthoPolyLine
uid 443,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,69000,90000,69000"
pts [
"80750,69000"
"90000,69000"
]
)
start &149
end &23
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 447,0
va (VaSet
isHidden 1
)
xt "82000,68000,84400,69000"
st "W_D"
blo "82000,68800"
tm "WireNameMgr"
)
)
on &71
)
*287 (Wire
uid 450,0
shape (OrthoPolyLine
uid 451,0
va (VaSet
vasetType 3
)
xt "80750,74000,90000,74000"
pts [
"90000,74000"
"80750,74000"
]
)
start &24
end &153
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 454,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 455,0
va (VaSet
isHidden 1
)
xt "82000,73000,85300,74000"
st "W_INT"
blo "82000,73800"
tm "WireNameMgr"
)
)
on &75
)
*288 (Wire
uid 458,0
shape (OrthoPolyLine
uid 459,0
va (VaSet
vasetType 3
)
xt "80750,72000,90000,72000"
pts [
"80750,72000"
"90000,72000"
]
)
start &152
end &25
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 462,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 463,0
va (VaSet
isHidden 1
)
xt "82000,71000,84900,72000"
st "W_RD"
blo "82000,71800"
tm "WireNameMgr"
)
)
on &73
)
*289 (Wire
uid 466,0
shape (OrthoPolyLine
uid 467,0
va (VaSet
vasetType 3
)
xt "80750,73000,90000,73000"
pts [
"80750,73000"
"90000,73000"
]
)
start &151
end &26
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 470,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 471,0
va (VaSet
isHidden 1
)
xt "82000,72000,85200,73000"
st "W_WR"
blo "82000,72800"
tm "WireNameMgr"
)
)
on &74
)
*290 (Wire
uid 1467,0
shape (OrthoPolyLine
uid 1468,0
va (VaSet
vasetType 3
)
xt "30000,95000,51250,95000"
pts [
"30000,95000"
"41000,95000"
"51250,95000"
]
)
start &43
end &158
sat 2
eat 32
st 0
sf 1
si 0
tg (WTG
uid 1471,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1472,0
va (VaSet
)
xt "32000,94000,38900,95000"
st "adc_data_array"
blo "32000,94800"
tm "WireNameMgr"
)
)
on &27
)
*291 (Wire
uid 1730,0
shape (OrthoPolyLine
uid 1731,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,89000,51250,89000"
pts [
"21000,89000"
"51250,89000"
]
)
start &41
end &157
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1735,0
va (VaSet
isHidden 1
)
xt "22000,88000,25000,89000"
st "A_OTR"
blo "22000,88800"
tm "WireNameMgr"
)
)
on &42
)
*292 (Wire
uid 1833,0
shape (OrthoPolyLine
uid 1834,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,109000,51250,109000"
pts [
"51250,109000"
"21000,109000"
]
)
start &159
end &63
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1837,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1838,0
va (VaSet
isHidden 1
)
xt "22000,108000,24100,109000"
st "D_A"
blo "22000,108800"
tm "WireNameMgr"
)
)
on &64
)
*293 (Wire
uid 1841,0
shape (OrthoPolyLine
uid 1842,0
va (VaSet
vasetType 3
)
xt "21000,110000,51250,110000"
pts [
"51250,110000"
"21000,110000"
]
)
start &160
end &65
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1846,0
va (VaSet
isHidden 1
)
xt "22000,109000,25800,110000"
st "DWRITE"
blo "22000,109800"
tm "WireNameMgr"
)
)
on &66
)
*294 (Wire
uid 1865,0
shape (OrthoPolyLine
uid 1866,0
va (VaSet
vasetType 3
)
xt "21000,105000,51250,105000"
pts [
"21000,105000"
"51250,105000"
]
)
start &55
end &161
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1869,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1870,0
va (VaSet
isHidden 1
)
xt "22000,104000,26600,105000"
st "D0_SROUT"
blo "22000,104800"
tm "WireNameMgr"
)
)
on &59
)
*295 (Wire
uid 1873,0
shape (OrthoPolyLine
uid 1874,0
va (VaSet
vasetType 3
)
xt "21000,106000,51250,106000"
pts [
"21000,106000"
"51250,106000"
]
)
start &56
end &162
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1877,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1878,0
va (VaSet
isHidden 1
)
xt "22000,105000,26600,106000"
st "D1_SROUT"
blo "22000,105800"
tm "WireNameMgr"
)
)
on &60
)
*296 (Wire
uid 1881,0
shape (OrthoPolyLine
uid 1882,0
va (VaSet
vasetType 3
)
xt "21000,107000,51250,107000"
pts [
"21000,107000"
"51250,107000"
]
)
start &57
end &163
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1885,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1886,0
va (VaSet
isHidden 1
)
xt "22000,106000,26600,107000"
st "D2_SROUT"
blo "22000,106800"
tm "WireNameMgr"
)
)
on &61
)
*297 (Wire
uid 1889,0
shape (OrthoPolyLine
uid 1890,0
va (VaSet
vasetType 3
)
xt "21000,108000,51250,108000"
pts [
"21000,108000"
"51250,108000"
]
)
start &58
end &164
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1893,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1894,0
va (VaSet
isHidden 1
)
xt "22000,107000,26600,108000"
st "D3_SROUT"
blo "22000,107800"
tm "WireNameMgr"
)
)
on &62
)
*298 (Wire
uid 2409,0
shape (OrthoPolyLine
uid 2410,0
va (VaSet
vasetType 3
)
xt "21000,111000,51250,111000"
pts [
"51250,111000"
"21000,111000"
]
)
start &165
end &29
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2413,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2414,0
va (VaSet
isHidden 1
)
xt "22000,110000,26200,111000"
st "RSRLOAD"
blo "22000,110800"
tm "WireNameMgr"
)
)
on &28
)
*299 (Wire
uid 3009,0
shape (OrthoPolyLine
uid 3010,0
va (VaSet
vasetType 3
)
xt "86000,95000,99000,97000"
pts [
"86000,95000"
"99000,97000"
]
)
start &238
end &68
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3011,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3012,0
va (VaSet
isHidden 1
)
xt "87000,94000,89900,95000"
st "S_CLK"
blo "87000,94800"
tm "WireNameMgr"
)
)
on &69
)
*300 (Wire
uid 3015,0
shape (OrthoPolyLine
uid 3016,0
va (VaSet
vasetType 3
)
xt "80750,99000,90000,99000"
pts [
"80750,99000"
"90000,99000"
]
)
start &168
end &77
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3017,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3018,0
va (VaSet
isHidden 1
)
xt "82750,98000,85450,99000"
st "MISO"
blo "82750,98800"
tm "WireNameMgr"
)
)
on &80
)
*301 (Wire
uid 3027,0
shape (OrthoPolyLine
uid 3028,0
va (VaSet
vasetType 3
)
xt "85000,84000,97000,85000"
pts [
"85000,85000"
"97000,84000"
]
)
start &212
end &67
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3031,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3032,0
va (VaSet
isHidden 1
)
xt "86000,84000,89700,85000"
st "DAC_CS"
blo "86000,84800"
tm "WireNameMgr"
)
)
on &30
)
*302 (Wire
uid 3218,0
shape (OrthoPolyLine
uid 3219,0
va (VaSet
vasetType 3
)
xt "22000,78000,51250,78000"
pts [
"22000,78000"
"51250,78000"
]
)
start &12
end &144
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3220,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3221,0
va (VaSet
isHidden 1
)
xt "33000,77000,34900,78000"
st "TRG"
blo "33000,77800"
tm "WireNameMgr"
)
)
on &33
)
*303 (Wire
uid 3260,0
shape (OrthoPolyLine
uid 3261,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-1000,71000,5000,71000"
pts [
"-1000,71000"
"5000,71000"
]
)
start &31
end &34
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3264,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3265,0
va (VaSet
isHidden 1
)
xt "-23000,70000,-20100,71000"
st "A_CLK"
blo "-23000,70800"
tm "WireNameMgr"
)
)
on &38
)
*304 (Wire
uid 3318,0
shape (OrthoPolyLine
uid 3319,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,95000,24000,95000"
pts [
"21000,95000"
"24000,95000"
]
)
start &47
end &43
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3322,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3323,0
va (VaSet
isHidden 1
)
xt "23000,94000,25300,95000"
st "A0_D"
blo "23000,94800"
tm "WireNameMgr"
)
)
on &51
)
*305 (Wire
uid 3352,0
shape (OrthoPolyLine
uid 3353,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,96000,24000,96000"
pts [
"21000,96000"
"24000,96000"
]
)
start &48
end &43
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3356,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3357,0
va (VaSet
isHidden 1
)
xt "23000,95000,25300,96000"
st "A1_D"
blo "23000,95800"
tm "WireNameMgr"
)
)
on &52
)
*306 (Wire
uid 3360,0
shape (OrthoPolyLine
uid 3361,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,97000,24000,97000"
pts [
"21000,97000"
"24000,97000"
]
)
start &49
end &43
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3364,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3365,0
va (VaSet
isHidden 1
)
xt "23000,96000,25300,97000"
st "A2_D"
blo "23000,96800"
tm "WireNameMgr"
)
)
on &53
)
*307 (Wire
uid 3368,0
shape (OrthoPolyLine
uid 3369,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,98000,24000,98000"
pts [
"21000,98000"
"24000,98000"
]
)
start &50
end &43
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3373,0
va (VaSet
isHidden 1
)
xt "23000,97000,25300,98000"
st "A3_D"
blo "23000,97800"
tm "WireNameMgr"
)
)
on &54
)
*308 (Wire
uid 3682,0
shape (OrthoPolyLine
uid 3683,0
va (VaSet
vasetType 3
)
xt "86000,100000,99000,102000"
pts [
"86000,102000"
"99000,100000"
]
)
start &251
end &79
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3686,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3687,0
va (VaSet
isHidden 1
)
xt "87000,101000,89700,102000"
st "MOSI"
blo "87000,101800"
tm "WireNameMgr"
)
)
on &78
)
*309 (Wire
uid 3834,0
shape (OrthoPolyLine
uid 3835,0
va (VaSet
vasetType 3
)
xt "132000,139000,137000,139000"
pts [
"137000,139000"
"132000,139000"
]
)
start &86
end &102
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3838,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3839,0
va (VaSet
isHidden 1
)
xt "132000,138000,135000,139000"
st "EE_CS"
blo "132000,138800"
tm "WireNameMgr"
)
)
on &92
)
*310 (Wire
uid 4942,0
shape (OrthoPolyLine
uid 4943,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "132000,118000,137000,118000"
pts [
"132000,118000"
"137000,118000"
]
)
start &102
end &93
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4948,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4949,0
va (VaSet
isHidden 1
)
xt "133750,115000,135750,116000"
st "D_T"
blo "133750,115800"
tm "WireNameMgr"
)
)
on &94
)
*311 (Wire
uid 6431,0
shape (OrthoPolyLine
uid 6432,0
va (VaSet
vasetType 3
)
xt "80750,121000,82000,121000"
pts [
"80750,121000"
"82000,121000"
]
)
start &172
end &85
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6435,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6436,0
va (VaSet
isHidden 1
)
xt "92000,120000,96100,121000"
st "DENABLE"
blo "92000,120800"
tm "WireNameMgr"
)
)
on &91
)
*312 (Wire
uid 7144,0
shape (OrthoPolyLine
uid 7145,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "132000,121000,137000,121000"
pts [
"132000,121000"
"137000,121000"
]
)
start &102
end &97
sat 2
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 7148,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7149,0
va (VaSet
isHidden 1
)
xt "137000,133000,142300,134000"
st "A1_T : (7:0)"
blo "137000,133800"
tm "WireNameMgr"
)
)
on &98
)
*313 (Wire
uid 9502,0
shape (OrthoPolyLine
uid 9503,0
va (VaSet
vasetType 3
)
xt "80750,116000,85000,116000"
pts [
"80750,116000"
"85000,116000"
]
)
start &155
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9506,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9507,0
va (VaSet
)
xt "86000,115000,89300,116000"
st "CLK_50"
blo "86000,115800"
tm "WireNameMgr"
)
)
on &99
)
*314 (Wire
uid 10302,0
shape (OrthoPolyLine
uid 10303,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "132000,120000,137000,120000"
pts [
"132000,120000"
"137000,120000"
]
)
start &102
end &100
sat 2
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 10306,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10307,0
va (VaSet
isHidden 1
)
xt "133000,139000,138400,140000"
st "A0_T : (7:0)"
blo "133000,139800"
tm "WireNameMgr"
)
)
on &101
)
*315 (Wire
uid 11514,0
shape (OrthoPolyLine
uid 11515,0
va (VaSet
vasetType 3
)
xt "80750,150000,85000,150000"
pts [
"85000,150000"
"80750,150000"
]
)
start &108
end &185
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 11518,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11519,0
va (VaSet
isHidden 1
)
xt "86000,149000,92000,150000"
st "RS485_E_DI"
blo "86000,149800"
tm "WireNameMgr"
)
)
on &109
)
*316 (Wire
uid 11528,0
shape (OrthoPolyLine
uid 11529,0
va (VaSet
vasetType 3
)
xt "80750,149000,85000,149000"
pts [
"80750,149000"
"85000,149000"
]
)
start &187
end &126
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 11532,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11533,0
va (VaSet
isHidden 1
)
xt "107000,148000,113200,149000"
st "RS485_E_DO"
blo "107000,148800"
tm "WireNameMgr"
)
)
on &110
)
*317 (Wire
uid 12320,0
shape (OrthoPolyLine
uid 12321,0
va (VaSet
vasetType 3
)
xt "80750,140000,87000,140000"
pts [
"80750,140000"
"87000,140000"
]
)
start &173
end &111
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12324,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12325,0
va (VaSet
isHidden 1
)
xt "82000,139000,84500,140000"
st "SRIN"
blo "82000,139800"
tm "WireNameMgr"
)
)
on &112
)
*318 (Wire
uid 12545,0
shape (OrthoPolyLine
uid 12546,0
va (VaSet
vasetType 3
)
xt "80750,135000,87000,135000"
pts [
"80750,135000"
"87000,135000"
]
)
start &175
end &113
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 12549,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12550,0
va (VaSet
isHidden 1
)
xt "83000,134000,88200,135000"
st "AMBER_LED"
blo "83000,134800"
tm "WireNameMgr"
)
)
on &116
)
*319 (Wire
uid 12559,0
shape (OrthoPolyLine
uid 12560,0
va (VaSet
vasetType 3
)
xt "80750,134000,87000,134000"
pts [
"80750,134000"
"87000,134000"
]
)
start &174
end &114
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 12563,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12564,0
va (VaSet
isHidden 1
)
xt "83000,133000,88000,134000"
st "GREEN_LED"
blo "83000,133800"
tm "WireNameMgr"
)
)
on &117
)
*320 (Wire
uid 12573,0
shape (OrthoPolyLine
uid 12574,0
va (VaSet
vasetType 3
)
xt "80750,136000,87000,136000"
pts [
"80750,136000"
"87000,136000"
]
)
start &176
end &115
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 12577,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12578,0
va (VaSet
isHidden 1
)
xt "83000,143000,87000,144000"
st "RED_LED"
blo "83000,143800"
tm "WireNameMgr"
)
)
on &118
)
*321 (Wire
uid 13522,0
shape (OrthoPolyLine
uid 13523,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,81000,28000,81000"
pts [
"22000,81000"
"28000,81000"
]
)
start &119
end &14
sat 32
eat 1
sty 1
st 0
sf 1
si 0
tg (WTG
uid 13526,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13527,0
va (VaSet
)
xt "22000,80000,27200,81000"
st "LINE : (5:0)"
blo "22000,80800"
tm "WireNameMgr"
)
)
on &120
)
*322 (Wire
uid 13618,0
shape (OrthoPolyLine
uid 13619,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "132000,128000,137000,128000"
pts [
"132000,128000"
"137000,128000"
]
)
start &102
end &95
sat 2
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 13624,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13625,0
va (VaSet
isHidden 1
)
xt "134000,133000,139300,134000"
st "D_T2 : (1:0)"
blo "134000,133800"
tm "WireNameMgr"
)
)
on &96
)
*323 (Wire
uid 13634,0
shape (OrthoPolyLine
uid 13635,0
va (VaSet
vasetType 3
)
xt "49000,133000,51250,133000"
pts [
"49000,133000"
"51250,133000"
]
)
start &121
end &178
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 13638,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13639,0
va (VaSet
isHidden 1
)
xt "51000,141000,54300,142000"
st "REFCLK"
blo "51000,141800"
tm "WireNameMgr"
)
)
on &122
)
*324 (Wire
uid 13658,0
shape (OrthoPolyLine
uid 13659,0
va (VaSet
vasetType 3
)
xt "80750,147000,85000,147000"
pts [
"80750,147000"
"85000,147000"
]
)
start &188
end &84
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 13664,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13665,0
va (VaSet
isHidden 1
)
xt "84000,145000,90100,146000"
st "RS485_E_DE"
blo "84000,145800"
tm "WireNameMgr"
)
)
on &90
)
*325 (Wire
uid 14328,0
shape (OrthoPolyLine
uid 14329,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49000,132000,51250,132000"
pts [
"49000,132000"
"51250,132000"
]
)
start &123
end &177
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 14332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14333,0
va (VaSet
isHidden 1
)
xt "52000,138000,57900,139000"
st "D_T_in : (1:0)"
blo "52000,138800"
tm "WireNameMgr"
)
)
on &124
)
*326 (Wire
uid 15175,0
shape (OrthoPolyLine
uid 15176,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,120000,87000,120000"
pts [
"80750,120000"
"87000,120000"
]
)
start &143
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 15179,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15180,0
va (VaSet
)
xt "82000,119000,86400,120000"
st "led : (7:0)"
blo "82000,119800"
tm "WireNameMgr"
)
)
on &125
)
*327 (Wire
uid 15517,0
shape (OrthoPolyLine
uid 15518,0
va (VaSet
vasetType 3
)
xt "132000,131000,137000,131000"
pts [
"132000,131000"
"137000,131000"
]
)
start &102
end &81
sat 2
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15523,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15524,0
va (VaSet
isHidden 1
)
xt "134000,130000,140100,131000"
st "RS485_C_DE"
blo "134000,130800"
tm "WireNameMgr"
)
)
on &88
)
*328 (Wire
uid 15525,0
shape (OrthoPolyLine
uid 15526,0
va (VaSet
vasetType 3
)
xt "132000,132000,137000,132000"
pts [
"132000,132000"
"137000,132000"
]
)
start &102
end &82
sat 2
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15531,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15532,0
va (VaSet
isHidden 1
)
xt "134000,131000,140200,132000"
st "RS485_C_DO"
blo "134000,131800"
tm "WireNameMgr"
)
)
on &107
)
*329 (Wire
uid 15533,0
shape (OrthoPolyLine
uid 15534,0
va (VaSet
vasetType 3
)
xt "132000,133000,137000,133000"
pts [
"132000,133000"
"137000,133000"
]
)
start &102
end &106
sat 2
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15539,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15540,0
va (VaSet
isHidden 1
)
xt "134000,132000,140000,133000"
st "RS485_C_RE"
blo "134000,132800"
tm "WireNameMgr"
)
)
on &87
)
*330 (Wire
uid 15563,0
shape (OrthoPolyLine
uid 15564,0
va (VaSet
vasetType 3
)
xt "80750,148000,85000,148000"
pts [
"80750,148000"
"85000,148000"
]
)
start &186
end &83
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15569,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15570,0
va (VaSet
isHidden 1
)
xt "83000,147000,89000,148000"
st "RS485_E_RE"
blo "83000,147800"
tm "WireNameMgr"
)
)
on &89
)
*331 (Wire
uid 15712,0
shape (OrthoPolyLine
uid 15713,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49000,137000,51250,137000"
pts [
"49000,137000"
"51250,137000"
]
)
start &127
end &179
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 15716,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15717,0
va (VaSet
isHidden 1
)
xt "51000,136000,58000,137000"
st "D_PLLLCK : (3:0)"
blo "51000,136800"
tm "WireNameMgr"
)
)
on &128
)
*332 (Wire
uid 15851,0
shape (OrthoPolyLine
uid 15852,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "85000,88000,95000,90000"
pts [
"85000,90000"
"95000,88000"
]
)
start &225
end &129
ss 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 15855,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15856,0
va (VaSet
isHidden 1
)
xt "87000,89000,91900,90000"
st "TCS : (3:0)"
blo "87000,89800"
tm "WireNameMgr"
)
)
on &130
)
*333 (Wire
uid 16063,0
shape (OrthoPolyLine
uid 16064,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "21000,113000,30000,113000"
pts [
"30000,113000"
"21000,113000"
]
)
start &134
end &131
sat 2
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16067,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16068,0
va (VaSet
isHidden 1
)
xt "24000,112000,30400,113000"
st "DSRCLK : (3:0)"
blo "24000,112800"
tm "WireNameMgr"
)
)
on &132
)
*334 (Wire
uid 16247,0
shape (OrthoPolyLine
uid 16248,0
va (VaSet
vasetType 3
)
xt "34000,113000,51250,113000"
pts [
"51250,113000"
"34000,113000"
]
)
start &166
end &134
sat 32
eat 1
st 0
sf 1
si 0
tg (WTG
uid 16251,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16252,0
va (VaSet
)
xt "35000,112000,37900,113000"
st "SRCLK"
blo "35000,112800"
tm "WireNameMgr"
)
)
on &133
)
*335 (Wire
uid 16538,0
shape (OrthoPolyLine
uid 16539,0
va (VaSet
vasetType 3
)
xt "80750,130000,92000,130000"
pts [
"80750,130000"
"92000,130000"
]
)
start &181
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 16542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16543,0
va (VaSet
)
xt "82000,129000,92000,130000"
st "alarm_refclk_too_high"
blo "82000,129800"
tm "WireNameMgr"
)
)
on &138
)
*336 (Wire
uid 16546,0
shape (OrthoPolyLine
uid 16547,0
va (VaSet
vasetType 3
)
xt "80750,131000,91000,131000"
pts [
"80750,131000"
"91000,131000"
]
)
start &182
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 16550,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16551,0
va (VaSet
)
xt "82000,130000,91600,131000"
st "alarm_refclk_too_low"
blo "82000,130800"
tm "WireNameMgr"
)
)
on &139
)
*337 (Wire
uid 16576,0
shape (OrthoPolyLine
uid 16577,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,132000,92000,132000"
pts [
"80750,132000"
"92000,132000"
]
)
start &180
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16580,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16581,0
va (VaSet
)
xt "82000,131000,91600,132000"
st "counter_result : (11:0)"
blo "82000,131800"
tm "WireNameMgr"
)
)
on &140
)
*338 (Wire
uid 17296,0
shape (OrthoPolyLine
uid 17297,0
va (VaSet
vasetType 3
)
xt "13000,71000,51250,71000"
pts [
"51250,71000"
"13000,71000"
]
)
start &183
end &34
sat 32
eat 1
st 0
sf 1
si 0
tg (WTG
uid 17300,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17301,0
va (VaSet
)
xt "14000,70000,18000,71000"
st "ADC_CLK"
blo "14000,70800"
tm "WireNameMgr"
)
)
on &198
)
*339 (Wire
uid 17407,0
shape (OrthoPolyLine
uid 17408,0
va (VaSet
vasetType 3
)
xt "98000,144000,100000,144000"
pts [
"98000,144000"
"100000,144000"
]
)
start &268
end &199
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 17411,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17412,0
va (VaSet
isHidden 1
)
xt "100000,143000,102900,144000"
st "TRG_V"
blo "100000,143800"
tm "WireNameMgr"
)
)
on &200
)
*340 (Wire
uid 17848,0
shape (OrthoPolyLine
uid 17849,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,106000,91000,106000"
pts [
"80750,106000"
"91000,106000"
]
)
start &189
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 17852,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17853,0
va (VaSet
)
xt "82000,105000,90400,106000"
st "w5300_state : (7:0)"
blo "82000,105800"
tm "WireNameMgr"
)
)
on &201
)
*341 (Wire
uid 17856,0
shape (OrthoPolyLine
uid 17857,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "114000,118000,126000,118000"
pts [
"114000,118000"
"126000,118000"
]
)
end &102
sat 16
eat 1
sty 1
st 0
sf 1
si 0
tg (WTG
uid 17862,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17863,0
va (VaSet
)
xt "118000,117000,126400,118000"
st "w5300_state : (7:0)"
blo "118000,117800"
tm "WireNameMgr"
)
)
on &201
)
*342 (Wire
uid 18068,0
shape (OrthoPolyLine
uid 18069,0
va (VaSet
vasetType 3
)
xt "80750,107000,93000,107000"
pts [
"80750,107000"
"93000,107000"
]
)
start &190
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 18072,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18073,0
va (VaSet
)
xt "82000,106000,92400,107000"
st "debug_data_ram_empty"
blo "82000,106800"
tm "WireNameMgr"
)
)
on &202
)
*343 (Wire
uid 18076,0
shape (OrthoPolyLine
uid 18077,0
va (VaSet
vasetType 3
)
xt "80750,108000,91000,108000"
pts [
"80750,108000"
"91000,108000"
]
)
start &191
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 18080,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18081,0
va (VaSet
)
xt "82000,107000,89500,108000"
st "debug_data_valid"
blo "82000,107800"
tm "WireNameMgr"
)
)
on &203
)
*344 (Wire
uid 18207,0
shape (OrthoPolyLine
uid 18208,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,105000,94000,105000"
pts [
"80750,105000"
"94000,105000"
]
)
start &192
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 18211,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18212,0
va (VaSet
)
xt "82000,104000,93400,105000"
st "mem_manager_state : (3:0)"
blo "82000,104800"
tm "WireNameMgr"
)
)
on &204
)
*345 (Wire
uid 18328,0
shape (OrthoPolyLine
uid 18329,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,109000,90000,109000"
pts [
"80750,109000"
"90000,109000"
]
)
start &193
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 18332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18333,0
va (VaSet
)
xt "82000,108000,88900,109000"
st "DG_state : (7:0)"
blo "82000,108800"
tm "WireNameMgr"
)
)
on &205
)
*346 (Wire
uid 18336,0
shape (OrthoPolyLine
uid 18337,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "111000,112000,121000,112000"
pts [
"111000,112000"
"121000,112000"
]
)
sat 16
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 18342,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18343,0
va (VaSet
)
xt "113000,111000,119900,112000"
st "DG_state : (7:0)"
blo "113000,111800"
tm "WireNameMgr"
)
)
on &205
)
*347 (Wire
uid 18352,0
shape (OrthoPolyLine
uid 18353,0
va (VaSet
vasetType 3
)
xt "109000,114000,119000,114000"
pts [
"109000,114000"
"119000,114000"
]
)
sat 16
eat 16
st 0
sf 1
si 0
tg (WTG
uid 18358,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18359,0
va (VaSet
)
xt "111000,113000,118500,114000"
st "debug_data_valid"
blo "111000,113800"
tm "WireNameMgr"
)
)
on &203
)
*348 (Wire
uid 18360,0
shape (OrthoPolyLine
uid 18361,0
va (VaSet
vasetType 3
)
xt "113000,122000,126000,122000"
pts [
"113000,122000"
"126000,122000"
]
)
end &102
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 18366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18367,0
va (VaSet
)
xt "115000,121000,126400,122000"
st "mem_manager_state : (3:0)"
blo "115000,121800"
tm "WireNameMgr"
)
)
on &204
)
*349 (Wire
uid 18477,0
shape (OrthoPolyLine
uid 18478,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80750,151000,95000,151000"
pts [
"80750,151000"
"95000,151000"
]
)
start &194
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 18481,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18482,0
va (VaSet
)
xt "82000,150000,93900,151000"
st "socket_tx_free_out : (16:0)"
blo "82000,150800"
tm "WireNameMgr"
)
)
on &206
)
*350 (Wire
uid 18808,0
shape (OrthoPolyLine
uid 18809,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "132000,122000,137000,122000"
pts [
"132000,122000"
"137000,122000"
]
)
start &102
end &207
sat 2
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 18812,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18813,0
va (VaSet
isHidden 1
)
xt "134000,121000,139200,122000"
st "W_T : (3:0)"
blo "134000,121800"
tm "WireNameMgr"
)
)
on &208
)
*351 (Wire
uid 18923,0
shape (OrthoPolyLine
uid 18924,0
va (VaSet
vasetType 3
)
xt "113000,120000,126000,120000"
pts [
"113000,120000"
"126000,120000"
]
)
end &102
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 18929,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18930,0
va (VaSet
)
xt "114000,119000,125900,120000"
st "socket_tx_free_out : (16:0)"
blo "114000,119800"
tm "WireNameMgr"
)
)
on &206
)
*352 (Wire
uid 19161,0
shape (OrthoPolyLine
uid 19162,0
va (VaSet
vasetType 3
)
xt "116000,123000,126000,123000"
pts [
"116000,123000"
"126000,123000"
]
)
end &102
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 19167,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19168,0
va (VaSet
)
xt "118000,122000,120900,123000"
st "TRG_V"
blo "118000,122800"
tm "WireNameMgr"
)
)
on &200
)
*353 (Wire
uid 19169,0
shape (OrthoPolyLine
uid 19170,0
va (VaSet
vasetType 3
)
xt "116000,124000,126000,124000"
pts [
"116000,124000"
"126000,124000"
]
)
end &102
sat 16
eat 1
st 0
sf 1
si 0
tg (WTG
uid 19175,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19176,0
va (VaSet
)
xt "118000,123000,128400,124000"
st "debug_data_ram_empty"
blo "118000,123800"
tm "WireNameMgr"
)
)
on &202
)
*354 (Wire
uid 19533,0
shape (OrthoPolyLine
uid 19534,0
va (VaSet
vasetType 3
)
xt "80750,85000,82000,87000"
pts [
"80750,87000"
"82000,87000"
"82000,85000"
]
)
start &169
end &210
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19535,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19536,0
va (VaSet
)
xt "82750,86000,86150,87000"
st "dac_cs1"
blo "82750,86800"
tm "WireNameMgr"
)
)
on &261
)
*355 (Wire
uid 19539,0
shape (OrthoPolyLine
uid 19540,0
va (VaSet
vasetType 3
)
xt "80750,89000,82000,90000"
pts [
"80750,89000"
"82000,89000"
"82000,90000"
]
)
start &170
end &223
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19541,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19542,0
va (VaSet
)
xt "82750,88000,89750,89000"
st "sensor_cs : (3:0)"
blo "82750,88800"
tm "WireNameMgr"
)
)
on &262
)
*356 (Wire
uid 19545,0
shape (OrthoPolyLine
uid 19546,0
va (VaSet
vasetType 3
)
xt "80750,95000,83000,98000"
pts [
"80750,98000"
"83000,98000"
"83000,95000"
]
)
start &167
end &236
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19547,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19548,0
va (VaSet
)
xt "82750,97000,84650,98000"
st "sclk"
blo "82750,97800"
tm "WireNameMgr"
)
)
on &263
)
*357 (Wire
uid 19551,0
shape (OrthoPolyLine
uid 19552,0
va (VaSet
vasetType 3
)
xt "80750,100000,83000,102000"
pts [
"83000,102000"
"80750,102000"
"80750,100000"
]
)
start &249
end &171
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19553,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 19554,0
va (VaSet
isHidden 1
)
xt "82000,101000,84400,102000"
st "mosi1"
blo "82000,101800"
tm "WireNameMgr"
)
)
on &264
)
*358 (Wire
uid 20221,0
shape (OrthoPolyLine
uid 20222,0
va (VaSet
vasetType 3
)
xt "80750,144000,95000,144000"
pts [
"80750,144000"
"95000,144000"
]
)
start &184
end &266
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 20223,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20224,0
va (VaSet
)
xt "82000,143000,87600,144000"
st "trigger_veto"
blo "82000,143800"
tm "WireNameMgr"
)
)
on &278
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *359 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*360 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*361 (MLText
uid 43,0
va (VaSet
)
xt "0,1000,14500,9000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE IEEE.NUMERIC_STD.all;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*362 (Text
uid 45,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*363 (Text
uid 46,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*364 (MLText
uid 47,0
va (VaSet
isHidden 1
)
xt "20000,2000,27500,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*365 (Text
uid 48,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*366 (MLText
uid 49,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*367 (Text
uid 50,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*368 (MLText
uid 51,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1281,1024"
viewArea "-47112,-60564,234587,171751"
cachedDiagramExtent "-23000,0,489000,153000"
pageSetupInfo (PageSetupInfo
ptrCmd "FreePDF,winspool,"
fileName "FreePDFXP1:"
toPrinter 1
colour 1
xMargin 0
yMargin 0
paperWidth 3046
paperHeight 4310
windowsPaperWidth 3046
windowsPaperHeight 4310
paperType "A0"
windowsPaperName "A0"
windowsPaperType 133
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "-73000,0"
lastUid 20456,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*369 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*370 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*371 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,3200,6500"
st "I0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*372 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*373 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*374 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,1550,6500"
st "I0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*375 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*376 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*377 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,1900,6500"
st "I0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*378 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*379 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*380 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,1500,6500"
st "I0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*381 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*382 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*383 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1050,6500"
st "I0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*384 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*385 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*386 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*387 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*388 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*389 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "37000,1800,42400,2800"
st "Declarations"
blo "37000,2600"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "37000,2800,39700,3800"
st "Ports:"
blo "37000,3600"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "37000,1800,40800,2800"
st "Pre User:"
blo "37000,2600"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "37000,1800,37000,1800"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "37000,45400,44100,46400"
st "Diagram Signals:"
blo "37000,46200"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "37000,1800,41700,2800"
st "Post User:"
blo "37000,2600"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "37000,1800,37000,1800"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 249,0
usingSuid 1
emptyRow *390 (LEmptyRow
)
uid 54,0
optionalChildren [
*391 (RefLabelRowHdr
)
*392 (TitleRowHdr
)
*393 (FilterRowHdr
)
*394 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*395 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*396 (GroupColHdr
tm "GroupColHdrMgr"
)
*397 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*398 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*399 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*400 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*401 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*402 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*403 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 60
suid 5,0
)
)
uid 327,0
)
*404 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 62
suid 6,0
)
)
uid 329,0
)
*405 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 57
suid 29,0
)
)
uid 1491,0
)
*406 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 40
suid 57,0
i "'0'"
)
)
uid 2435,0
)
*407 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DAC_CS"
t "std_logic"
o 22
suid 66,0
)
)
uid 3039,0
)
*408 (LeafLogPort
port (LogicalPort
decl (Decl
n "X_50M"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 17
suid 67,0
)
)
uid 3276,0
)
*409 (LeafLogPort
port (LogicalPort
decl (Decl
n "TRG"
t "STD_LOGIC"
o 15
suid 68,0
)
)
uid 3278,0
)
*410 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "A_CLK"
t "std_logic_vector"
b "(3 downto 0)"
o 21
suid 71,0
)
)
uid 3280,0
)
*411 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "OE_ADC"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 32
suid 73,0
)
)
uid 3382,0
)
*412 (LeafLogPort
port (LogicalPort
decl (Decl
n "A_OTR"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 74,0
)
)
uid 3384,0
)
*413 (LeafLogPort
port (LogicalPort
decl (Decl
n "A0_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 1
suid 79,0
)
)
uid 3386,0
)
*414 (LeafLogPort
port (LogicalPort
decl (Decl
n "A1_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 2
suid 80,0
)
)
uid 3388,0
)
*415 (LeafLogPort
port (LogicalPort
decl (Decl
n "A2_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 3
suid 81,0
)
)
uid 3390,0
)
*416 (LeafLogPort
port (LogicalPort
decl (Decl
n "A3_D"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 4
suid 82,0
)
)
uid 3392,0
)
*417 (LeafLogPort
port (LogicalPort
decl (Decl
n "D0_SROUT"
t "std_logic"
o 6
suid 91,0
)
)
uid 3524,0
)
*418 (LeafLogPort
port (LogicalPort
decl (Decl
n "D1_SROUT"
t "std_logic"
o 7
suid 92,0
)
)
uid 3526,0
)
*419 (LeafLogPort
port (LogicalPort
decl (Decl
n "D2_SROUT"
t "std_logic"
o 8
suid 93,0
)
)
uid 3528,0
)
*420 (LeafLogPort
port (LogicalPort
decl (Decl
n "D3_SROUT"
t "std_logic"
o 9
suid 94,0
)
)
uid 3530,0
)
*421 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "D_A"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 26
suid 95,0
i "(others => '0')"
)
)
uid 3532,0
)
*422 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DWRITE"
t "std_logic"
o 25
suid 96,0
i "'0'"
)
)
uid 3534,0
)
*423 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "S_CLK"
t "std_logic"
o 42
suid 105,0
)
)
uid 3654,0
)
*424 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "W_A"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 45
suid 106,0
)
)
uid 3656,0
)
*425 (LeafLogPort
port (LogicalPort
m 2
decl (Decl
n "W_D"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 52
suid 107,0
)
)
uid 3658,0
)
*426 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "W_RES"
t "std_logic"
o 48
suid 108,0
i "'1'"
)
)
uid 3660,0
)
*427 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "W_RD"
t "std_logic"
o 47
suid 109,0
i "'1'"
)
)
uid 3662,0
)
*428 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "W_WR"
t "std_logic"
o 50
suid 110,0
i "'1'"
)
)
uid 3664,0
)
*429 (LeafLogPort
port (LogicalPort
decl (Decl
n "W_INT"
t "std_logic"
o 16
suid 111,0
)
)
uid 3666,0
)
*430 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "W_CS"
t "std_logic"
o 46
suid 112,0
i "'1'"
)
)
uid 3668,0
)
*431 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "MOSI"
t "std_logic"
o 31
suid 113,0
i "'0'"
)
)
uid 3696,0
)
*432 (LeafLogPort
port (LogicalPort
m 2
decl (Decl
n "MISO"
t "std_logic"
preAdd 0
posAdd 0
o 51
suid 114,0
)
)
uid 3698,0
)
*433 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_C_RE"
t "std_logic"
o 36
suid 127,0
)
)
uid 3888,0
)
*434 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_C_DE"
t "std_logic"
o 34
suid 128,0
)
)
uid 3890,0
)
*435 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_E_RE"
t "std_logic"
o 39
suid 129,0
)
)
uid 3892,0
)
*436 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_E_DE"
t "std_logic"
o 37
suid 130,0
)
)
uid 3894,0
)
*437 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DENABLE"
t "std_logic"
o 23
suid 131,0
i "'0'"
)
)
uid 3896,0
)
*438 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "EE_CS"
t "std_logic"
o 29
suid 133,0
)
)
uid 3900,0
)
*439 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "D_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 27
suid 141,0
i "(OTHERS => '0')"
)
)
uid 5322,0
)
*440 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "D_T2"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 28
suid 154,0
i "(others => '0')"
)
)
uid 6872,0
scheme 0
)
*441 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "A1_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 19
suid 155,0
i "(OTHERS => '0')"
)
)
uid 7134,0
scheme 0
)
*442 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_50"
t "std_logic"
o 54
suid 163,0
)
)
uid 9516,0
)
*443 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "A0_T"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 18
suid 166,0
i "(others => '0')"
)
)
uid 10294,0
scheme 0
)
*444 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_C_DO"
t "std_logic"
o 35
suid 198,0
)
)
uid 11086,0
scheme 0
)
*445 (LeafLogPort
port (LogicalPort
decl (Decl
n "RS485_E_DI"
t "std_logic"
o 14
suid 200,0
)
)
uid 11504,0
scheme 0
)
*446 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RS485_E_DO"
t "std_logic"
o 38
suid 201,0
)
)
uid 11506,0
scheme 0
)
*447 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "SRIN"
t "std_logic"
o 41
suid 203,0
i "'0'"
)
)
uid 12336,0
)
*448 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "AMBER_LED"
t "std_logic"
o 20
suid 207,0
)
)
uid 12768,0
)
*449 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "GREEN_LED"
t "std_logic"
o 30
suid 208,0
)
)
uid 12770,0
)
*450 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RED_LED"
t "std_logic"
o 33
suid 209,0
)
)
uid 12772,0
)
*451 (LeafLogPort
port (LogicalPort
decl (Decl
n "LINE"
t "std_logic_vector"
b "( 5 DOWNTO 0 )"
o 12
suid 210,0
)
)
uid 13514,0
scheme 0
)
*452 (LeafLogPort
port (LogicalPort
decl (Decl
n "REFCLK"
t "std_logic"
o 13
suid 211,0
)
)
uid 13626,0
scheme 0
)
*453 (LeafLogPort
port (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 213,0
)
)
uid 14320,0
scheme 0
)
*454 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 65
suid 215,0
i "(OTHERS => '0')"
)
)
uid 15181,0
)
*455 (LeafLogPort
port (LogicalPort
decl (Decl
n "D_PLLLCK"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 216,0
)
)
uid 15704,0
scheme 0
)
*456 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "TCS"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 217,0
)
)
uid 15843,0
scheme 0
)
*457 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DSRCLK"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 222,0
i "(others => '0')"
)
)
uid 16055,0
scheme 0
)
*458 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRCLK"
t "std_logic"
o 56
suid 225,0
i "'0'"
)
)
uid 16253,0
)
*459 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 58
suid 226,0
i "'0'"
)
)
uid 16582,0
)
*460 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
o 59
suid 227,0
i "'0'"
)
)
uid 16584,0
)
*461 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 downto 0)"
o 61
suid 230,0
i "(others => '0')"
)
)
uid 16586,0
)
*462 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "ADC_CLK"
t "std_logic"
o 53
suid 231,0
)
)
uid 17310,0
)
*463 (LeafLogPort
port (LogicalPort
lang 2
m 1
decl (Decl
n "TRG_V"
t "std_logic"
o 44
suid 232,0
i "'0'"
)
)
uid 17399,0
scheme 0
)
*464 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 68
suid 233,0
)
)
uid 17854,0
)
*465 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 63
suid 234,0
)
)
uid 18082,0
)
*466 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "debug_data_valid"
t "std_logic"
o 64
suid 235,0
)
)
uid 18084,0
)
*467 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 66
suid 237,0
)
)
uid 18213,0
)
*468 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 55
suid 238,0
)
)
uid 18334,0
)
*469 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 67
suid 239,0
)
)
uid 18483,0
)
*470 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "W_T"
t "std_logic_vector"
b "( 3 DOWNTO 0 )"
o 49
suid 240,0
i "(others => '0')"
)
)
uid 18800,0
scheme 0
)
*471 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dac_cs1"
t "std_logic"
o 69
suid 241,0
)
)
uid 19557,0
)
*472 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 70
suid 242,0
)
)
uid 19559,0
)
*473 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sclk"
t "std_logic"
o 71
suid 243,0
)
)
uid 19561,0
)
*474 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "mosi1"
t "std_logic"
o 72
suid 245,0
)
)
uid 19563,0
)
*475 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_veto"
t "std_logic"
o 73
suid 249,0
i "'1'"
)
)
uid 20225,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*476 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *477 (MRCItem
litem &390
pos 73
dimension 20
)
uid 69,0
optionalChildren [
*478 (MRCItem
litem &391
pos 0
dimension 20
uid 70,0
)
*479 (MRCItem
litem &392
pos 1
dimension 23
uid 71,0
)
*480 (MRCItem
litem &393
pos 2
hidden 1
dimension 20
uid 72,0
)
*481 (MRCItem
litem &403
pos 52
dimension 20
uid 328,0
)
*482 (MRCItem
litem &404
pos 53
dimension 20
uid 330,0
)
*483 (MRCItem
litem &405
pos 54
dimension 20
uid 1492,0
)
*484 (MRCItem
litem &406
pos 0
dimension 20
uid 2436,0
)
*485 (MRCItem
litem &407
pos 1
dimension 20
uid 3040,0
)
*486 (MRCItem
litem &408
pos 2
dimension 20
uid 3277,0
)
*487 (MRCItem
litem &409
pos 3
dimension 20
uid 3279,0
)
*488 (MRCItem
litem &410
pos 4
dimension 20
uid 3281,0
)
*489 (MRCItem
litem &411
pos 5
dimension 20
uid 3383,0
)
*490 (MRCItem
litem &412
pos 6
dimension 20
uid 3385,0
)
*491 (MRCItem
litem &413
pos 7
dimension 20
uid 3387,0
)
*492 (MRCItem
litem &414
pos 8
dimension 20
uid 3389,0
)
*493 (MRCItem
litem &415
pos 9
dimension 20
uid 3391,0
)
*494 (MRCItem
litem &416
pos 10
dimension 20
uid 3393,0
)
*495 (MRCItem
litem &417
pos 11
dimension 20
uid 3525,0
)
*496 (MRCItem
litem &418
pos 12
dimension 20
uid 3527,0
)
*497 (MRCItem
litem &419
pos 13
dimension 20
uid 3529,0
)
*498 (MRCItem
litem &420
pos 14
dimension 20
uid 3531,0
)
*499 (MRCItem
litem &421
pos 15
dimension 20
uid 3533,0
)
*500 (MRCItem
litem &422
pos 16
dimension 20
uid 3535,0
)
*501 (MRCItem
litem &423
pos 17
dimension 20
uid 3655,0
)
*502 (MRCItem
litem &424
pos 18
dimension 20
uid 3657,0
)
*503 (MRCItem
litem &425
pos 19
dimension 20
uid 3659,0
)
*504 (MRCItem
litem &426
pos 20
dimension 20
uid 3661,0
)
*505 (MRCItem
litem &427
pos 21
dimension 20
uid 3663,0
)
*506 (MRCItem
litem &428
pos 22
dimension 20
uid 3665,0
)
*507 (MRCItem
litem &429
pos 23
dimension 20
uid 3667,0
)
*508 (MRCItem
litem &430
pos 24
dimension 20
uid 3669,0
)
*509 (MRCItem
litem &431
pos 25
dimension 20
uid 3697,0
)
*510 (MRCItem
litem &432
pos 26
dimension 20
uid 3699,0
)
*511 (MRCItem
litem &433
pos 27
dimension 20
uid 3889,0
)
*512 (MRCItem
litem &434
pos 28
dimension 20
uid 3891,0
)
*513 (MRCItem
litem &435
pos 29
dimension 20
uid 3893,0
)
*514 (MRCItem
litem &436
pos 30
dimension 20
uid 3895,0
)
*515 (MRCItem
litem &437
pos 31
dimension 20
uid 3897,0
)
*516 (MRCItem
litem &438
pos 32
dimension 20
uid 3901,0
)
*517 (MRCItem
litem &439
pos 33
dimension 20
uid 5323,0
)
*518 (MRCItem
litem &440
pos 34
dimension 20
uid 6873,0
)
*519 (MRCItem
litem &441
pos 35
dimension 20
uid 7135,0
)
*520 (MRCItem
litem &442
pos 55
dimension 20
uid 9517,0
)
*521 (MRCItem
litem &443
pos 36
dimension 20
uid 10295,0
)
*522 (MRCItem
litem &444
pos 37
dimension 20
uid 11087,0
)
*523 (MRCItem
litem &445
pos 38
dimension 20
uid 11505,0
)
*524 (MRCItem
litem &446
pos 39
dimension 20
uid 11507,0
)
*525 (MRCItem
litem &447
pos 40
dimension 20
uid 12337,0
)
*526 (MRCItem
litem &448
pos 41
dimension 20
uid 12769,0
)
*527 (MRCItem
litem &449
pos 42
dimension 20
uid 12771,0
)
*528 (MRCItem
litem &450
pos 43
dimension 20
uid 12773,0
)
*529 (MRCItem
litem &451
pos 44
dimension 20
uid 13515,0
)
*530 (MRCItem
litem &452
pos 45
dimension 20
uid 13627,0
)
*531 (MRCItem
litem &453
pos 46
dimension 20
uid 14321,0
)
*532 (MRCItem
litem &454
pos 56
dimension 20
uid 15182,0
)
*533 (MRCItem
litem &455
pos 47
dimension 20
uid 15705,0
)
*534 (MRCItem
litem &456
pos 48
dimension 20
uid 15844,0
)
*535 (MRCItem
litem &457
pos 49
dimension 20
uid 16056,0
)
*536 (MRCItem
litem &458
pos 57
dimension 20
uid 16254,0
)
*537 (MRCItem
litem &459
pos 58
dimension 20
uid 16583,0
)
*538 (MRCItem
litem &460
pos 59
dimension 20
uid 16585,0
)
*539 (MRCItem
litem &461
pos 60
dimension 20
uid 16587,0
)
*540 (MRCItem
litem &462
pos 61
dimension 20
uid 17311,0
)
*541 (MRCItem
litem &463
pos 50
dimension 20
uid 17400,0
)
*542 (MRCItem
litem &464
pos 62
dimension 20
uid 17855,0
)
*543 (MRCItem
litem &465
pos 63
dimension 20
uid 18083,0
)
*544 (MRCItem
litem &466
pos 64
dimension 20
uid 18085,0
)
*545 (MRCItem
litem &467
pos 65
dimension 20
uid 18214,0
)
*546 (MRCItem
litem &468
pos 66
dimension 20
uid 18335,0
)
*547 (MRCItem
litem &469
pos 67
dimension 20
uid 18484,0
)
*548 (MRCItem
litem &470
pos 51
dimension 20
uid 18801,0
)
*549 (MRCItem
litem &471
pos 68
dimension 20
uid 19558,0
)
*550 (MRCItem
litem &472
pos 69
dimension 20
uid 19560,0
)
*551 (MRCItem
litem &473
pos 70
dimension 20
uid 19562,0
)
*552 (MRCItem
litem &474
pos 71
dimension 20
uid 19564,0
)
*553 (MRCItem
litem &475
pos 72
dimension 20
uid 20226,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 73,0
optionalChildren [
*554 (MRCItem
litem &394
pos 0
dimension 20
uid 74,0
)
*555 (MRCItem
litem &396
pos 1
dimension 50
uid 75,0
)
*556 (MRCItem
litem &397
pos 2
dimension 100
uid 76,0
)
*557 (MRCItem
litem &398
pos 3
dimension 50
uid 77,0
)
*558 (MRCItem
litem &399
pos 4
dimension 100
uid 78,0
)
*559 (MRCItem
litem &400
pos 5
dimension 100
uid 79,0
)
*560 (MRCItem
litem &401
pos 6
dimension 182
uid 80,0
)
*561 (MRCItem
litem &402
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *562 (LEmptyRow
)
uid 83,0
optionalChildren [
*563 (RefLabelRowHdr
)
*564 (TitleRowHdr
)
*565 (FilterRowHdr
)
*566 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*567 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*568 (GroupColHdr
tm "GroupColHdrMgr"
)
*569 (NameColHdr
tm "GenericNameColHdrMgr"
)
*570 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*571 (InitColHdr
tm "GenericValueColHdrMgr"
)
*572 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*573 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
*574 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *575 (MRCItem
litem &562
pos 0
dimension 20
)
uid 97,0
optionalChildren [
*576 (MRCItem
litem &563
pos 0
dimension 20
uid 98,0
)
*577 (MRCItem
litem &564
pos 1
dimension 23
uid 99,0
)
*578 (MRCItem
litem &565
pos 2
hidden 1
dimension 20
uid 100,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 101,0
optionalChildren [
*579 (MRCItem
litem &566
pos 0
dimension 20
uid 102,0
)
*580 (MRCItem
litem &568
pos 1
dimension 50
uid 103,0
)
*581 (MRCItem
litem &569
pos 2
dimension 100
uid 104,0
)
*582 (MRCItem
litem &570
pos 3
dimension 100
uid 105,0
)
*583 (MRCItem
litem &571
pos 4
dimension 50
uid 106,0
)
*584 (MRCItem
litem &572
pos 5
dimension 50
uid 107,0
)
*585 (MRCItem
litem &573
pos 6
dimension 80
uid 108,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)