source: firmware/FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd@ 19875

Last change on this file since 19875 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 178.9 KB
Line 
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1020va (VaSet
1021vasetType 1
1022fg "0,0,32768"
1023)
1024optionalChildren [
1025(Hexagon
1026uid 492,0
1027sl 0
1028xt "90500,68625,92000,69375"
1029)
1030(Line
1031uid 493,0
1032sl 0
1033xt "90000,69000,90500,69000"
1034pts [
1035"90000,69000"
1036"90500,69000"
1037]
1038)
1039]
1040)
1041stc 0
1042sf 1
1043tg (WTG
1044uid 494,0
1045ps "PortIoTextPlaceStrategy"
1046stg "STSignalDisplayStrategy"
1047f (Text
1048uid 495,0
1049va (VaSet
1050)
1051xt "93000,68500,95400,69500"
1052st "W_D"
1053blo "93000,69300"
1054tm "WireNameMgr"
1055)
1056)
1057)
1058*24 (PortIoIn
1059uid 496,0
1060shape (CompositeShape
1061uid 497,0
1062va (VaSet
1063vasetType 1
1064fg "0,0,32768"
1065)
1066optionalChildren [
1067(Pentagon
1068uid 498,0
1069sl 0
1070ro 90
1071xt "90500,73625,92000,74375"
1072)
1073(Line
1074uid 499,0
1075sl 0
1076ro 90
1077xt "90000,74000,90500,74000"
1078pts [
1079"90500,74000"
1080"90000,74000"
1081]
1082)
1083]
1084)
1085stc 0
1086sf 1
1087tg (WTG
1088uid 500,0
1089ps "PortIoTextPlaceStrategy"
1090stg "STSignalDisplayStrategy"
1091f (Text
1092uid 501,0
1093va (VaSet
1094)
1095xt "93000,73500,96300,74500"
1096st "W_INT"
1097blo "93000,74300"
1098tm "WireNameMgr"
1099)
1100)
1101)
1102*25 (PortIoOut
1103uid 502,0
1104shape (CompositeShape
1105uid 503,0
1106va (VaSet
1107vasetType 1
1108fg "0,0,32768"
1109)
1110optionalChildren [
1111(Pentagon
1112uid 504,0
1113sl 0
1114ro 270
1115xt "90500,71625,92000,72375"
1116)
1117(Line
1118uid 505,0
1119sl 0
1120ro 270
1121xt "90000,72000,90500,72000"
1122pts [
1123"90000,72000"
1124"90500,72000"
1125]
1126)
1127]
1128)
1129stc 0
1130sf 1
1131tg (WTG
1132uid 506,0
1133ps "PortIoTextPlaceStrategy"
1134stg "STSignalDisplayStrategy"
1135f (Text
1136uid 507,0
1137va (VaSet
1138)
1139xt "93000,71500,95900,72500"
1140st "W_RD"
1141blo "93000,72300"
1142tm "WireNameMgr"
1143)
1144)
1145)
1146*26 (PortIoOut
1147uid 508,0
1148shape (CompositeShape
1149uid 509,0
1150va (VaSet
1151vasetType 1
1152fg "0,0,32768"
1153)
1154optionalChildren [
1155(Pentagon
1156uid 510,0
1157sl 0
1158ro 270
1159xt "90500,72625,92000,73375"
1160)
1161(Line
1162uid 511,0
1163sl 0
1164ro 270
1165xt "90000,73000,90500,73000"
1166pts [
1167"90000,73000"
1168"90500,73000"
1169]
1170)
1171]
1172)
1173stc 0
1174sf 1
1175tg (WTG
1176uid 512,0
1177ps "PortIoTextPlaceStrategy"
1178stg "STSignalDisplayStrategy"
1179f (Text
1180uid 513,0
1181va (VaSet
1182)
1183xt "93000,72500,96200,73500"
1184st "W_WR"
1185blo "93000,73300"
1186tm "WireNameMgr"
1187)
1188)
1189)
1190*27 (Net
1191uid 1465,0
1192decl (Decl
1193n "adc_data_array"
1194t "adc_data_array_type"
1195o 57
1196suid 29,0
1197)
1198declText (MLText
1199uid 1466,0
1200va (VaSet
1201font "Courier New,8,0"
1202)
1203xt "39000,50400,66000,51200"
1204st "SIGNAL adc_data_array : adc_data_array_type"
1205)
1206)
1207*28 (Net
1208uid 2407,0
1209decl (Decl
1210n "RSRLOAD"
1211t "std_logic"
1212o 40
1213suid 57,0
1214i "'0'"
1215)
1216declText (MLText
1217uid 2408,0
1218va (VaSet
1219font "Courier New,8,0"
1220)
1221xt "39000,35000,71500,35800"
1222st "RSRLOAD : std_logic := '0'"
1223)
1224)
1225*29 (PortIoOut
1226uid 2415,0
1227shape (CompositeShape
1228uid 2416,0
1229va (VaSet
1230vasetType 1
1231fg "0,0,32768"
1232)
1233optionalChildren [
1234(Pentagon
1235uid 2417,0
1236sl 0
1237ro 90
1238xt "19000,110625,20500,111375"
1239)
1240(Line
1241uid 2418,0
1242sl 0
1243ro 90
1244xt "20500,111000,21000,111000"
1245pts [
1246"21000,111000"
1247"20500,111000"
1248]
1249)
1250]
1251)
1252stc 0
1253sf 1
1254tg (WTG
1255uid 2419,0
1256ps "PortIoTextPlaceStrategy"
1257stg "STSignalDisplayStrategy"
1258f (Text
1259uid 2420,0
1260va (VaSet
1261)
1262xt "13800,110500,18000,111500"
1263st "RSRLOAD"
1264ju 2
1265blo "18000,111300"
1266tm "WireNameMgr"
1267)
1268)
1269)
1270*30 (Net
1271uid 3025,0
1272decl (Decl
1273n "DAC_CS"
1274t "std_logic"
1275o 22
1276suid 66,0
1277)
1278declText (MLText
1279uid 3026,0
1280va (VaSet
1281font "Courier New,8,0"
1282)
1283xt "39000,20600,57000,21400"
1284st "DAC_CS : std_logic"
1285)
1286)
1287*31 (PortIoOut
1288uid 3153,0
1289shape (CompositeShape
1290uid 3154,0
1291va (VaSet
1292vasetType 1
1293fg "0,0,32768"
1294)
1295optionalChildren [
1296(Pentagon
1297uid 3155,0
1298sl 0
1299ro 90
1300xt "-3000,70625,-1500,71375"
1301)
1302(Line
1303uid 3156,0
1304sl 0
1305ro 90
1306xt "-1500,71000,-1000,71000"
1307pts [
1308"-1000,71000"
1309"-1500,71000"
1310]
1311)
1312]
1313)
1314stc 0
1315sf 1
1316tg (WTG
1317uid 3157,0
1318ps "PortIoTextPlaceStrategy"
1319stg "STSignalDisplayStrategy"
1320f (Text
1321uid 3158,0
1322va (VaSet
1323)
1324xt "-6900,70500,-4000,71500"
1325st "A_CLK"
1326ju 2
1327blo "-4000,71300"
1328tm "WireNameMgr"
1329)
1330)
1331)
1332*32 (Net
1333uid 3216,0
1334decl (Decl
1335n "X_50M"
1336t "STD_LOGIC"
1337preAdd 0
1338posAdd 0
1339o 17
1340suid 67,0
1341)
1342declText (MLText
1343uid 3217,0
1344va (VaSet
1345font "Courier New,8,0"
1346)
1347xt "39000,16600,57000,17400"
1348st "X_50M : STD_LOGIC"
1349)
1350)
1351*33 (Net
1352uid 3226,0
1353decl (Decl
1354n "TRG"
1355t "STD_LOGIC"
1356o 15
1357suid 68,0
1358)
1359declText (MLText
1360uid 3227,0
1361va (VaSet
1362font "Courier New,8,0"
1363)
1364xt "39000,15000,57000,15800"
1365st "TRG : STD_LOGIC"
1366)
1367)
1368*34 (HdlText
1369uid 3248,0
1370optionalChildren [
1371*35 (EmbeddedText
1372uid 3254,0
1373commentText (CommentText
1374uid 3255,0
1375ps "CenterOffsetStrategy"
1376shape (Rectangle
1377uid 3256,0
1378va (VaSet
1379vasetType 1
1380fg "65535,65535,65535"
1381lineColor "0,0,32768"
1382lineWidth 2
1383)
1384xt "-14000,63000,12000,69000"
1385)
1386oxt "0,0,18000,5000"
1387text (MLText
1388uid 3257,0
1389va (VaSet
1390)
1391xt "-13800,63200,-8900,69200"
1392st "
1393A_CLK <= (
1394ADC_CLK,
1395ADC_CLK,
1396ADC_CLK,
1397ADC_CLK
1398);
1399
1400"
1401tm "HdlTextMgr"
1402wrapOption 3
1403visibleHeight 6000
1404visibleWidth 26000
1405)
1406)
1407)
1408]
1409shape (Rectangle
1410uid 3249,0
1411va (VaSet
1412vasetType 1
1413fg "65535,65535,37120"
1414lineColor "0,0,32768"
1415lineWidth 2
1416)
1417xt "5000,70000,13000,73000"
1418)
1419oxt "0,0,8000,10000"
1420ttg (MlTextGroup
1421uid 3250,0
1422ps "CenterOffsetStrategy"
1423stg "VerticalLayoutStrategy"
1424textVec [
1425*36 (Text
1426uid 3251,0
1427va (VaSet
1428font "Arial,8,1"
1429)
1430xt "6150,70000,10350,71000"
1431st "ADC_CLK"
1432blo "6150,70800"
1433tm "HdlTextNameMgr"
1434)
1435*37 (Text
1436uid 3252,0
1437va (VaSet
1438font "Arial,8,1"
1439)
1440xt "6150,71000,6950,72000"
1441st "2"
1442blo "6150,71800"
1443tm "HdlTextNumberMgr"
1444)
1445]
1446)
1447viewicon (ZoomableIcon
1448uid 3253,0
1449sl 0
1450va (VaSet
1451vasetType 1
1452fg "49152,49152,49152"
1453)
1454xt "5250,71250,6750,72750"
1455iconName "TextFile.png"
1456iconMaskName "TextFile.msk"
1457ftype 21
1458)
1459viewiconposition 0
1460)
1461*38 (Net
1462uid 3266,0
1463decl (Decl
1464n "A_CLK"
1465t "std_logic_vector"
1466b "(3 downto 0)"
1467o 21
1468suid 71,0
1469)
1470declText (MLText
1471uid 3267,0
1472va (VaSet
1473font "Courier New,8,0"
1474)
1475xt "39000,19800,67000,20600"
1476st "A_CLK : std_logic_vector(3 downto 0)"
1477)
1478)
1479*39 (PortIoOut
1480uid 3284,0
1481shape (CompositeShape
1482uid 3285,0
1483va (VaSet
1484vasetType 1
1485fg "0,0,32768"
1486)
1487optionalChildren [
1488(Pentagon
1489uid 3286,0
1490sl 0
1491ro 90
1492xt "19000,89625,20500,90375"
1493)
1494(Line
1495uid 3287,0
1496sl 0
1497ro 90
1498xt "20500,90000,21000,90000"
1499pts [
1500"21000,90000"
1501"20500,90000"
1502]
1503)
1504]
1505)
1506stc 0
1507sf 1
1508tg (WTG
1509uid 3288,0
1510ps "PortIoTextPlaceStrategy"
1511stg "STSignalDisplayStrategy"
1512f (Text
1513uid 3289,0
1514va (VaSet
1515)
1516xt "14300,89500,18000,90500"
1517st "OE_ADC"
1518ju 2
1519blo "18000,90300"
1520tm "WireNameMgr"
1521)
1522)
1523)
1524*40 (Net
1525uid 3290,0
1526decl (Decl
1527n "OE_ADC"
1528t "STD_LOGIC"
1529preAdd 0
1530posAdd 0
1531o 32
1532suid 73,0
1533)
1534declText (MLText
1535uid 3291,0
1536va (VaSet
1537font "Courier New,8,0"
1538)
1539xt "39000,28600,57000,29400"
1540st "OE_ADC : STD_LOGIC"
1541)
1542)
1543*41 (PortIoIn
1544uid 3292,0
1545shape (CompositeShape
1546uid 3293,0
1547va (VaSet
1548vasetType 1
1549fg "0,0,32768"
1550)
1551optionalChildren [
1552(Pentagon
1553uid 3294,0
1554sl 0
1555ro 270
1556xt "19000,88625,20500,89375"
1557)
1558(Line
1559uid 3295,0
1560sl 0
1561ro 270
1562xt "20500,89000,21000,89000"
1563pts [
1564"20500,89000"
1565"21000,89000"
1566]
1567)
1568]
1569)
1570stc 0
1571sf 1
1572tg (WTG
1573uid 3296,0
1574ps "PortIoTextPlaceStrategy"
1575stg "STSignalDisplayStrategy"
1576f (Text
1577uid 3297,0
1578va (VaSet
1579)
1580xt "14900,88500,18000,89500"
1581st "A_OTR"
1582ju 2
1583blo "18000,89300"
1584tm "WireNameMgr"
1585)
1586)
1587)
1588*42 (Net
1589uid 3298,0
1590decl (Decl
1591n "A_OTR"
1592t "std_logic_vector"
1593b "(3 DOWNTO 0)"
1594o 5
1595suid 74,0
1596)
1597declText (MLText
1598uid 3299,0
1599va (VaSet
1600font "Courier New,8,0"
1601)
1602xt "39000,7000,67000,7800"
1603st "A_OTR : std_logic_vector(3 DOWNTO 0)"
1604)
1605)
1606*43 (HdlText
1607uid 3300,0
1608optionalChildren [
1609*44 (EmbeddedText
1610uid 3306,0
1611commentText (CommentText
1612uid 3307,0
1613ps "CenterOffsetStrategy"
1614shape (Rectangle
1615uid 3308,0
1616va (VaSet
1617vasetType 1
1618fg "65535,65535,65535"
1619lineColor "0,0,32768"
1620lineWidth 2
1621)
1622xt "19000,99000,38000,101000"
1623)
1624oxt "0,0,18000,5000"
1625text (MLText
1626uid 3309,0
1627va (VaSet
1628)
1629xt "19200,99200,37300,100200"
1630st "
1631adc_data_array <= ( A0_D, A1_D, A2_D, A3_D );
1632
1633"
1634tm "HdlTextMgr"
1635wrapOption 3
1636visibleHeight 2000
1637visibleWidth 19000
1638)
1639)
1640)
1641]
1642shape (Rectangle
1643uid 3301,0
1644va (VaSet
1645vasetType 1
1646fg "65535,65535,37120"
1647lineColor "0,0,32768"
1648lineWidth 2
1649)
1650xt "24000,94000,30000,99000"
1651)
1652oxt "0,0,8000,10000"
1653ttg (MlTextGroup
1654uid 3302,0
1655ps "CenterOffsetStrategy"
1656stg "VerticalLayoutStrategy"
1657textVec [
1658*45 (Text
1659uid 3303,0
1660va (VaSet
1661font "Arial,8,1"
1662)
1663xt "27150,95000,31750,96000"
1664st "ADC_DATA"
1665blo "27150,95800"
1666tm "HdlTextNameMgr"
1667)
1668*46 (Text
1669uid 3304,0
1670va (VaSet
1671font "Arial,8,1"
1672)
1673xt "27150,96000,27950,97000"
1674st "3"
1675blo "27150,96800"
1676tm "HdlTextNumberMgr"
1677)
1678]
1679)
1680viewicon (ZoomableIcon
1681uid 3305,0
1682sl 0
1683va (VaSet
1684vasetType 1
1685fg "49152,49152,49152"
1686)
1687xt "24250,97250,25750,98750"
1688iconName "TextFile.png"
1689iconMaskName "TextFile.msk"
1690ftype 21
1691)
1692viewiconposition 0
1693)
1694*47 (PortIoIn
1695uid 3310,0
1696shape (CompositeShape
1697uid 3311,0
1698va (VaSet
1699vasetType 1
1700fg "0,0,32768"
1701)
1702optionalChildren [
1703(Pentagon
1704uid 3312,0
1705sl 0
1706ro 270
1707xt "19000,94625,20500,95375"
1708)
1709(Line
1710uid 3313,0
1711sl 0
1712ro 270
1713xt "20500,95000,21000,95000"
1714pts [
1715"20500,95000"
1716"21000,95000"
1717]
1718)
1719]
1720)
1721stc 0
1722sf 1
1723tg (WTG
1724uid 3314,0
1725ps "PortIoTextPlaceStrategy"
1726stg "STSignalDisplayStrategy"
1727f (Text
1728uid 3315,0
1729va (VaSet
1730)
1731xt "15400,94500,18000,95500"
1732st "A0_D"
1733ju 2
1734blo "18000,95300"
1735tm "WireNameMgr"
1736)
1737)
1738)
1739*48 (PortIoIn
1740uid 3332,0
1741shape (CompositeShape
1742uid 3333,0
1743va (VaSet
1744vasetType 1
1745fg "0,0,32768"
1746)
1747optionalChildren [
1748(Pentagon
1749uid 3334,0
1750sl 0
1751ro 270
1752xt "19000,95625,20500,96375"
1753)
1754(Line
1755uid 3335,0
1756sl 0
1757ro 270
1758xt "20500,96000,21000,96000"
1759pts [
1760"20500,96000"
1761"21000,96000"
1762]
1763)
1764]
1765)
1766stc 0
1767sf 1
1768tg (WTG
1769uid 3336,0
1770ps "PortIoTextPlaceStrategy"
1771stg "STSignalDisplayStrategy"
1772f (Text
1773uid 3337,0
1774va (VaSet
1775)
1776xt "15500,95500,18000,96500"
1777st "A1_D"
1778ju 2
1779blo "18000,96300"
1780tm "WireNameMgr"
1781)
1782)
1783)
1784*49 (PortIoIn
1785uid 3338,0
1786shape (CompositeShape
1787uid 3339,0
1788va (VaSet
1789vasetType 1
1790fg "0,0,32768"
1791)
1792optionalChildren [
1793(Pentagon
1794uid 3340,0
1795sl 0
1796ro 270
1797xt "19000,96625,20500,97375"
1798)
1799(Line
1800uid 3341,0
1801sl 0
1802ro 270
1803xt "20500,97000,21000,97000"
1804pts [
1805"20500,97000"
1806"21000,97000"
1807]
1808)
1809]
1810)
1811stc 0
1812sf 1
1813tg (WTG
1814uid 3342,0
1815ps "PortIoTextPlaceStrategy"
1816stg "STSignalDisplayStrategy"
1817f (Text
1818uid 3343,0
1819va (VaSet
1820)
1821xt "15400,96500,18000,97500"
1822st "A2_D"
1823ju 2
1824blo "18000,97300"
1825tm "WireNameMgr"
1826)
1827)
1828)
1829*50 (PortIoIn
1830uid 3344,0
1831shape (CompositeShape
1832uid 3345,0
1833va (VaSet
1834vasetType 1
1835fg "0,0,32768"
1836)
1837optionalChildren [
1838(Pentagon
1839uid 3346,0
1840sl 0
1841ro 270
1842xt "19000,97625,20500,98375"
1843)
1844(Line
1845uid 3347,0
1846sl 0
1847ro 270
1848xt "20500,98000,21000,98000"
1849pts [
1850"20500,98000"
1851"21000,98000"
1852]
1853)
1854]
1855)
1856stc 0
1857sf 1
1858tg (WTG
1859uid 3348,0
1860ps "PortIoTextPlaceStrategy"
1861stg "STSignalDisplayStrategy"
1862f (Text
1863uid 3349,0
1864va (VaSet
1865)
1866xt "15400,97500,18000,98500"
1867st "A3_D"
1868ju 2
1869blo "18000,98300"
1870tm "WireNameMgr"
1871)
1872)
1873)
1874*51 (Net
1875uid 3374,0
1876decl (Decl
1877n "A0_D"
1878t "std_logic_vector"
1879b "(11 DOWNTO 0)"
1880o 1
1881suid 79,0
1882)
1883declText (MLText
1884uid 3375,0
1885va (VaSet
1886font "Courier New,8,0"
1887)
1888xt "39000,3800,67500,4600"
1889st "A0_D : std_logic_vector(11 DOWNTO 0)"
1890)
1891)
1892*52 (Net
1893uid 3376,0
1894decl (Decl
1895n "A1_D"
1896t "std_logic_vector"
1897b "(11 DOWNTO 0)"
1898o 2
1899suid 80,0
1900)
1901declText (MLText
1902uid 3377,0
1903va (VaSet
1904font "Courier New,8,0"
1905)
1906xt "39000,4600,67500,5400"
1907st "A1_D : std_logic_vector(11 DOWNTO 0)"
1908)
1909)
1910*53 (Net
1911uid 3378,0
1912decl (Decl
1913n "A2_D"
1914t "std_logic_vector"
1915b "(11 DOWNTO 0)"
1916o 3
1917suid 81,0
1918)
1919declText (MLText
1920uid 3379,0
1921va (VaSet
1922font "Courier New,8,0"
1923)
1924xt "39000,5400,67500,6200"
1925st "A2_D : std_logic_vector(11 DOWNTO 0)"
1926)
1927)
1928*54 (Net
1929uid 3380,0
1930decl (Decl
1931n "A3_D"
1932t "std_logic_vector"
1933b "(11 DOWNTO 0)"
1934o 4
1935suid 82,0
1936)
1937declText (MLText
1938uid 3381,0
1939va (VaSet
1940font "Courier New,8,0"
1941)
1942xt "39000,6200,67500,7000"
1943st "A3_D : std_logic_vector(11 DOWNTO 0)"
1944)
1945)
1946*55 (PortIoIn
1947uid 3476,0
1948shape (CompositeShape
1949uid 3477,0
1950va (VaSet
1951vasetType 1
1952fg "0,0,32768"
1953)
1954optionalChildren [
1955(Pentagon
1956uid 3478,0
1957sl 0
1958ro 270
1959xt "19000,104625,20500,105375"
1960)
1961(Line
1962uid 3479,0
1963sl 0
1964ro 270
1965xt "20500,105000,21000,105000"
1966pts [
1967"20500,105000"
1968"21000,105000"
1969]
1970)
1971]
1972)
1973stc 0
1974sf 1
1975tg (WTG
1976uid 3480,0
1977ps "PortIoTextPlaceStrategy"
1978stg "STSignalDisplayStrategy"
1979f (Text
1980uid 3481,0
1981va (VaSet
1982)
1983xt "13200,104500,18000,105500"
1984st "D0_SROUT"
1985ju 2
1986blo "18000,105300"
1987tm "WireNameMgr"
1988)
1989)
1990)
1991*56 (PortIoIn
1992uid 3482,0
1993shape (CompositeShape
1994uid 3483,0
1995va (VaSet
1996vasetType 1
1997fg "0,0,32768"
1998)
1999optionalChildren [
2000(Pentagon
2001uid 3484,0
2002sl 0
2003ro 270
2004xt "19000,105625,20500,106375"
2005)
2006(Line
2007uid 3485,0
2008sl 0
2009ro 270
2010xt "20500,106000,21000,106000"
2011pts [
2012"20500,106000"
2013"21000,106000"
2014]
2015)
2016]
2017)
2018stc 0
2019sf 1
2020tg (WTG
2021uid 3486,0
2022ps "PortIoTextPlaceStrategy"
2023stg "STSignalDisplayStrategy"
2024f (Text
2025uid 3487,0
2026va (VaSet
2027)
2028xt "13300,105500,18000,106500"
2029st "D1_SROUT"
2030ju 2
2031blo "18000,106300"
2032tm "WireNameMgr"
2033)
2034)
2035)
2036*57 (PortIoIn
2037uid 3488,0
2038shape (CompositeShape
2039uid 3489,0
2040va (VaSet
2041vasetType 1
2042fg "0,0,32768"
2043)
2044optionalChildren [
2045(Pentagon
2046uid 3490,0
2047sl 0
2048ro 270
2049xt "19000,106625,20500,107375"
2050)
2051(Line
2052uid 3491,0
2053sl 0
2054ro 270
2055xt "20500,107000,21000,107000"
2056pts [
2057"20500,107000"
2058"21000,107000"
2059]
2060)
2061]
2062)
2063stc 0
2064sf 1
2065tg (WTG
2066uid 3492,0
2067ps "PortIoTextPlaceStrategy"
2068stg "STSignalDisplayStrategy"
2069f (Text
2070uid 3493,0
2071va (VaSet
2072)
2073xt "13200,106500,18000,107500"
2074st "D2_SROUT"
2075ju 2
2076blo "18000,107300"
2077tm "WireNameMgr"
2078)
2079)
2080)
2081*58 (PortIoIn
2082uid 3494,0
2083shape (CompositeShape
2084uid 3495,0
2085va (VaSet
2086vasetType 1
2087fg "0,0,32768"
2088)
2089optionalChildren [
2090(Pentagon
2091uid 3496,0
2092sl 0
2093ro 270
2094xt "19000,107625,20500,108375"
2095)
2096(Line
2097uid 3497,0
2098sl 0
2099ro 270
2100xt "20500,108000,21000,108000"
2101pts [
2102"20500,108000"
2103"21000,108000"
2104]
2105)
2106]
2107)
2108stc 0
2109sf 1
2110tg (WTG
2111uid 3498,0
2112ps "PortIoTextPlaceStrategy"
2113stg "STSignalDisplayStrategy"
2114f (Text
2115uid 3499,0
2116va (VaSet
2117)
2118xt "13200,107500,18000,108500"
2119st "D3_SROUT"
2120ju 2
2121blo "18000,108300"
2122tm "WireNameMgr"
2123)
2124)
2125)
2126*59 (Net
2127uid 3500,0
2128decl (Decl
2129n "D0_SROUT"
2130t "std_logic"
2131o 6
2132suid 91,0
2133)
2134declText (MLText
2135uid 3501,0
2136va (VaSet
2137font "Courier New,8,0"
2138)
2139xt "39000,7800,57000,8600"
2140st "D0_SROUT : std_logic"
2141)
2142)
2143*60 (Net
2144uid 3502,0
2145decl (Decl
2146n "D1_SROUT"
2147t "std_logic"
2148o 7
2149suid 92,0
2150)
2151declText (MLText
2152uid 3503,0
2153va (VaSet
2154font "Courier New,8,0"
2155)
2156xt "39000,8600,57000,9400"
2157st "D1_SROUT : std_logic"
2158)
2159)
2160*61 (Net
2161uid 3504,0
2162decl (Decl
2163n "D2_SROUT"
2164t "std_logic"
2165o 8
2166suid 93,0
2167)
2168declText (MLText
2169uid 3505,0
2170va (VaSet
2171font "Courier New,8,0"
2172)
2173xt "39000,9400,57000,10200"
2174st "D2_SROUT : std_logic"
2175)
2176)
2177*62 (Net
2178uid 3506,0
2179decl (Decl
2180n "D3_SROUT"
2181t "std_logic"
2182o 9
2183suid 94,0
2184)
2185declText (MLText
2186uid 3507,0
2187va (VaSet
2188font "Courier New,8,0"
2189)
2190xt "39000,10200,57000,11000"
2191st "D3_SROUT : std_logic"
2192)
2193)
2194*63 (PortIoOut
2195uid 3508,0
2196shape (CompositeShape
2197uid 3509,0
2198va (VaSet
2199vasetType 1
2200fg "0,0,32768"
2201)
2202optionalChildren [
2203(Pentagon
2204uid 3510,0
2205sl 0
2206ro 90
2207xt "19000,108625,20500,109375"
2208)
2209(Line
2210uid 3511,0
2211sl 0
2212ro 90
2213xt "20500,109000,21000,109000"
2214pts [
2215"21000,109000"
2216"20500,109000"
2217]
2218)
2219]
2220)
2221stc 0
2222sf 1
2223tg (WTG
2224uid 3512,0
2225ps "PortIoTextPlaceStrategy"
2226stg "STSignalDisplayStrategy"
2227f (Text
2228uid 3513,0
2229va (VaSet
2230)
2231xt "15900,108500,18000,109500"
2232st "D_A"
2233ju 2
2234blo "18000,109300"
2235tm "WireNameMgr"
2236)
2237)
2238)
2239*64 (Net
2240uid 3514,0
2241decl (Decl
2242n "D_A"
2243t "std_logic_vector"
2244b "(3 DOWNTO 0)"
2245o 26
2246suid 95,0
2247i "(others => '0')"
2248)
2249declText (MLText
2250uid 3515,0
2251va (VaSet
2252font "Courier New,8,0"
2253)
2254xt "39000,23800,77500,24600"
2255st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')"
2256)
2257)
2258*65 (PortIoOut
2259uid 3516,0
2260shape (CompositeShape
2261uid 3517,0
2262va (VaSet
2263vasetType 1
2264fg "0,0,32768"
2265)
2266optionalChildren [
2267(Pentagon
2268uid 3518,0
2269sl 0
2270ro 90
2271xt "19000,109625,20500,110375"
2272)
2273(Line
2274uid 3519,0
2275sl 0
2276ro 90
2277xt "20500,110000,21000,110000"
2278pts [
2279"21000,110000"
2280"20500,110000"
2281]
2282)
2283]
2284)
2285stc 0
2286sf 1
2287tg (WTG
2288uid 3520,0
2289ps "PortIoTextPlaceStrategy"
2290stg "STSignalDisplayStrategy"
2291f (Text
2292uid 3521,0
2293va (VaSet
2294)
2295xt "14200,109500,18000,110500"
2296st "DWRITE"
2297ju 2
2298blo "18000,110300"
2299tm "WireNameMgr"
2300)
2301)
2302)
2303*66 (Net
2304uid 3522,0
2305decl (Decl
2306n "DWRITE"
2307t "std_logic"
2308o 25
2309suid 96,0
2310i "'0'"
2311)
2312declText (MLText
2313uid 3523,0
2314va (VaSet
2315font "Courier New,8,0"
2316)
2317xt "39000,23000,71500,23800"
2318st "DWRITE : std_logic := '0'"
2319)
2320)
2321*67 (PortIoOut
2322uid 3536,0
2323shape (CompositeShape
2324uid 3537,0
2325va (VaSet
2326vasetType 1
2327fg "0,0,32768"
2328)
2329optionalChildren [
2330(Pentagon
2331uid 3538,0
2332sl 0
2333ro 270
2334xt "97500,83625,99000,84375"
2335)
2336(Line
2337uid 3539,0
2338sl 0
2339ro 270
2340xt "97000,84000,97500,84000"
2341pts [
2342"97000,84000"
2343"97500,84000"
2344]
2345)
2346]
2347)
2348stc 0
2349sf 1
2350tg (WTG
2351uid 3540,0
2352ps "PortIoTextPlaceStrategy"
2353stg "STSignalDisplayStrategy"
2354f (Text
2355uid 3541,0
2356va (VaSet
2357)
2358xt "100000,83500,103700,84500"
2359st "DAC_CS"
2360blo "100000,84300"
2361tm "WireNameMgr"
2362)
2363)
2364)
2365*68 (PortIoOut
2366uid 3624,0
2367shape (CompositeShape
2368uid 3625,0
2369va (VaSet
2370vasetType 1
2371fg "0,0,32768"
2372)
2373optionalChildren [
2374(Pentagon
2375uid 3626,0
2376sl 0
2377ro 270
2378xt "99500,96625,101000,97375"
2379)
2380(Line
2381uid 3627,0
2382sl 0
2383ro 270
2384xt "99000,97000,99500,97000"
2385pts [
2386"99000,97000"
2387"99500,97000"
2388]
2389)
2390]
2391)
2392stc 0
2393sf 1
2394tg (WTG
2395uid 3628,0
2396ps "PortIoTextPlaceStrategy"
2397stg "STSignalDisplayStrategy"
2398f (Text
2399uid 3629,0
2400va (VaSet
2401)
2402xt "101750,96500,104650,97500"
2403st "S_CLK"
2404blo "101750,97300"
2405tm "WireNameMgr"
2406)
2407)
2408)
2409*69 (Net
2410uid 3630,0
2411decl (Decl
2412n "S_CLK"
2413t "std_logic"
2414o 42
2415suid 105,0
2416)
2417declText (MLText
2418uid 3631,0
2419va (VaSet
2420font "Courier New,8,0"
2421)
2422xt "39000,36600,57000,37400"
2423st "S_CLK : std_logic"
2424)
2425)
2426*70 (Net
2427uid 3632,0
2428decl (Decl
2429n "W_A"
2430t "std_logic_vector"
2431b "(9 DOWNTO 0)"
2432o 45
2433suid 106,0
2434)
2435declText (MLText
2436uid 3633,0
2437va (VaSet
2438font "Courier New,8,0"
2439)
2440xt "39000,39000,67000,39800"
2441st "W_A : std_logic_vector(9 DOWNTO 0)"
2442)
2443)
2444*71 (Net
2445uid 3634,0
2446decl (Decl
2447n "W_D"
2448t "std_logic_vector"
2449b "(15 DOWNTO 0)"
2450o 52
2451suid 107,0
2452)
2453declText (MLText
2454uid 3635,0
2455va (VaSet
2456font "Courier New,8,0"
2457)
2458xt "39000,44600,67500,45400"
2459st "W_D : std_logic_vector(15 DOWNTO 0)"
2460)
2461)
2462*72 (Net
2463uid 3636,0
2464decl (Decl
2465n "W_RES"
2466t "std_logic"
2467o 48
2468suid 108,0
2469i "'1'"
2470)
2471declText (MLText
2472uid 3637,0
2473va (VaSet
2474font "Courier New,8,0"
2475)
2476xt "39000,41400,71500,42200"
2477st "W_RES : std_logic := '1'"
2478)
2479)
2480*73 (Net
2481uid 3638,0
2482decl (Decl
2483n "W_RD"
2484t "std_logic"
2485o 47
2486suid 109,0
2487i "'1'"
2488)
2489declText (MLText
2490uid 3639,0
2491va (VaSet
2492font "Courier New,8,0"
2493)
2494xt "39000,40600,71500,41400"
2495st "W_RD : std_logic := '1'"
2496)
2497)
2498*74 (Net
2499uid 3640,0
2500decl (Decl
2501n "W_WR"
2502t "std_logic"
2503o 50
2504suid 110,0
2505i "'1'"
2506)
2507declText (MLText
2508uid 3641,0
2509va (VaSet
2510font "Courier New,8,0"
2511)
2512xt "39000,43000,71500,43800"
2513st "W_WR : std_logic := '1'"
2514)
2515)
2516*75 (Net
2517uid 3642,0
2518decl (Decl
2519n "W_INT"
2520t "std_logic"
2521o 16
2522suid 111,0
2523)
2524declText (MLText
2525uid 3643,0
2526va (VaSet
2527font "Courier New,8,0"
2528)
2529xt "39000,15800,57000,16600"
2530st "W_INT : std_logic"
2531)
2532)
2533*76 (Net
2534uid 3644,0
2535decl (Decl
2536n "W_CS"
2537t "std_logic"
2538o 46
2539suid 112,0
2540i "'1'"
2541)
2542declText (MLText
2543uid 3645,0
2544va (VaSet
2545font "Courier New,8,0"
2546)
2547xt "39000,39800,71500,40600"
2548st "W_CS : std_logic := '1'"
2549)
2550)
2551*77 (PortIoInOut
2552uid 3674,0
2553shape (CompositeShape
2554uid 3675,0
2555va (VaSet
2556vasetType 1
2557fg "0,0,32768"
2558)
2559optionalChildren [
2560(Hexagon
2561uid 3676,0
2562sl 0
2563xt "90500,98625,92000,99375"
2564)
2565(Line
2566uid 3677,0
2567sl 0
2568xt "90000,99000,90500,99000"
2569pts [
2570"90000,99000"
2571"90500,99000"
2572]
2573)
2574]
2575)
2576stc 0
2577sf 1
2578tg (WTG
2579uid 3678,0
2580ps "PortIoTextPlaceStrategy"
2581stg "STSignalDisplayStrategy"
2582f (Text
2583uid 3679,0
2584va (VaSet
2585)
2586xt "93000,98500,95700,99500"
2587st "MISO"
2588blo "93000,99300"
2589tm "WireNameMgr"
2590)
2591)
2592)
2593*78 (Net
2594uid 3680,0
2595decl (Decl
2596n "MOSI"
2597t "std_logic"
2598o 31
2599suid 113,0
2600i "'0'"
2601)
2602declText (MLText
2603uid 3681,0
2604va (VaSet
2605font "Courier New,8,0"
2606)
2607xt "39000,27800,71500,28600"
2608st "MOSI : std_logic := '0'"
2609)
2610)
2611*79 (PortIoOut
2612uid 3688,0
2613shape (CompositeShape
2614uid 3689,0
2615va (VaSet
2616vasetType 1
2617fg "0,0,32768"
2618)
2619optionalChildren [
2620(Pentagon
2621uid 3690,0
2622sl 0
2623ro 270
2624xt "99500,99625,101000,100375"
2625)
2626(Line
2627uid 3691,0
2628sl 0
2629ro 270
2630xt "99000,100000,99500,100000"
2631pts [
2632"99000,100000"
2633"99500,100000"
2634]
2635)
2636]
2637)
2638stc 0
2639sf 1
2640tg (WTG
2641uid 3692,0
2642ps "PortIoTextPlaceStrategy"
2643stg "STSignalDisplayStrategy"
2644f (Text
2645uid 3693,0
2646va (VaSet
2647)
2648xt "102000,99500,104700,100500"
2649st "MOSI"
2650blo "102000,100300"
2651tm "WireNameMgr"
2652)
2653)
2654)
2655*80 (Net
2656uid 3694,0
2657decl (Decl
2658n "MISO"
2659t "std_logic"
2660preAdd 0
2661posAdd 0
2662o 51
2663suid 114,0
2664)
2665declText (MLText
2666uid 3695,0
2667va (VaSet
2668font "Courier New,8,0"
2669)
2670xt "39000,43800,57000,44600"
2671st "MISO : std_logic"
2672)
2673)
2674*81 (PortIoOut
2675uid 3716,0
2676shape (CompositeShape
2677uid 3717,0
2678va (VaSet
2679vasetType 1
2680fg "0,0,32768"
2681)
2682optionalChildren [
2683(Pentagon
2684uid 3718,0
2685sl 0
2686ro 270
2687xt "137500,130625,139000,131375"
2688)
2689(Line
2690uid 3719,0
2691sl 0
2692ro 270
2693xt "137000,131000,137500,131000"
2694pts [
2695"137000,131000"
2696"137500,131000"
2697]
2698)
2699]
2700)
2701stc 0
2702sf 1
2703tg (WTG
2704uid 3720,0
2705ps "PortIoTextPlaceStrategy"
2706stg "STSignalDisplayStrategy"
2707f (Text
2708uid 3721,0
2709va (VaSet
2710)
2711xt "140000,130500,146100,131500"
2712st "RS485_C_DE"
2713blo "140000,131300"
2714tm "WireNameMgr"
2715)
2716)
2717)
2718*82 (PortIoOut
2719uid 3722,0
2720shape (CompositeShape
2721uid 3723,0
2722va (VaSet
2723vasetType 1
2724fg "0,0,32768"
2725)
2726optionalChildren [
2727(Pentagon
2728uid 3724,0
2729sl 0
2730ro 270
2731xt "137500,131625,139000,132375"
2732)
2733(Line
2734uid 3725,0
2735sl 0
2736ro 270
2737xt "137000,132000,137500,132000"
2738pts [
2739"137000,132000"
2740"137500,132000"
2741]
2742)
2743]
2744)
2745stc 0
2746sf 1
2747tg (WTG
2748uid 3726,0
2749ps "PortIoTextPlaceStrategy"
2750stg "STSignalDisplayStrategy"
2751f (Text
2752uid 3727,0
2753va (VaSet
2754)
2755xt "140000,131500,146200,132500"
2756st "RS485_C_DO"
2757blo "140000,132300"
2758tm "WireNameMgr"
2759)
2760)
2761)
2762*83 (PortIoOut
2763uid 3728,0
2764shape (CompositeShape
2765uid 3729,0
2766va (VaSet
2767vasetType 1
2768fg "0,0,32768"
2769)
2770optionalChildren [
2771(Pentagon
2772uid 3730,0
2773sl 0
2774ro 270
2775xt "85500,147625,87000,148375"
2776)
2777(Line
2778uid 3731,0
2779sl 0
2780ro 270
2781xt "85000,148000,85500,148000"
2782pts [
2783"85000,148000"
2784"85500,148000"
2785]
2786)
2787]
2788)
2789stc 0
2790sf 1
2791tg (WTG
2792uid 3732,0
2793ps "PortIoTextPlaceStrategy"
2794stg "STSignalDisplayStrategy"
2795f (Text
2796uid 3733,0
2797va (VaSet
2798)
2799xt "88000,147500,94000,148500"
2800st "RS485_E_RE"
2801blo "88000,148300"
2802tm "WireNameMgr"
2803)
2804)
2805)
2806*84 (PortIoOut
2807uid 3734,0
2808shape (CompositeShape
2809uid 3735,0
2810va (VaSet
2811vasetType 1
2812fg "0,0,32768"
2813)
2814optionalChildren [
2815(Pentagon
2816uid 3736,0
2817sl 0
2818ro 270
2819xt "85500,146625,87000,147375"
2820)
2821(Line
2822uid 3737,0
2823sl 0
2824ro 270
2825xt "85000,147000,85500,147000"
2826pts [
2827"85000,147000"
2828"85500,147000"
2829]
2830)
2831]
2832)
2833stc 0
2834sf 1
2835tg (WTG
2836uid 3738,0
2837ps "PortIoTextPlaceStrategy"
2838stg "STSignalDisplayStrategy"
2839f (Text
2840uid 3739,0
2841va (VaSet
2842)
2843xt "88000,146500,94100,147500"
2844st "RS485_E_DE"
2845blo "88000,147300"
2846tm "WireNameMgr"
2847)
2848)
2849)
2850*85 (PortIoOut
2851uid 3740,0
2852shape (CompositeShape
2853uid 3741,0
2854va (VaSet
2855vasetType 1
2856fg "0,0,32768"
2857)
2858optionalChildren [
2859(Pentagon
2860uid 3742,0
2861sl 0
2862ro 270
2863xt "82500,120625,84000,121375"
2864)
2865(Line
2866uid 3743,0
2867sl 0
2868ro 270
2869xt "82000,121000,82500,121000"
2870pts [
2871"82000,121000"
2872"82500,121000"
2873]
2874)
2875]
2876)
2877stc 0
2878sf 1
2879tg (WTG
2880uid 3744,0
2881ps "PortIoTextPlaceStrategy"
2882stg "STSignalDisplayStrategy"
2883f (Text
2884uid 3745,0
2885va (VaSet
2886)
2887xt "85000,120500,89100,121500"
2888st "DENABLE"
2889blo "85000,121300"
2890tm "WireNameMgr"
2891)
2892)
2893)
2894*86 (PortIoOut
2895uid 3752,0
2896shape (CompositeShape
2897uid 3753,0
2898va (VaSet
2899vasetType 1
2900fg "0,0,32768"
2901)
2902optionalChildren [
2903(Pentagon
2904uid 3754,0
2905sl 0
2906ro 270
2907xt "137500,138625,139000,139375"
2908)
2909(Line
2910uid 3755,0
2911sl 0
2912ro 270
2913xt "137000,139000,137500,139000"
2914pts [
2915"137000,139000"
2916"137500,139000"
2917]
2918)
2919]
2920)
2921stc 0
2922sf 1
2923tg (WTG
2924uid 3756,0
2925ps "PortIoTextPlaceStrategy"
2926stg "STSignalDisplayStrategy"
2927f (Text
2928uid 3757,0
2929va (VaSet
2930)
2931xt "140000,138500,143000,139500"
2932st "EE_CS"
2933blo "140000,139300"
2934tm "WireNameMgr"
2935)
2936)
2937)
2938*87 (Net
2939uid 3866,0
2940decl (Decl
2941n "RS485_C_RE"
2942t "std_logic"
2943o 36
2944suid 127,0
2945)
2946declText (MLText
2947uid 3867,0
2948va (VaSet
2949font "Courier New,8,0"
2950)
2951xt "39000,31800,57000,32600"
2952st "RS485_C_RE : std_logic"
2953)
2954)
2955*88 (Net
2956uid 3868,0
2957decl (Decl
2958n "RS485_C_DE"
2959t "std_logic"
2960o 34
2961suid 128,0
2962)
2963declText (MLText
2964uid 3869,0
2965va (VaSet
2966font "Courier New,8,0"
2967)
2968xt "39000,30200,57000,31000"
2969st "RS485_C_DE : std_logic"
2970)
2971)
2972*89 (Net
2973uid 3870,0
2974decl (Decl
2975n "RS485_E_RE"
2976t "std_logic"
2977o 39
2978suid 129,0
2979)
2980declText (MLText
2981uid 3871,0
2982va (VaSet
2983font "Courier New,8,0"
2984)
2985xt "39000,34200,57000,35000"
2986st "RS485_E_RE : std_logic"
2987)
2988)
2989*90 (Net
2990uid 3872,0
2991decl (Decl
2992n "RS485_E_DE"
2993t "std_logic"
2994o 37
2995suid 130,0
2996)
2997declText (MLText
2998uid 3873,0
2999va (VaSet
3000font "Courier New,8,0"
3001)
3002xt "39000,32600,57000,33400"
3003st "RS485_E_DE : std_logic"
3004)
3005)
3006*91 (Net
3007uid 3874,0
3008decl (Decl
3009n "DENABLE"
3010t "std_logic"
3011o 23
3012suid 131,0
3013i "'0'"
3014)
3015declText (MLText
3016uid 3875,0
3017va (VaSet
3018font "Courier New,8,0"
3019)
3020xt "39000,21400,71500,22200"
3021st "DENABLE : std_logic := '0'"
3022)
3023)
3024*92 (Net
3025uid 3878,0
3026decl (Decl
3027n "EE_CS"
3028t "std_logic"
3029o 29
3030suid 133,0
3031)
3032declText (MLText
3033uid 3879,0
3034va (VaSet
3035font "Courier New,8,0"
3036)
3037xt "39000,26200,57000,27000"
3038st "EE_CS : std_logic"
3039)
3040)
3041*93 (PortIoOut
3042uid 4916,0
3043shape (CompositeShape
3044uid 4917,0
3045va (VaSet
3046vasetType 1
3047fg "0,0,32768"
3048)
3049optionalChildren [
3050(Pentagon
3051uid 4918,0
3052sl 0
3053ro 270
3054xt "137500,117625,139000,118375"
3055)
3056(Line
3057uid 4919,0
3058sl 0
3059ro 270
3060xt "137000,118000,137500,118000"
3061pts [
3062"137000,118000"
3063"137500,118000"
3064]
3065)
3066]
3067)
3068stc 0
3069sf 1
3070tg (WTG
3071uid 4920,0
3072ps "PortIoTextPlaceStrategy"
3073stg "STSignalDisplayStrategy"
3074f (Text
3075uid 4921,0
3076va (VaSet
3077)
3078xt "140000,117500,142000,118500"
3079st "D_T"
3080blo "140000,118300"
3081tm "WireNameMgr"
3082)
3083)
3084)
3085*94 (Net
3086uid 5320,0
3087decl (Decl
3088n "D_T"
3089t "std_logic_vector"
3090b "(7 DOWNTO 0)"
3091o 27
3092suid 141,0
3093i "(OTHERS => '0')"
3094)
3095declText (MLText
3096uid 5321,0
3097va (VaSet
3098font "Courier New,8,0"
3099)
3100xt "39000,24600,77500,25400"
3101st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
3102)
3103)
3104*95 (PortIoOut
3105uid 6874,0
3106shape (CompositeShape
3107uid 6875,0
3108va (VaSet
3109vasetType 1
3110fg "0,0,32768"
3111)
3112optionalChildren [
3113(Pentagon
3114uid 6876,0
3115sl 0
3116ro 270
3117xt "137500,127625,139000,128375"
3118)
3119(Line
3120uid 6877,0
3121sl 0
3122ro 270
3123xt "137000,128000,137500,128000"
3124pts [
3125"137000,128000"
3126"137500,128000"
3127]
3128)
3129]
3130)
3131stc 0
3132sf 1
3133tg (WTG
3134uid 6878,0
3135ps "PortIoTextPlaceStrategy"
3136stg "STSignalDisplayStrategy"
3137f (Text
3138uid 6879,0
3139va (VaSet
3140)
3141xt "140000,127500,142500,128500"
3142st "D_T2"
3143blo "140000,128300"
3144tm "WireNameMgr"
3145)
3146)
3147)
3148*96 (Net
3149uid 6886,0
3150decl (Decl
3151n "D_T2"
3152t "std_logic_vector"
3153b "(1 DOWNTO 0)"
3154o 28
3155suid 154,0
3156i "(others => '0')"
3157)
3158declText (MLText
3159uid 6887,0
3160va (VaSet
3161font "Courier New,8,0"
3162)
3163xt "39000,25400,77500,26200"
3164st "D_T2 : std_logic_vector(1 DOWNTO 0) := (others => '0')"
3165)
3166)
3167*97 (PortIoOut
3168uid 7138,0
3169shape (CompositeShape
3170uid 7139,0
3171va (VaSet
3172vasetType 1
3173fg "0,0,32768"
3174)
3175optionalChildren [
3176(Pentagon
3177uid 7140,0
3178sl 0
3179ro 270
3180xt "137500,120625,139000,121375"
3181)
3182(Line
3183uid 7141,0
3184sl 0
3185ro 270
3186xt "137000,121000,137500,121000"
3187pts [
3188"137000,121000"
3189"137500,121000"
3190]
3191)
3192]
3193)
3194stc 0
3195sf 1
3196tg (WTG
3197uid 7142,0
3198ps "PortIoTextPlaceStrategy"
3199stg "STSignalDisplayStrategy"
3200f (Text
3201uid 7143,0
3202va (VaSet
3203)
3204xt "140000,120500,142400,121500"
3205st "A1_T"
3206blo "140000,121300"
3207tm "WireNameMgr"
3208)
3209)
3210)
3211*98 (Net
3212uid 7150,0
3213decl (Decl
3214n "A1_T"
3215t "std_logic_vector"
3216b "(7 DOWNTO 0)"
3217o 19
3218suid 155,0
3219i "(OTHERS => '0')"
3220)
3221declText (MLText
3222uid 7151,0
3223va (VaSet
3224font "Courier New,8,0"
3225)
3226xt "39000,18200,77500,19000"
3227st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
3228)
3229)
3230*99 (Net
3231uid 9500,0
3232decl (Decl
3233n "CLK_50"
3234t "std_logic"
3235o 54
3236suid 163,0
3237)
3238declText (MLText
3239uid 9501,0
3240va (VaSet
3241font "Courier New,8,0"
3242)
3243xt "39000,47200,61000,48000"
3244st "SIGNAL CLK_50 : std_logic"
3245)
3246)
3247*100 (PortIoOut
3248uid 10296,0
3249shape (CompositeShape
3250uid 10297,0
3251va (VaSet
3252vasetType 1
3253fg "0,0,32768"
3254)
3255optionalChildren [
3256(Pentagon
3257uid 10298,0
3258sl 0
3259ro 270
3260xt "137500,119625,139000,120375"
3261)
3262(Line
3263uid 10299,0
3264sl 0
3265ro 270
3266xt "137000,120000,137500,120000"
3267pts [
3268"137000,120000"
3269"137500,120000"
3270]
3271)
3272]
3273)
3274stc 0
3275sf 1
3276tg (WTG
3277uid 10300,0
3278ps "PortIoTextPlaceStrategy"
3279stg "STSignalDisplayStrategy"
3280f (Text
3281uid 10301,0
3282va (VaSet
3283)
3284xt "140000,119500,142500,120500"
3285st "A0_T"
3286blo "140000,120300"
3287tm "WireNameMgr"
3288)
3289)
3290)
3291*101 (Net
3292uid 10308,0
3293decl (Decl
3294n "A0_T"
3295t "std_logic_vector"
3296b "(7 DOWNTO 0)"
3297o 18
3298suid 166,0
3299i "(others => '0')"
3300)
3301declText (MLText
3302uid 10309,0
3303va (VaSet
3304font "Courier New,8,0"
3305)
3306xt "39000,17400,77500,18200"
3307st "A0_T : std_logic_vector(7 DOWNTO 0) := (others => '0')"
3308)
3309)
3310*102 (HdlText
3311uid 10310,0
3312optionalChildren [
3313*103 (EmbeddedText
3314uid 10316,0
3315commentText (CommentText
3316uid 10317,0
3317ps "CenterOffsetStrategy"
3318shape (Rectangle
3319uid 10318,0
3320va (VaSet
3321vasetType 1
3322fg "65535,65535,65535"
3323lineColor "0,0,32768"
3324lineWidth 2
3325)
3326xt "109000,64000,141000,106000"
3327)
3328oxt "0,0,18000,5000"
3329text (MLText
3330uid 10319,0
3331va (VaSet
3332)
3333xt "109200,64200,128500,106200"
3334st "
3335-- testpins D_T2 are used as MAX3485 outputs.
3336
3337--D_T <= (others => '0');
3338D_T <= w5300_state;
3339--D_T2(0) <= debug_data_valid;
3340D_T2(0) <= debug_data_ram_empty;
3341--D_T2(1) <= socket_tx_free_out(16);
3342
3343D_T2(1) <= TRG_V;
3344--D_T2 <= ( others => '0' );
3345
3346
3347A0_T <= (others => '0');
3348A1_T <= (others => '1');
3349
3350
3351--A0_T <= DG_state;
3352W_T(3 downto 0) <= mem_manager_state;
3353--A1_T(7 downto 4) <= \"1100\";
3354
3355--A0_T <= socket_tx_free_out(7 downto 0);
3356--A0_T <= spi_debug_16bit(7 downto 0);
3357--A1_T <= spi_debug_16bit(15 downto 8);
3358--A1_T <= socket_tx_free_out(15 downto 8);
3359
3360-- check SPI interfac
3361--A1_T(7) <= sclk;
3362--A1_T(6) <= MISO;
3363--A1_T(5) <= mosi1;
3364
3365--A1_T(4) <= dac_cs1;
3366--A1_T( 3 downto 0) <= sensor_cs;
3367
3368
3369--D_T(3 downto 0) <= counter_result ( 11 downto 8);
3370--D_T(4) <= alarm_refclk_too_low;
3371--D_T(5) <= alarm_refclk_too_high;
3372--D_T(6) <= '0';
3373--D_T(7) <= '0';
3374
3375
3376
3377-- additional MAX3485 is switched to shutdown mode
3378RS485_C_RE <= '1'; --inverted logic
3379RS485_C_DE <= '0';
3380RS485_C_DO <= '0';
3381-- MAX3485 receiver out pit is fed out... should be HIGH-Z
3382
3383
3384-- EEPROM is not used on FAD. CS is always high.
3385EE_CS <= '1';
3386"
3387tm "HdlTextMgr"
3388wrapOption 3
3389visibleHeight 42000
3390visibleWidth 32000
3391)
3392)
3393)
3394]
3395shape (Rectangle
3396uid 10311,0
3397va (VaSet
3398vasetType 1
3399fg "65535,65535,37120"
3400lineColor "0,0,32768"
3401lineWidth 2
3402)
3403xt "126000,107000,132000,143000"
3404)
3405oxt "0,0,8000,10000"
3406ttg (MlTextGroup
3407uid 10312,0
3408ps "CenterOffsetStrategy"
3409stg "VerticalLayoutStrategy"
3410textVec [
3411*104 (Text
3412uid 10313,0
3413va (VaSet
3414font "Arial,8,1"
3415)
3416xt "129150,110000,130850,111000"
3417st "eb3"
3418blo "129150,110800"
3419tm "HdlTextNameMgr"
3420)
3421*105 (Text
3422uid 10314,0
3423va (VaSet
3424font "Arial,8,1"
3425)
3426xt "129150,111000,129950,112000"
3427st "9"
3428blo "129150,111800"
3429tm "HdlTextNumberMgr"
3430)
3431]
3432)
3433viewicon (ZoomableIcon
3434uid 10315,0
3435sl 0
3436va (VaSet
3437vasetType 1
3438fg "49152,49152,49152"
3439)
3440xt "126250,141250,127750,142750"
3441iconName "TextFile.png"
3442iconMaskName "TextFile.msk"
3443ftype 21
3444)
3445viewiconposition 0
3446)
3447*106 (PortIoOut
3448uid 11104,0
3449shape (CompositeShape
3450uid 11105,0
3451va (VaSet
3452vasetType 1
3453fg "0,0,32768"
3454)
3455optionalChildren [
3456(Pentagon
3457uid 11106,0
3458sl 0
3459ro 270
3460xt "137500,132625,139000,133375"
3461)
3462(Line
3463uid 11107,0
3464sl 0
3465ro 270
3466xt "137000,133000,137500,133000"
3467pts [
3468"137000,133000"
3469"137500,133000"
3470]
3471)
3472]
3473)
3474stc 0
3475sf 1
3476tg (WTG
3477uid 11108,0
3478ps "PortIoTextPlaceStrategy"
3479stg "STSignalDisplayStrategy"
3480f (Text
3481uid 11109,0
3482va (VaSet
3483)
3484xt "140000,132500,146000,133500"
3485st "RS485_C_RE"
3486blo "140000,133300"
3487tm "WireNameMgr"
3488)
3489)
3490)
3491*107 (Net
3492uid 11116,0
3493decl (Decl
3494n "RS485_C_DO"
3495t "std_logic"
3496o 35
3497suid 198,0
3498)
3499declText (MLText
3500uid 11117,0
3501va (VaSet
3502font "Courier New,8,0"
3503)
3504xt "39000,31000,57000,31800"
3505st "RS485_C_DO : std_logic"
3506)
3507)
3508*108 (PortIoIn
3509uid 11508,0
3510shape (CompositeShape
3511uid 11509,0
3512va (VaSet
3513vasetType 1
3514fg "0,0,32768"
3515)
3516optionalChildren [
3517(Pentagon
3518uid 11510,0
3519sl 0
3520ro 90
3521xt "85500,149625,87000,150375"
3522)
3523(Line
3524uid 11511,0
3525sl 0
3526ro 90
3527xt "85000,150000,85500,150000"
3528pts [
3529"85500,150000"
3530"85000,150000"
3531]
3532)
3533]
3534)
3535stc 0
3536sf 1
3537tg (WTG
3538uid 11512,0
3539ps "PortIoTextPlaceStrategy"
3540stg "STSignalDisplayStrategy"
3541f (Text
3542uid 11513,0
3543va (VaSet
3544)
3545xt "88000,149500,94000,150500"
3546st "RS485_E_DI"
3547blo "88000,150300"
3548tm "WireNameMgr"
3549)
3550)
3551)
3552*109 (Net
3553uid 11520,0
3554decl (Decl
3555n "RS485_E_DI"
3556t "std_logic"
3557o 14
3558suid 200,0
3559)
3560declText (MLText
3561uid 11521,0
3562va (VaSet
3563font "Courier New,8,0"
3564)
3565xt "39000,14200,57000,15000"
3566st "RS485_E_DI : std_logic"
3567)
3568)
3569*110 (Net
3570uid 11534,0
3571decl (Decl
3572n "RS485_E_DO"
3573t "std_logic"
3574o 38
3575suid 201,0
3576)
3577declText (MLText
3578uid 11535,0
3579va (VaSet
3580font "Courier New,8,0"
3581)
3582xt "39000,33400,57000,34200"
3583st "RS485_E_DO : std_logic"
3584)
3585)
3586*111 (PortIoOut
3587uid 12326,0
3588shape (CompositeShape
3589uid 12327,0
3590va (VaSet
3591vasetType 1
3592fg "0,0,32768"
3593)
3594optionalChildren [
3595(Pentagon
3596uid 12328,0
3597sl 0
3598ro 270
3599xt "87500,139625,89000,140375"
3600)
3601(Line
3602uid 12329,0
3603sl 0
3604ro 270
3605xt "87000,140000,87500,140000"
3606pts [
3607"87000,140000"
3608"87500,140000"
3609]
3610)
3611]
3612)
3613stc 0
3614sf 1
3615tg (WTG
3616uid 12330,0
3617ps "PortIoTextPlaceStrategy"
3618stg "STSignalDisplayStrategy"
3619f (Text
3620uid 12331,0
3621va (VaSet
3622)
3623xt "89000,139500,91500,140500"
3624st "SRIN"
3625blo "89000,140300"
3626tm "WireNameMgr"
3627)
3628)
3629)
3630*112 (Net
3631uid 12334,0
3632decl (Decl
3633n "SRIN"
3634t "std_logic"
3635o 41
3636suid 203,0
3637i "'0'"
3638)
3639declText (MLText
3640uid 12335,0
3641va (VaSet
3642font "Courier New,8,0"
3643)
3644xt "39000,35800,71500,36600"
3645st "SRIN : std_logic := '0'"
3646)
3647)
3648*113 (PortIoOut
3649uid 12539,0
3650shape (CompositeShape
3651uid 12540,0
3652va (VaSet
3653vasetType 1
3654fg "0,0,32768"
3655)
3656optionalChildren [
3657(Pentagon
3658uid 12541,0
3659sl 0
3660ro 270
3661xt "87500,134625,89000,135375"
3662)
3663(Line
3664uid 12542,0
3665sl 0
3666ro 270
3667xt "87000,135000,87500,135000"
3668pts [
3669"87000,135000"
3670"87500,135000"
3671]
3672)
3673]
3674)
3675stc 0
3676sf 1
3677tg (WTG
3678uid 12543,0
3679ps "PortIoTextPlaceStrategy"
3680stg "STSignalDisplayStrategy"
3681f (Text
3682uid 12544,0
3683va (VaSet
3684)
3685xt "90000,134500,95200,135500"
3686st "AMBER_LED"
3687blo "90000,135300"
3688tm "WireNameMgr"
3689)
3690)
3691)
3692*114 (PortIoOut
3693uid 12553,0
3694shape (CompositeShape
3695uid 12554,0
3696va (VaSet
3697vasetType 1
3698fg "0,0,32768"
3699)
3700optionalChildren [
3701(Pentagon
3702uid 12555,0
3703sl 0
3704ro 270
3705xt "87500,133625,89000,134375"
3706)
3707(Line
3708uid 12556,0
3709sl 0
3710ro 270
3711xt "87000,134000,87500,134000"
3712pts [
3713"87000,134000"
3714"87500,134000"
3715]
3716)
3717]
3718)
3719stc 0
3720sf 1
3721tg (WTG
3722uid 12557,0
3723ps "PortIoTextPlaceStrategy"
3724stg "STSignalDisplayStrategy"
3725f (Text
3726uid 12558,0
3727va (VaSet
3728)
3729xt "90000,133500,95000,134500"
3730st "GREEN_LED"
3731blo "90000,134300"
3732tm "WireNameMgr"
3733)
3734)
3735)
3736*115 (PortIoOut
3737uid 12567,0
3738shape (CompositeShape
3739uid 12568,0
3740va (VaSet
3741vasetType 1
3742fg "0,0,32768"
3743)
3744optionalChildren [
3745(Pentagon
3746uid 12569,0
3747sl 0
3748ro 270
3749xt "87500,135625,89000,136375"
3750)
3751(Line
3752uid 12570,0
3753sl 0
3754ro 270
3755xt "87000,136000,87500,136000"
3756pts [
3757"87000,136000"
3758"87500,136000"
3759]
3760)
3761]
3762)
3763stc 0
3764sf 1
3765tg (WTG
3766uid 12571,0
3767ps "PortIoTextPlaceStrategy"
3768stg "STSignalDisplayStrategy"
3769f (Text
3770uid 12572,0
3771va (VaSet
3772)
3773xt "90000,135500,94000,136500"
3774st "RED_LED"
3775blo "90000,136300"
3776tm "WireNameMgr"
3777)
3778)
3779)
3780*116 (Net
3781uid 12762,0
3782decl (Decl
3783n "AMBER_LED"
3784t "std_logic"
3785o 20
3786suid 207,0
3787)
3788declText (MLText
3789uid 12763,0
3790va (VaSet
3791font "Courier New,8,0"
3792)
3793xt "39000,19000,57000,19800"
3794st "AMBER_LED : std_logic"
3795)
3796)
3797*117 (Net
3798uid 12764,0
3799decl (Decl
3800n "GREEN_LED"
3801t "std_logic"
3802o 30
3803suid 208,0
3804)
3805declText (MLText
3806uid 12765,0
3807va (VaSet
3808font "Courier New,8,0"
3809)
3810xt "39000,27000,57000,27800"
3811st "GREEN_LED : std_logic"
3812)
3813)
3814*118 (Net
3815uid 12766,0
3816decl (Decl
3817n "RED_LED"
3818t "std_logic"
3819o 33
3820suid 209,0
3821)
3822declText (MLText
3823uid 12767,0
3824va (VaSet
3825font "Courier New,8,0"
3826)
3827xt "39000,29400,57000,30200"
3828st "RED_LED : std_logic"
3829)
3830)
3831*119 (PortIoIn
3832uid 13516,0
3833shape (CompositeShape
3834uid 13517,0
3835va (VaSet
3836vasetType 1
3837fg "0,0,32768"
3838)
3839optionalChildren [
3840(Pentagon
3841uid 13518,0
3842sl 0
3843ro 270
3844xt "20000,80625,21500,81375"
3845)
3846(Line
3847uid 13519,0
3848sl 0
3849ro 270
3850xt "21500,81000,22000,81000"
3851pts [
3852"21500,81000"
3853"22000,81000"
3854]
3855)
3856]
3857)
3858stc 0
3859sf 1
3860tg (WTG
3861uid 13520,0
3862ps "PortIoTextPlaceStrategy"
3863stg "STSignalDisplayStrategy"
3864f (Text
3865uid 13521,0
3866va (VaSet
3867)
3868xt "16700,80500,19000,81500"
3869st "LINE"
3870ju 2
3871blo "19000,81300"
3872tm "WireNameMgr"
3873)
3874)
3875)
3876*120 (Net
3877uid 13528,0
3878decl (Decl
3879n "LINE"
3880t "std_logic_vector"
3881b "( 5 DOWNTO 0 )"
3882o 12
3883suid 210,0
3884)
3885declText (MLText
3886uid 13529,0
3887va (VaSet
3888font "Courier New,8,0"
3889)
3890xt "39000,12600,68000,13400"
3891st "LINE : std_logic_vector( 5 DOWNTO 0 )"
3892)
3893)
3894*121 (PortIoIn
3895uid 13628,0
3896shape (CompositeShape
3897uid 13629,0
3898va (VaSet
3899vasetType 1
3900fg "0,0,32768"
3901)
3902optionalChildren [
3903(Pentagon
3904uid 13630,0
3905sl 0
3906ro 270
3907xt "47000,132625,48500,133375"
3908)
3909(Line
3910uid 13631,0
3911sl 0
3912ro 270
3913xt "48500,133000,49000,133000"
3914pts [
3915"48500,133000"
3916"49000,133000"
3917]
3918)
3919]
3920)
3921stc 0
3922sf 1
3923tg (WTG
3924uid 13632,0
3925ps "PortIoTextPlaceStrategy"
3926stg "STSignalDisplayStrategy"
3927f (Text
3928uid 13633,0
3929va (VaSet
3930)
3931xt "42700,132500,46000,133500"
3932st "REFCLK"
3933ju 2
3934blo "46000,133300"
3935tm "WireNameMgr"
3936)
3937)
3938)
3939*122 (Net
3940uid 13640,0
3941decl (Decl
3942n "REFCLK"
3943t "std_logic"
3944o 13
3945suid 211,0
3946)
3947declText (MLText
3948uid 13641,0
3949va (VaSet
3950font "Courier New,8,0"
3951)
3952xt "39000,13400,57000,14200"
3953st "REFCLK : std_logic"
3954)
3955)
3956*123 (PortIoIn
3957uid 14322,0
3958shape (CompositeShape
3959uid 14323,0
3960va (VaSet
3961vasetType 1
3962fg "0,0,32768"
3963)
3964optionalChildren [
3965(Pentagon
3966uid 14324,0
3967sl 0
3968ro 270
3969xt "47000,131625,48500,132375"
3970)
3971(Line
3972uid 14325,0
3973sl 0
3974ro 270
3975xt "48500,132000,49000,132000"
3976pts [
3977"48500,132000"
3978"49000,132000"
3979]
3980)
3981]
3982)
3983stc 0
3984sf 1
3985tg (WTG
3986uid 14326,0
3987ps "PortIoTextPlaceStrategy"
3988stg "STSignalDisplayStrategy"
3989f (Text
3990uid 14327,0
3991va (VaSet
3992)
3993xt "42900,131500,46000,132500"
3994st "D_T_in"
3995ju 2
3996blo "46000,132300"
3997tm "WireNameMgr"
3998)
3999)
4000)
4001*124 (Net
4002uid 14334,0
4003decl (Decl
4004n "D_T_in"
4005t "std_logic_vector"
4006b "(1 DOWNTO 0)"
4007o 11
4008suid 213,0
4009)
4010declText (MLText
4011uid 14335,0
4012va (VaSet
4013font "Courier New,8,0"
4014)
4015xt "39000,11800,67000,12600"
4016st "D_T_in : std_logic_vector(1 DOWNTO 0)"
4017)
4018)
4019*125 (Net
4020uid 15173,0
4021decl (Decl
4022n "led"
4023t "std_logic_vector"
4024b "(7 DOWNTO 0)"
4025posAdd 0
4026o 65
4027suid 215,0
4028i "(OTHERS => '0')"
4029)
4030declText (MLText
4031uid 15174,0
4032va (VaSet
4033font "Courier New,8,0"
4034)
4035xt "39000,57600,81000,58400"
4036st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
4037)
4038)
4039*126 (PortIoOut
4040uid 15557,0
4041shape (CompositeShape
4042uid 15558,0
4043va (VaSet
4044vasetType 1
4045fg "0,0,32768"
4046)
4047optionalChildren [
4048(Pentagon
4049uid 15559,0
4050sl 0
4051ro 270
4052xt "85500,148625,87000,149375"
4053)
4054(Line
4055uid 15560,0
4056sl 0
4057ro 270
4058xt "85000,149000,85500,149000"
4059pts [
4060"85000,149000"
4061"85500,149000"
4062]
4063)
4064]
4065)
4066stc 0
4067sf 1
4068tg (WTG
4069uid 15561,0
4070ps "PortIoTextPlaceStrategy"
4071stg "STSignalDisplayStrategy"
4072f (Text
4073uid 15562,0
4074va (VaSet
4075)
4076xt "88000,148500,94200,149500"
4077st "RS485_E_DO"
4078blo "88000,149300"
4079tm "WireNameMgr"
4080)
4081)
4082)
4083*127 (PortIoIn
4084uid 15706,0
4085shape (CompositeShape
4086uid 15707,0
4087va (VaSet
4088vasetType 1
4089fg "0,0,32768"
4090)
4091optionalChildren [
4092(Pentagon
4093uid 15708,0
4094sl 0
4095ro 270
4096xt "47000,136625,48500,137375"
4097)
4098(Line
4099uid 15709,0
4100sl 0
4101ro 270
4102xt "48500,137000,49000,137000"
4103pts [
4104"48500,137000"
4105"49000,137000"
4106]
4107)
4108]
4109)
4110stc 0
4111sf 1
4112tg (WTG
4113uid 15710,0
4114ps "PortIoTextPlaceStrategy"
4115stg "STSignalDisplayStrategy"
4116f (Text
4117uid 15711,0
4118va (VaSet
4119)
4120xt "41900,136500,46000,137500"
4121st "D_PLLLCK"
4122ju 2
4123blo "46000,137300"
4124tm "WireNameMgr"
4125)
4126)
4127)
4128*128 (Net
4129uid 15718,0
4130decl (Decl
4131n "D_PLLLCK"
4132t "std_logic_vector"
4133b "(3 DOWNTO 0)"
4134o 10
4135suid 216,0
4136)
4137declText (MLText
4138uid 15719,0
4139va (VaSet
4140font "Courier New,8,0"
4141)
4142xt "39000,11000,67000,11800"
4143st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)"
4144)
4145)
4146*129 (PortIoOut
4147uid 15845,0
4148shape (CompositeShape
4149uid 15846,0
4150va (VaSet
4151vasetType 1
4152fg "0,0,32768"
4153)
4154optionalChildren [
4155(Pentagon
4156uid 15847,0
4157sl 0
4158ro 270
4159xt "95500,87625,97000,88375"
4160)
4161(Line
4162uid 15848,0
4163sl 0
4164ro 270
4165xt "95000,88000,95500,88000"
4166pts [
4167"95000,88000"
4168"95500,88000"
4169]
4170)
4171]
4172)
4173stc 0
4174sf 1
4175tg (WTG
4176uid 15849,0
4177ps "PortIoTextPlaceStrategy"
4178stg "STSignalDisplayStrategy"
4179f (Text
4180uid 15850,0
4181va (VaSet
4182)
4183xt "98000,87500,100000,88500"
4184st "TCS"
4185blo "98000,88300"
4186tm "WireNameMgr"
4187)
4188)
4189)
4190*130 (Net
4191uid 15857,0
4192decl (Decl
4193n "TCS"
4194t "std_logic_vector"
4195b "(3 DOWNTO 0)"
4196o 43
4197suid 217,0
4198)
4199declText (MLText
4200uid 15858,0
4201va (VaSet
4202font "Courier New,8,0"
4203)
4204xt "39000,37400,67000,38200"
4205st "TCS : std_logic_vector(3 DOWNTO 0)"
4206)
4207)
4208*131 (PortIoOut
4209uid 16057,0
4210shape (CompositeShape
4211uid 16058,0
4212va (VaSet
4213vasetType 1
4214fg "0,0,32768"
4215)
4216optionalChildren [
4217(Pentagon
4218uid 16059,0
4219sl 0
4220ro 90
4221xt "19000,112625,20500,113375"
4222)
4223(Line
4224uid 16060,0
4225sl 0
4226ro 90
4227xt "20500,113000,21000,113000"
4228pts [
4229"21000,113000"
4230"20500,113000"
4231]
4232)
4233]
4234)
4235stc 0
4236sf 1
4237tg (WTG
4238uid 16061,0
4239ps "PortIoTextPlaceStrategy"
4240stg "STSignalDisplayStrategy"
4241f (Text
4242uid 16062,0
4243va (VaSet
4244)
4245xt "14500,112500,18000,113500"
4246st "DSRCLK"
4247ju 2
4248blo "18000,113300"
4249tm "WireNameMgr"
4250)
4251)
4252)
4253*132 (Net
4254uid 16069,0
4255decl (Decl
4256n "DSRCLK"
4257t "std_logic_vector"
4258b "(3 DOWNTO 0)"
4259o 24
4260suid 222,0
4261i "(others => '0')"
4262)
4263declText (MLText
4264uid 16070,0
4265va (VaSet
4266font "Courier New,8,0"
4267)
4268xt "39000,22200,77500,23000"
4269st "DSRCLK : std_logic_vector(3 DOWNTO 0) := (others => '0')"
4270)
4271)
4272*133 (Net
4273uid 16245,0
4274decl (Decl
4275n "SRCLK"
4276t "std_logic"
4277o 56
4278suid 225,0
4279i "'0'"
4280)
4281declText (MLText
4282uid 16246,0
4283va (VaSet
4284font "Courier New,8,0"
4285)
4286xt "39000,49600,75000,50400"
4287st "SIGNAL SRCLK : std_logic := '0'"
4288)
4289)
4290*134 (HdlText
4291uid 16336,0
4292optionalChildren [
4293*135 (EmbeddedText
4294uid 16342,0
4295commentText (CommentText
4296uid 16343,0
4297ps "CenterOffsetStrategy"
4298shape (Rectangle
4299uid 16344,0
4300va (VaSet
4301vasetType 1
4302fg "65535,65535,65535"
4303lineColor "0,0,32768"
4304lineWidth 2
4305)
4306xt "23000,116000,42000,118000"
4307)
4308oxt "0,0,18000,5000"
4309text (MLText
4310uid 16345,0
4311va (VaSet
4312)
4313xt "23200,116200,41200,117200"
4314st "
4315DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK);
4316"
4317tm "HdlTextMgr"
4318wrapOption 3
4319visibleHeight 2000
4320visibleWidth 19000
4321)
4322)
4323)
4324]
4325shape (Rectangle
4326uid 16337,0
4327va (VaSet
4328vasetType 1
4329fg "65535,65535,37120"
4330lineColor "0,0,32768"
4331lineWidth 2
4332)
4333xt "30000,112000,34000,116000"
4334)
4335oxt "0,0,8000,10000"
4336ttg (MlTextGroup
4337uid 16338,0
4338ps "CenterOffsetStrategy"
4339stg "VerticalLayoutStrategy"
4340textVec [
4341*136 (Text
4342uid 16339,0
4343va (VaSet
4344font "Arial,8,1"
4345)
4346xt "30150,112000,33350,113000"
4347st "SRCLK"
4348blo "30150,112800"
4349tm "HdlTextNameMgr"
4350)
4351*137 (Text
4352uid 16340,0
4353va (VaSet
4354font "Arial,8,1"
4355)
4356xt "30150,113000,30950,114000"
4357st "1"
4358blo "30150,113800"
4359tm "HdlTextNumberMgr"
4360)
4361]
4362)
4363viewicon (ZoomableIcon
4364uid 16341,0
4365sl 0
4366va (VaSet
4367vasetType 1
4368fg "49152,49152,49152"
4369)
4370xt "30250,114250,31750,115750"
4371iconName "TextFile.png"
4372iconMaskName "TextFile.msk"
4373ftype 21
4374)
4375viewiconposition 0
4376)
4377*138 (Net
4378uid 16536,0
4379decl (Decl
4380n "alarm_refclk_too_high"
4381t "std_logic"
4382o 58
4383suid 226,0
4384i "'0'"
4385)
4386declText (MLText
4387uid 16537,0
4388va (VaSet
4389font "Courier New,8,0"
4390)
4391xt "39000,51200,75000,52000"
4392st "SIGNAL alarm_refclk_too_high : std_logic := '0'"
4393)
4394)
4395*139 (Net
4396uid 16544,0
4397decl (Decl
4398n "alarm_refclk_too_low"
4399t "std_logic"
4400o 59
4401suid 227,0
4402i "'0'"
4403)
4404declText (MLText
4405uid 16545,0
4406va (VaSet
4407font "Courier New,8,0"
4408)
4409xt "39000,52000,75000,52800"
4410st "SIGNAL alarm_refclk_too_low : std_logic := '0'"
4411)
4412)
4413*140 (Net
4414uid 16574,0
4415decl (Decl
4416n "counter_result"
4417t "std_logic_vector"
4418b "(11 downto 0)"
4419o 61
4420suid 230,0
4421i "(others => '0')"
4422)
4423declText (MLText
4424uid 16575,0
4425va (VaSet
4426font "Courier New,8,0"
4427)
4428xt "39000,53600,81000,54400"
4429st "SIGNAL counter_result : std_logic_vector(11 downto 0) := (others => '0')"
4430)
4431)
4432*141 (SaComponent
4433uid 17195,0
4434optionalChildren [
4435*142 (CptPort
4436uid 17027,0
4437ps "OnEdgeStrategy"
4438shape (Triangle
4439uid 17028,0
4440ro 90
4441va (VaSet
4442vasetType 1
4443fg "0,65535,0"
4444)
4445xt "80000,70625,80750,71375"
4446)
4447tg (CPTG
4448uid 17029,0
4449ps "CptPortTextPlaceStrategy"
4450stg "RightVerticalLayoutStrategy"
4451f (Text
4452uid 17030,0
4453va (VaSet
4454)
4455xt "74800,70500,79000,71500"
4456st "wiz_reset"
4457ju 2
4458blo "79000,71300"
4459)
4460)
4461thePort (LogicalPort
4462m 1
4463decl (Decl
4464n "wiz_reset"
4465t "std_logic"
4466o 50
4467suid 2,0
4468i "'1'"
4469)
4470)
4471)
4472*143 (CptPort
4473uid 17031,0
4474ps "OnEdgeStrategy"
4475shape (Triangle
4476uid 17032,0
4477ro 90
4478va (VaSet
4479vasetType 1
4480fg "0,65535,0"
4481)
4482xt "80000,119625,80750,120375"
4483)
4484tg (CPTG
4485uid 17033,0
4486ps "CptPortTextPlaceStrategy"
4487stg "RightVerticalLayoutStrategy"
4488f (Text
4489uid 17034,0
4490va (VaSet
4491)
4492xt "74600,119500,79000,120500"
4493st "led : (7:0)"
4494ju 2
4495blo "79000,120300"
4496)
4497)
4498thePort (LogicalPort
4499m 1
4500decl (Decl
4501n "led"
4502t "std_logic_vector"
4503b "(7 DOWNTO 0)"
4504posAdd 0
4505o 38
4506suid 7,0
4507i "(OTHERS => '0')"
4508)
4509)
4510)
4511*144 (CptPort
4512uid 17035,0
4513ps "OnEdgeStrategy"
4514shape (Triangle
4515uid 17036,0
4516ro 90
4517va (VaSet
4518vasetType 1
4519fg "0,65535,0"
4520)
4521xt "51250,77625,52000,78375"
4522)
4523tg (CPTG
4524uid 17037,0
4525ps "CptPortTextPlaceStrategy"
4526stg "VerticalLayoutStrategy"
4527f (Text
4528uid 17038,0
4529va (VaSet
4530)
4531xt "53000,77500,56000,78500"
4532st "trigger"
4533blo "53000,78300"
4534)
4535)
4536thePort (LogicalPort
4537decl (Decl
4538n "trigger"
4539t "std_logic"
4540preAdd 0
4541posAdd 0
4542o 14
4543suid 18,0
4544)
4545)
4546)
4547*145 (CptPort
4548uid 17039,0
4549ps "OnEdgeStrategy"
4550shape (Triangle
4551uid 17040,0
4552ro 270
4553va (VaSet
4554vasetType 1
4555fg "0,65535,0"
4556)
4557xt "51250,89625,52000,90375"
4558)
4559tg (CPTG
4560uid 17041,0
4561ps "CptPortTextPlaceStrategy"
4562stg "VerticalLayoutStrategy"
4563f (Text
4564uid 17042,0
4565va (VaSet
4566)
4567xt "53000,89500,56500,90500"
4568st "adc_oeb"
4569blo "53000,90300"
4570)
4571)
4572thePort (LogicalPort
4573m 1
4574decl (Decl
4575n "adc_oeb"
4576t "std_logic"
4577o 26
4578suid 21,0
4579i "'1'"
4580)
4581)
4582)
4583*146 (CptPort
4584uid 17043,0
4585ps "OnEdgeStrategy"
4586shape (Triangle
4587uid 17044,0
4588ro 90
4589va (VaSet
4590vasetType 1
4591fg "0,65535,0"
4592)
4593xt "51250,80625,52000,81375"
4594)
4595tg (CPTG
4596uid 17045,0
4597ps "CptPortTextPlaceStrategy"
4598stg "VerticalLayoutStrategy"
4599f (Text
4600uid 17046,0
4601va (VaSet
4602)
4603xt "53000,80500,59700,81500"
4604st "board_id : (3:0)"
4605blo "53000,81300"
4606)
4607)
4608thePort (LogicalPort
4609decl (Decl
4610n "board_id"
4611t "std_logic_vector"
4612b "(3 DOWNTO 0)"
4613o 10
4614suid 24,0
4615)
4616)
4617)
4618*147 (CptPort
4619uid 17047,0
4620ps "OnEdgeStrategy"
4621shape (Triangle
4622uid 17048,0
4623ro 90
4624va (VaSet
4625vasetType 1
4626fg "0,65535,0"
4627)
4628xt "51250,81625,52000,82375"
4629)
4630tg (CPTG
4631uid 17049,0
4632ps "CptPortTextPlaceStrategy"
4633stg "VerticalLayoutStrategy"
4634f (Text
4635uid 17050,0
4636va (VaSet
4637)
4638xt "53000,81500,59400,82500"
4639st "crate_id : (1:0)"
4640blo "53000,82300"
4641)
4642)
4643thePort (LogicalPort
4644decl (Decl
4645n "crate_id"
4646t "std_logic_vector"
4647b "(1 DOWNTO 0)"
4648o 11
4649suid 25,0
4650)
4651)
4652)
4653*148 (CptPort
4654uid 17051,0
4655ps "OnEdgeStrategy"
4656shape (Triangle
4657uid 17052,0
4658ro 90
4659va (VaSet
4660vasetType 1
4661fg "0,65535,0"
4662)
4663xt "80000,67625,80750,68375"
4664)
4665tg (CPTG
4666uid 17053,0
4667ps "CptPortTextPlaceStrategy"
4668stg "RightVerticalLayoutStrategy"
4669f (Text
4670uid 17054,0
4671va (VaSet
4672)
4673xt "72100,67500,79000,68500"
4674st "wiz_addr : (9:0)"
4675ju 2
4676blo "79000,68300"
4677)
4678)
4679thePort (LogicalPort
4680m 1
4681decl (Decl
4682n "wiz_addr"
4683t "std_logic_vector"
4684b "(9 DOWNTO 0)"
4685o 47
4686suid 26,0
4687)
4688)
4689)
4690*149 (CptPort
4691uid 17055,0
4692ps "OnEdgeStrategy"
4693shape (Diamond
4694uid 17056,0
4695ro 90
4696va (VaSet
4697vasetType 1
4698fg "0,65535,0"
4699)
4700xt "80000,68625,80750,69375"
4701)
4702tg (CPTG
4703uid 17057,0
4704ps "CptPortTextPlaceStrategy"
4705stg "RightVerticalLayoutStrategy"
4706f (Text
4707uid 17058,0
4708va (VaSet
4709)
4710xt "71800,68500,79000,69500"
4711st "wiz_data : (15:0)"
4712ju 2
4713blo "79000,69300"
4714)
4715)
4716thePort (LogicalPort
4717m 2
4718decl (Decl
4719n "wiz_data"
4720t "std_logic_vector"
4721b "(15 DOWNTO 0)"
4722o 53
4723suid 27,0
4724)
4725)
4726)
4727*150 (CptPort
4728uid 17059,0
4729ps "OnEdgeStrategy"
4730shape (Triangle
4731uid 17060,0
4732ro 90
4733va (VaSet
4734vasetType 1
4735fg "0,65535,0"
4736)
4737xt "80000,74625,80750,75375"
4738)
4739tg (CPTG
4740uid 17061,0
4741ps "CptPortTextPlaceStrategy"
4742stg "RightVerticalLayoutStrategy"
4743f (Text
4744uid 17062,0
4745va (VaSet
4746)
4747xt "76000,74500,79000,75500"
4748st "wiz_cs"
4749ju 2
4750blo "79000,75300"
4751)
4752)
4753thePort (LogicalPort
4754m 1
4755decl (Decl
4756n "wiz_cs"
4757t "std_logic"
4758o 48
4759suid 28,0
4760i "'1'"
4761)
4762)
4763)
4764*151 (CptPort
4765uid 17063,0
4766ps "OnEdgeStrategy"
4767shape (Triangle
4768uid 17064,0
4769ro 90
4770va (VaSet
4771vasetType 1
4772fg "0,65535,0"
4773)
4774xt "80000,72625,80750,73375"
4775)
4776tg (CPTG
4777uid 17065,0
4778ps "CptPortTextPlaceStrategy"
4779stg "RightVerticalLayoutStrategy"
4780f (Text
4781uid 17066,0
4782va (VaSet
4783)
4784xt "75800,72500,79000,73500"
4785st "wiz_wr"
4786ju 2
4787blo "79000,73300"
4788)
4789)
4790thePort (LogicalPort
4791m 1
4792decl (Decl
4793n "wiz_wr"
4794t "std_logic"
4795o 51
4796suid 29,0
4797i "'1'"
4798)
4799)
4800)
4801*152 (CptPort
4802uid 17067,0
4803ps "OnEdgeStrategy"
4804shape (Triangle
4805uid 17068,0
4806ro 90
4807va (VaSet
4808vasetType 1
4809fg "0,65535,0"
4810)
4811xt "80000,71625,80750,72375"
4812)
4813tg (CPTG
4814uid 17069,0
4815ps "CptPortTextPlaceStrategy"
4816stg "RightVerticalLayoutStrategy"
4817f (Text
4818uid 17070,0
4819va (VaSet
4820)
4821xt "75900,71500,79000,72500"
4822st "wiz_rd"
4823ju 2
4824blo "79000,72300"
4825)
4826)
4827thePort (LogicalPort
4828m 1
4829decl (Decl
4830n "wiz_rd"
4831t "std_logic"
4832o 49
4833suid 30,0
4834i "'1'"
4835)
4836)
4837)
4838*153 (CptPort
4839uid 17071,0
4840ps "OnEdgeStrategy"
4841shape (Triangle
4842uid 17072,0
4843ro 270
4844va (VaSet
4845vasetType 1
4846fg "0,65535,0"
4847)
4848xt "80000,73625,80750,74375"
4849)
4850tg (CPTG
4851uid 17073,0
4852ps "CptPortTextPlaceStrategy"
4853stg "RightVerticalLayoutStrategy"
4854f (Text
4855uid 17074,0
4856va (VaSet
4857)
4858xt "75800,73500,79000,74500"
4859st "wiz_int"
4860ju 2
4861blo "79000,74300"
4862)
4863)
4864thePort (LogicalPort
4865decl (Decl
4866n "wiz_int"
4867t "std_logic"
4868o 15
4869suid 31,0
4870)
4871)
4872)
4873*154 (CptPort
4874uid 17075,0
4875ps "OnEdgeStrategy"
4876shape (Triangle
4877uid 17076,0
4878ro 270
4879va (VaSet
4880vasetType 1
4881fg "0,65535,0"
4882)
4883xt "51250,73625,52000,74375"
4884)
4885tg (CPTG
4886uid 17077,0
4887ps "CptPortTextPlaceStrategy"
4888stg "VerticalLayoutStrategy"
4889f (Text
4890uid 17078,0
4891va (VaSet
4892)
4893xt "53000,73500,57800,74500"
4894st "CLK_25_PS"
4895blo "53000,74300"
4896)
4897)
4898thePort (LogicalPort
4899m 1
4900decl (Decl
4901n "CLK_25_PS"
4902t "std_logic"
4903o 17
4904suid 35,0
4905)
4906)
4907)
4908*155 (CptPort
4909uid 17079,0
4910ps "OnEdgeStrategy"
4911shape (Triangle
4912uid 17080,0
4913ro 90
4914va (VaSet
4915vasetType 1
4916fg "0,65535,0"
4917)
4918xt "80000,115625,80750,116375"
4919)
4920tg (CPTG
4921uid 17081,0
4922ps "CptPortTextPlaceStrategy"
4923stg "RightVerticalLayoutStrategy"
4924f (Text
4925uid 17082,0
4926va (VaSet
4927)
4928xt "75700,115500,79000,116500"
4929st "CLK_50"
4930ju 2
4931blo "79000,116300"
4932)
4933)
4934thePort (LogicalPort
4935m 1
4936decl (Decl
4937n "CLK_50"
4938t "std_logic"
4939preAdd 0
4940posAdd 0
4941o 18
4942suid 37,0
4943)
4944)
4945)
4946*156 (CptPort
4947uid 17083,0
4948ps "OnEdgeStrategy"
4949shape (Triangle
4950uid 17084,0
4951ro 90
4952va (VaSet
4953vasetType 1
4954fg "0,65535,0"
4955)
4956xt "51250,67625,52000,68375"
4957)
4958tg (CPTG
4959uid 17085,0
4960ps "CptPortTextPlaceStrategy"
4961stg "VerticalLayoutStrategy"
4962f (Text
4963uid 17086,0
4964va (VaSet
4965)
4966xt "53000,67500,54900,68500"
4967st "CLK"
4968blo "53000,68300"
4969)
4970)
4971thePort (LogicalPort
4972decl (Decl
4973n "CLK"
4974t "std_logic"
4975o 1
4976suid 38,0
4977)
4978)
4979)
4980*157 (CptPort
4981uid 17087,0
4982ps "OnEdgeStrategy"
4983shape (Triangle
4984uid 17088,0
4985ro 90
4986va (VaSet
4987vasetType 1
4988fg "0,65535,0"
4989)
4990xt "51250,88625,52000,89375"
4991)
4992tg (CPTG
4993uid 17089,0
4994ps "CptPortTextPlaceStrategy"
4995stg "VerticalLayoutStrategy"
4996f (Text
4997uid 17090,0
4998va (VaSet
4999)
5000xt "53000,88500,62300,89500"
5001st "adc_otr_array : (3:0)"
5002blo "53000,89300"
5003)
5004)
5005thePort (LogicalPort
5006decl (Decl
5007n "adc_otr_array"
5008t "std_logic_vector"
5009b "(3 DOWNTO 0)"
5010o 9
5011suid 40,0
5012)
5013)
5014)
5015*158 (CptPort
5016uid 17091,0
5017ps "OnEdgeStrategy"
5018shape (Triangle
5019uid 17092,0
5020ro 90
5021va (VaSet
5022vasetType 1
5023fg "0,65535,0"
5024)
5025xt "51250,94625,52000,95375"
5026)
5027tg (CPTG
5028uid 17093,0
5029ps "CptPortTextPlaceStrategy"
5030stg "VerticalLayoutStrategy"
5031f (Text
5032uid 17094,0
5033va (VaSet
5034)
5035xt "53000,94500,59900,95500"
5036st "adc_data_array"
5037blo "53000,95300"
5038)
5039)
5040thePort (LogicalPort
5041decl (Decl
5042n "adc_data_array"
5043t "adc_data_array_type"
5044o 8
5045suid 41,0
5046)
5047)
5048)
5049*159 (CptPort
5050uid 17095,0
5051ps "OnEdgeStrategy"
5052shape (Triangle
5053uid 17096,0
5054ro 270
5055va (VaSet
5056vasetType 1
5057fg "0,65535,0"
5058)
5059xt "51250,108625,52000,109375"
5060)
5061tg (CPTG
5062uid 17097,0
5063ps "CptPortTextPlaceStrategy"
5064stg "VerticalLayoutStrategy"
5065f (Text
5066uid 17098,0
5067va (VaSet
5068)
5069xt "53000,108500,62500,109500"
5070st "drs_channel_id : (3:0)"
5071blo "53000,109300"
5072)
5073)
5074thePort (LogicalPort
5075m 1
5076decl (Decl
5077n "drs_channel_id"
5078t "std_logic_vector"
5079b "(3 downto 0)"
5080o 35
5081suid 48,0
5082i "(others => '0')"
5083)
5084)
5085)
5086*160 (CptPort
5087uid 17099,0
5088ps "OnEdgeStrategy"
5089shape (Triangle
5090uid 17100,0
5091ro 270
5092va (VaSet
5093vasetType 1
5094fg "0,65535,0"
5095)
5096xt "51250,109625,52000,110375"
5097)
5098tg (CPTG
5099uid 17101,0
5100ps "CptPortTextPlaceStrategy"
5101stg "VerticalLayoutStrategy"
5102f (Text
5103uid 17102,0
5104va (VaSet
5105)
5106xt "53000,109500,58200,110500"
5107st "drs_dwrite"
5108blo "53000,110300"
5109)
5110)
5111thePort (LogicalPort
5112m 1
5113decl (Decl
5114n "drs_dwrite"
5115t "std_logic"
5116o 36
5117suid 49,0
5118i "'1'"
5119)
5120)
5121)
5122*161 (CptPort
5123uid 17103,0
5124ps "OnEdgeStrategy"
5125shape (Triangle
5126uid 17104,0
5127ro 90
5128va (VaSet
5129vasetType 1
5130fg "0,65535,0"
5131)
5132xt "51250,104625,52000,105375"
5133)
5134tg (CPTG
5135uid 17105,0
5136ps "CptPortTextPlaceStrategy"
5137stg "VerticalLayoutStrategy"
5138f (Text
5139uid 17106,0
5140va (VaSet
5141)
5142xt "53000,104500,58800,105500"
5143st "SROUT_in_0"
5144blo "53000,105300"
5145)
5146)
5147thePort (LogicalPort
5148decl (Decl
5149n "SROUT_in_0"
5150t "std_logic"
5151o 4
5152suid 52,0
5153)
5154)
5155)
5156*162 (CptPort
5157uid 17107,0
5158ps "OnEdgeStrategy"
5159shape (Triangle
5160uid 17108,0
5161ro 90
5162va (VaSet
5163vasetType 1
5164fg "0,65535,0"
5165)
5166xt "51250,105625,52000,106375"
5167)
5168tg (CPTG
5169uid 17109,0
5170ps "CptPortTextPlaceStrategy"
5171stg "VerticalLayoutStrategy"
5172f (Text
5173uid 17110,0
5174va (VaSet
5175)
5176xt "53000,105500,58700,106500"
5177st "SROUT_in_1"
5178blo "53000,106300"
5179)
5180)
5181thePort (LogicalPort
5182decl (Decl
5183n "SROUT_in_1"
5184t "std_logic"
5185o 5
5186suid 53,0
5187)
5188)
5189)
5190*163 (CptPort
5191uid 17111,0
5192ps "OnEdgeStrategy"
5193shape (Triangle
5194uid 17112,0
5195ro 90
5196va (VaSet
5197vasetType 1
5198fg "0,65535,0"
5199)
5200xt "51250,106625,52000,107375"
5201)
5202tg (CPTG
5203uid 17113,0
5204ps "CptPortTextPlaceStrategy"
5205stg "VerticalLayoutStrategy"
5206f (Text
5207uid 17114,0
5208va (VaSet
5209)
5210xt "53000,106500,58800,107500"
5211st "SROUT_in_2"
5212blo "53000,107300"
5213)
5214)
5215thePort (LogicalPort
5216decl (Decl
5217n "SROUT_in_2"
5218t "std_logic"
5219o 6
5220suid 54,0
5221)
5222)
5223)
5224*164 (CptPort
5225uid 17115,0
5226ps "OnEdgeStrategy"
5227shape (Triangle
5228uid 17116,0
5229ro 90
5230va (VaSet
5231vasetType 1
5232fg "0,65535,0"
5233)
5234xt "51250,107625,52000,108375"
5235)
5236tg (CPTG
5237uid 17117,0
5238ps "CptPortTextPlaceStrategy"
5239stg "VerticalLayoutStrategy"
5240f (Text
5241uid 17118,0
5242va (VaSet
5243)
5244xt "53000,107500,58800,108500"
5245st "SROUT_in_3"
5246blo "53000,108300"
5247)
5248)
5249thePort (LogicalPort
5250decl (Decl
5251n "SROUT_in_3"
5252t "std_logic"
5253o 7
5254suid 55,0
5255)
5256)
5257)
5258*165 (CptPort
5259uid 17119,0
5260ps "OnEdgeStrategy"
5261shape (Triangle
5262uid 17120,0
5263ro 270
5264va (VaSet
5265vasetType 1
5266fg "0,65535,0"
5267)
5268xt "51250,110625,52000,111375"
5269)
5270tg (CPTG
5271uid 17121,0
5272ps "CptPortTextPlaceStrategy"
5273stg "VerticalLayoutStrategy"
5274f (Text
5275uid 17122,0
5276va (VaSet
5277)
5278xt "53000,110500,57200,111500"
5279st "RSRLOAD"
5280blo "53000,111300"
5281)
5282)
5283thePort (LogicalPort
5284m 1
5285decl (Decl
5286n "RSRLOAD"
5287t "std_logic"
5288o 23
5289suid 56,0
5290i "'0'"
5291)
5292)
5293)
5294*166 (CptPort
5295uid 17123,0
5296ps "OnEdgeStrategy"
5297shape (Triangle
5298uid 17124,0
5299ro 270
5300va (VaSet
5301vasetType 1
5302fg "0,65535,0"
5303)
5304xt "51250,112625,52000,113375"
5305)
5306tg (CPTG
5307uid 17125,0
5308ps "CptPortTextPlaceStrategy"
5309stg "VerticalLayoutStrategy"
5310f (Text
5311uid 17126,0
5312va (VaSet
5313)
5314xt "53000,112500,55900,113500"
5315st "SRCLK"
5316blo "53000,113300"
5317)
5318)
5319thePort (LogicalPort
5320m 1
5321decl (Decl
5322n "SRCLK"
5323t "std_logic"
5324o 24
5325suid 57,0
5326i "'0'"
5327)
5328)
5329)
5330*167 (CptPort
5331uid 17127,0
5332ps "OnEdgeStrategy"
5333shape (Triangle
5334uid 17128,0
5335ro 90
5336va (VaSet
5337vasetType 1
5338fg "0,65535,0"
5339)
5340xt "80000,97625,80750,98375"
5341)
5342tg (CPTG
5343uid 17129,0
5344ps "CptPortTextPlaceStrategy"
5345stg "RightVerticalLayoutStrategy"
5346f (Text
5347uid 17130,0
5348va (VaSet
5349)
5350xt "77100,97500,79000,98500"
5351st "sclk"
5352ju 2
5353blo "79000,98300"
5354)
5355)
5356thePort (LogicalPort
5357m 1
5358decl (Decl
5359n "sclk"
5360t "std_logic"
5361o 42
5362suid 62,0
5363)
5364)
5365)
5366*168 (CptPort
5367uid 17131,0
5368ps "OnEdgeStrategy"
5369shape (Diamond
5370uid 17132,0
5371ro 90
5372va (VaSet
5373vasetType 1
5374fg "0,65535,0"
5375)
5376xt "80000,98625,80750,99375"
5377)
5378tg (CPTG
5379uid 17133,0
5380ps "CptPortTextPlaceStrategy"
5381stg "RightVerticalLayoutStrategy"
5382f (Text
5383uid 17134,0
5384va (VaSet
5385)
5386xt "77600,98500,79000,99500"
5387st "sio"
5388ju 2
5389blo "79000,99300"
5390)
5391)
5392thePort (LogicalPort
5393m 2
5394decl (Decl
5395n "sio"
5396t "std_logic"
5397preAdd 0
5398posAdd 0
5399o 52
5400suid 63,0
5401)
5402)
5403)
5404*169 (CptPort
5405uid 17135,0
5406ps "OnEdgeStrategy"
5407shape (Triangle
5408uid 17136,0
5409ro 90
5410va (VaSet
5411vasetType 1
5412fg "0,65535,0"
5413)
5414xt "80000,86625,80750,87375"
5415)
5416tg (CPTG
5417uid 17137,0
5418ps "CptPortTextPlaceStrategy"
5419stg "RightVerticalLayoutStrategy"
5420f (Text
5421uid 17138,0
5422va (VaSet
5423)
5424xt "76000,86500,79000,87500"
5425st "dac_cs"
5426ju 2
5427blo "79000,87300"
5428)
5429)
5430thePort (LogicalPort
5431m 1
5432decl (Decl
5433n "dac_cs"
5434t "std_logic"
5435o 31
5436suid 64,0
5437)
5438)
5439)
5440*170 (CptPort
5441uid 17139,0
5442ps "OnEdgeStrategy"
5443shape (Triangle
5444uid 17140,0
5445ro 90
5446va (VaSet
5447vasetType 1
5448fg "0,65535,0"
5449)
5450xt "80000,88625,80750,89375"
5451)
5452tg (CPTG
5453uid 17141,0
5454ps "CptPortTextPlaceStrategy"
5455stg "RightVerticalLayoutStrategy"
5456f (Text
5457uid 17142,0
5458va (VaSet
5459)
5460xt "72000,88500,79000,89500"
5461st "sensor_cs : (3:0)"
5462ju 2
5463blo "79000,89300"
5464)
5465)
5466thePort (LogicalPort
5467m 1
5468decl (Decl
5469n "sensor_cs"
5470t "std_logic_vector"
5471b "(3 DOWNTO 0)"
5472o 43
5473suid 65,0
5474)
5475)
5476)
5477*171 (CptPort
5478uid 17143,0
5479ps "OnEdgeStrategy"
5480shape (Triangle
5481uid 17144,0
5482ro 90
5483va (VaSet
5484vasetType 1
5485fg "0,65535,0"
5486)
5487xt "80000,99625,80750,100375"
5488)
5489tg (CPTG
5490uid 17145,0
5491ps "CptPortTextPlaceStrategy"
5492stg "RightVerticalLayoutStrategy"
5493f (Text
5494uid 17146,0
5495va (VaSet
5496)
5497xt "77000,99500,79000,100500"
5498st "mosi"
5499ju 2
5500blo "79000,100300"
5501)
5502)
5503thePort (LogicalPort
5504m 1
5505decl (Decl
5506n "mosi"
5507t "std_logic"
5508o 40
5509suid 66,0
5510i "'0'"
5511)
5512)
5513)
5514*172 (CptPort
5515uid 17147,0
5516ps "OnEdgeStrategy"
5517shape (Triangle
5518uid 17148,0
5519ro 90
5520va (VaSet
5521vasetType 1
5522fg "0,65535,0"
5523)
5524xt "80000,120625,80750,121375"
5525)
5526tg (CPTG
5527uid 17149,0
5528ps "CptPortTextPlaceStrategy"
5529stg "RightVerticalLayoutStrategy"
5530f (Text
5531uid 17150,0
5532va (VaSet
5533)
5534xt "75800,120500,79000,121500"
5535st "denable"
5536ju 2
5537blo "79000,121300"
5538)
5539)
5540thePort (LogicalPort
5541m 1
5542decl (Decl
5543n "denable"
5544t "std_logic"
5545eolc "-- default domino wave off"
5546posAdd 0
5547o 34
5548suid 67,0
5549i "'0'"
5550)
5551)
5552)
5553*173 (CptPort
5554uid 17151,0
5555ps "OnEdgeStrategy"
5556shape (Triangle
5557uid 17152,0
5558ro 90
5559va (VaSet
5560vasetType 1
5561fg "0,65535,0"
5562)
5563xt "80000,139625,80750,140375"
5564)
5565tg (CPTG
5566uid 17153,0
5567ps "CptPortTextPlaceStrategy"
5568stg "RightVerticalLayoutStrategy"
5569f (Text
5570uid 17154,0
5571va (VaSet
5572)
5573xt "74800,139500,79000,140500"
5574st "SRIN_out"
5575ju 2
5576blo "79000,140300"
5577)
5578)
5579thePort (LogicalPort
5580m 1
5581decl (Decl
5582n "SRIN_out"
5583t "std_logic"
5584o 25
5585suid 85,0
5586i "'0'"
5587)
5588)
5589)
5590*174 (CptPort
5591uid 17155,0
5592ps "OnEdgeStrategy"
5593shape (Triangle
5594uid 17156,0
5595ro 90
5596va (VaSet
5597vasetType 1
5598fg "0,65535,0"
5599)
5600xt "80000,133625,80750,134375"
5601)
5602tg (CPTG
5603uid 17157,0
5604ps "CptPortTextPlaceStrategy"
5605stg "RightVerticalLayoutStrategy"
5606f (Text
5607uid 17158,0
5608va (VaSet
5609)
5610xt "76600,133500,79000,134500"
5611st "green"
5612ju 2
5613blo "79000,134300"
5614)
5615)
5616thePort (LogicalPort
5617m 1
5618decl (Decl
5619n "green"
5620t "std_logic"
5621o 37
5622suid 86,0
5623)
5624)
5625)
5626*175 (CptPort
5627uid 17159,0
5628ps "OnEdgeStrategy"
5629shape (Triangle
5630uid 17160,0
5631ro 90
5632va (VaSet
5633vasetType 1
5634fg "0,65535,0"
5635)
5636xt "80000,134625,80750,135375"
5637)
5638tg (CPTG
5639uid 17161,0
5640ps "CptPortTextPlaceStrategy"
5641stg "RightVerticalLayoutStrategy"
5642f (Text
5643uid 17162,0
5644va (VaSet
5645)
5646xt "76300,134500,79000,135500"
5647st "amber"
5648ju 2
5649blo "79000,135300"
5650)
5651)
5652thePort (LogicalPort
5653m 1
5654decl (Decl
5655n "amber"
5656t "std_logic"
5657o 29
5658suid 87,0
5659)
5660)
5661)
5662*176 (CptPort
5663uid 17163,0
5664ps "OnEdgeStrategy"
5665shape (Triangle
5666uid 17164,0
5667ro 90
5668va (VaSet
5669vasetType 1
5670fg "0,65535,0"
5671)
5672xt "80000,135625,80750,136375"
5673)
5674tg (CPTG
5675uid 17165,0
5676ps "CptPortTextPlaceStrategy"
5677stg "RightVerticalLayoutStrategy"
5678f (Text
5679uid 17166,0
5680va (VaSet
5681)
5682xt "77300,135500,79000,136500"
5683st "red"
5684ju 2
5685blo "79000,136300"
5686)
5687)
5688thePort (LogicalPort
5689m 1
5690decl (Decl
5691n "red"
5692t "std_logic"
5693o 41
5694suid 88,0
5695)
5696)
5697)
5698*177 (CptPort
5699uid 17167,0
5700ps "OnEdgeStrategy"
5701shape (Triangle
5702uid 17168,0
5703ro 90
5704va (VaSet
5705vasetType 1
5706fg "0,65535,0"
5707)
5708xt "51250,131625,52000,132375"
5709)
5710tg (CPTG
5711uid 17169,0
5712ps "CptPortTextPlaceStrategy"
5713stg "VerticalLayoutStrategy"
5714f (Text
5715uid 17170,0
5716va (VaSet
5717)
5718xt "53000,131500,58500,132500"
5719st "D_T_in : (1:0)"
5720blo "53000,132300"
5721)
5722)
5723thePort (LogicalPort
5724decl (Decl
5725n "D_T_in"
5726t "std_logic_vector"
5727b "(1 DOWNTO 0)"
5728o 2
5729suid 91,0
5730)
5731)
5732)
5733*178 (CptPort
5734uid 17171,0
5735ps "OnEdgeStrategy"
5736shape (Triangle
5737uid 17172,0
5738ro 90
5739va (VaSet
5740vasetType 1
5741fg "0,65535,0"
5742)
5743xt "51250,132625,52000,133375"
5744)
5745tg (CPTG
5746uid 17173,0
5747ps "CptPortTextPlaceStrategy"
5748stg "VerticalLayoutStrategy"
5749f (Text
5750uid 17174,0
5751va (VaSet
5752)
5753xt "53000,132500,59100,133500"
5754st "drs_refclk_in"
5755blo "53000,133300"
5756)
5757)
5758thePort (LogicalPort
5759decl (Decl
5760n "drs_refclk_in"
5761t "std_logic"
5762eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
5763o 12
5764suid 92,0
5765)
5766)
5767)
5768*179 (CptPort
5769uid 17175,0
5770ps "OnEdgeStrategy"
5771shape (Triangle
5772uid 17176,0
5773ro 90
5774va (VaSet
5775vasetType 1
5776fg "0,65535,0"
5777)
5778xt "51250,136625,52000,137375"
5779)
5780tg (CPTG
5781uid 17177,0
5782ps "CptPortTextPlaceStrategy"
5783stg "VerticalLayoutStrategy"
5784f (Text
5785uid 17178,0
5786va (VaSet
5787)
5788xt "53000,136500,59700,137500"
5789st "plllock_in : (3:0)"
5790blo "53000,137300"
5791)
5792)
5793thePort (LogicalPort
5794decl (Decl
5795n "plllock_in"
5796t "std_logic_vector"
5797b "(3 DOWNTO 0)"
5798eolc "-- high level, if dominowave is running and DRS PLL locked"
5799o 13
5800suid 93,0
5801)
5802)
5803)
5804*180 (CptPort
5805uid 17179,0
5806ps "OnEdgeStrategy"
5807shape (Triangle
5808uid 17180,0
5809ro 90
5810va (VaSet
5811vasetType 1
5812fg "0,65535,0"
5813)
5814xt "80000,131625,80750,132375"
5815)
5816tg (CPTG
5817uid 17181,0
5818ps "CptPortTextPlaceStrategy"
5819stg "RightVerticalLayoutStrategy"
5820f (Text
5821uid 17182,0
5822va (VaSet
5823)
5824xt "69400,131500,79000,132500"
5825st "counter_result : (11:0)"
5826ju 2
5827blo "79000,132300"
5828)
5829)
5830thePort (LogicalPort
5831m 1
5832decl (Decl
5833n "counter_result"
5834t "std_logic_vector"
5835b "(11 DOWNTO 0)"
5836o 30
5837suid 94,0
5838)
5839)
5840)
5841*181 (CptPort
5842uid 17183,0
5843ps "OnEdgeStrategy"
5844shape (Triangle
5845uid 17184,0
5846ro 90
5847va (VaSet
5848vasetType 1
5849fg "0,65535,0"
5850)
5851xt "80000,129625,80750,130375"
5852)
5853tg (CPTG
5854uid 17185,0
5855ps "CptPortTextPlaceStrategy"
5856stg "RightVerticalLayoutStrategy"
5857f (Text
5858uid 17186,0
5859va (VaSet
5860)
5861xt "69000,129500,79000,130500"
5862st "alarm_refclk_too_high"
5863ju 2
5864blo "79000,130300"
5865)
5866)
5867thePort (LogicalPort
5868m 1
5869decl (Decl
5870n "alarm_refclk_too_high"
5871t "std_logic"
5872o 27
5873suid 95,0
5874)
5875)
5876)
5877*182 (CptPort
5878uid 17187,0
5879ps "OnEdgeStrategy"
5880shape (Triangle
5881uid 17188,0
5882ro 90
5883va (VaSet
5884vasetType 1
5885fg "0,65535,0"
5886)
5887xt "80000,130625,80750,131375"
5888)
5889tg (CPTG
5890uid 17189,0
5891ps "CptPortTextPlaceStrategy"
5892stg "RightVerticalLayoutStrategy"
5893f (Text
5894uid 17190,0
5895va (VaSet
5896)
5897xt "69400,130500,79000,131500"
5898st "alarm_refclk_too_low"
5899ju 2
5900blo "79000,131300"
5901)
5902)
5903thePort (LogicalPort
5904m 1
5905decl (Decl
5906n "alarm_refclk_too_low"
5907t "std_logic"
5908posAdd 0
5909o 28
5910suid 96,0
5911)
5912)
5913)
5914*183 (CptPort
5915uid 17191,0
5916ps "OnEdgeStrategy"
5917shape (Triangle
5918uid 17192,0
5919ro 270
5920va (VaSet
5921vasetType 1
5922fg "0,65535,0"
5923)
5924xt "51250,70625,52000,71375"
5925)
5926tg (CPTG
5927uid 17193,0
5928ps "CptPortTextPlaceStrategy"
5929stg "VerticalLayoutStrategy"
5930f (Text
5931uid 17194,0
5932va (VaSet
5933)
5934xt "53000,70500,57000,71500"
5935st "ADC_CLK"
5936blo "53000,71300"
5937)
5938)
5939thePort (LogicalPort
5940lang 2
5941m 1
5942decl (Decl
5943n "ADC_CLK"
5944t "std_logic"
5945o 16
5946suid 97,0
5947)
5948)
5949)
5950*184 (CptPort
5951uid 17620,0
5952ps "OnEdgeStrategy"
5953shape (Triangle
5954uid 17621,0
5955ro 90
5956va (VaSet
5957vasetType 1
5958fg "0,65535,0"
5959)
5960xt "80000,143625,80750,144375"
5961)
5962tg (CPTG
5963uid 17622,0
5964ps "CptPortTextPlaceStrategy"
5965stg "RightVerticalLayoutStrategy"
5966f (Text
5967uid 17623,0
5968va (VaSet
5969)
5970xt "73400,143500,79000,144500"
5971st "trigger_veto"
5972ju 2
5973blo "79000,144300"
5974)
5975)
5976thePort (LogicalPort
5977m 1
5978decl (Decl
5979n "trigger_veto"
5980t "std_logic"
5981o 45
5982suid 98,0
5983i "'1'"
5984)
5985)
5986)
5987*185 (CptPort
5988uid 17711,0
5989ps "OnEdgeStrategy"
5990shape (Triangle
5991uid 17712,0
5992ro 270
5993va (VaSet
5994vasetType 1
5995fg "0,65535,0"
5996)
5997xt "80000,149625,80750,150375"
5998)
5999tg (CPTG
6000uid 17713,0
6001ps "CptPortTextPlaceStrategy"
6002stg "RightVerticalLayoutStrategy"
6003f (Text
6004uid 17714,0
6005va (VaSet
6006)
6007xt "70900,149500,79000,150500"
6008st "FTM_RS485_rx_d"
6009ju 2
6010blo "79000,150300"
6011)
6012)
6013thePort (LogicalPort
6014decl (Decl
6015n "FTM_RS485_rx_d"
6016t "std_logic"
6017o 3
6018suid 99,0
6019)
6020)
6021)
6022*186 (CptPort
6023uid 17715,0
6024ps "OnEdgeStrategy"
6025shape (Triangle
6026uid 17716,0
6027ro 90
6028va (VaSet
6029vasetType 1
6030fg "0,65535,0"
6031)
6032xt "80000,147625,80750,148375"
6033)
6034tg (CPTG
6035uid 17717,0
6036ps "CptPortTextPlaceStrategy"
6037stg "RightVerticalLayoutStrategy"
6038f (Text
6039uid 17718,0
6040va (VaSet
6041)
6042xt "70600,147500,79000,148500"
6043st "FTM_RS485_rx_en"
6044ju 2
6045blo "79000,148300"
6046)
6047)
6048thePort (LogicalPort
6049m 1
6050decl (Decl
6051n "FTM_RS485_rx_en"
6052t "std_logic"
6053o 20
6054suid 101,0
6055)
6056)
6057)
6058*187 (CptPort
6059uid 17719,0
6060ps "OnEdgeStrategy"
6061shape (Triangle
6062uid 17720,0
6063ro 90
6064va (VaSet
6065vasetType 1
6066fg "0,65535,0"
6067)
6068xt "80000,148625,80750,149375"
6069)
6070tg (CPTG
6071uid 17721,0
6072ps "CptPortTextPlaceStrategy"
6073stg "RightVerticalLayoutStrategy"
6074f (Text
6075uid 17722,0
6076va (VaSet
6077)
6078xt "70900,148500,79000,149500"
6079st "FTM_RS485_tx_d"
6080ju 2
6081blo "79000,149300"
6082)
6083)
6084thePort (LogicalPort
6085m 1
6086decl (Decl
6087n "FTM_RS485_tx_d"
6088t "std_logic"
6089o 21
6090suid 100,0
6091)
6092)
6093)
6094*188 (CptPort
6095uid 17723,0
6096ps "OnEdgeStrategy"
6097shape (Triangle
6098uid 17724,0
6099ro 90
6100va (VaSet
6101vasetType 1
6102fg "0,65535,0"
6103)
6104xt "80000,146625,80750,147375"
6105)
6106tg (CPTG
6107uid 17725,0
6108ps "CptPortTextPlaceStrategy"
6109stg "RightVerticalLayoutStrategy"
6110f (Text
6111uid 17726,0
6112va (VaSet
6113)
6114xt "70600,146500,79000,147500"
6115st "FTM_RS485_tx_en"
6116ju 2
6117blo "79000,147300"
6118)
6119)
6120thePort (LogicalPort
6121m 1
6122decl (Decl
6123n "FTM_RS485_tx_en"
6124t "std_logic"
6125o 22
6126suid 102,0
6127)
6128)
6129)
6130*189 (CptPort
6131uid 17842,0
6132ps "OnEdgeStrategy"
6133shape (Triangle
6134uid 17843,0
6135ro 90
6136va (VaSet
6137vasetType 1
6138fg "0,65535,0"
6139)
6140xt "80000,105625,80750,106375"
6141)
6142tg (CPTG
6143uid 17844,0
6144ps "CptPortTextPlaceStrategy"
6145stg "RightVerticalLayoutStrategy"
6146f (Text
6147uid 17845,0
6148va (VaSet
6149)
6150xt "70600,105500,79000,106500"
6151st "w5300_state : (7:0)"
6152ju 2
6153blo "79000,106300"
6154)
6155)
6156thePort (LogicalPort
6157m 1
6158decl (Decl
6159n "w5300_state"
6160t "std_logic_vector"
6161b "(7 DOWNTO 0)"
6162eolc "-- state is encoded here ... useful for debugging."
6163posAdd 0
6164o 46
6165suid 103,0
6166)
6167)
6168)
6169*190 (CptPort
6170uid 18058,0
6171ps "OnEdgeStrategy"
6172shape (Triangle
6173uid 18059,0
6174ro 90
6175va (VaSet
6176vasetType 1
6177fg "0,65535,0"
6178)
6179xt "80000,106625,80750,107375"
6180)
6181tg (CPTG
6182uid 18060,0
6183ps "CptPortTextPlaceStrategy"
6184stg "RightVerticalLayoutStrategy"
6185f (Text
6186uid 18061,0
6187va (VaSet
6188)
6189xt "68600,106500,79000,107500"
6190st "debug_data_ram_empty"
6191ju 2
6192blo "79000,107300"
6193)
6194)
6195thePort (LogicalPort
6196m 1
6197decl (Decl
6198n "debug_data_ram_empty"
6199t "std_logic"
6200o 32
6201suid 104,0
6202)
6203)
6204)
6205*191 (CptPort
6206uid 18062,0
6207ps "OnEdgeStrategy"
6208shape (Triangle
6209uid 18063,0
6210ro 90
6211va (VaSet
6212vasetType 1
6213fg "0,65535,0"
6214)
6215xt "80000,107625,80750,108375"
6216)
6217tg (CPTG
6218uid 18064,0
6219ps "CptPortTextPlaceStrategy"
6220stg "RightVerticalLayoutStrategy"
6221f (Text
6222uid 18065,0
6223va (VaSet
6224)
6225xt "71500,107500,79000,108500"
6226st "debug_data_valid"
6227ju 2
6228blo "79000,108300"
6229)
6230)
6231thePort (LogicalPort
6232m 1
6233decl (Decl
6234n "debug_data_valid"
6235t "std_logic"
6236o 33
6237suid 105,0
6238)
6239)
6240)
6241*192 (CptPort
6242uid 18187,0
6243ps "OnEdgeStrategy"
6244shape (Triangle
6245uid 18188,0
6246ro 90
6247va (VaSet
6248vasetType 1
6249fg "0,65535,0"
6250)
6251xt "80000,104625,80750,105375"
6252)
6253tg (CPTG
6254uid 18189,0
6255ps "CptPortTextPlaceStrategy"
6256stg "RightVerticalLayoutStrategy"
6257f (Text
6258uid 18190,0
6259va (VaSet
6260)
6261xt "67600,104500,79000,105500"
6262st "mem_manager_state : (3:0)"
6263ju 2
6264blo "79000,105300"
6265)
6266)
6267thePort (LogicalPort
6268lang 2
6269m 1
6270decl (Decl
6271n "mem_manager_state"
6272t "std_logic_vector"
6273b "(3 DOWNTO 0)"
6274eolc "-- state is encoded here ... useful for debugging."
6275posAdd 0
6276o 39
6277suid 106,0
6278)
6279)
6280)
6281*193 (CptPort
6282uid 18322,0
6283ps "OnEdgeStrategy"
6284shape (Triangle
6285uid 18323,0
6286ro 90
6287va (VaSet
6288vasetType 1
6289fg "0,65535,0"
6290)
6291xt "80000,108625,80750,109375"
6292)
6293tg (CPTG
6294uid 18324,0
6295ps "CptPortTextPlaceStrategy"
6296stg "RightVerticalLayoutStrategy"
6297f (Text
6298uid 18325,0
6299va (VaSet
6300)
6301xt "72100,108500,79000,109500"
6302st "DG_state : (7:0)"
6303ju 2
6304blo "79000,109300"
6305)
6306)
6307thePort (LogicalPort
6308m 1
6309decl (Decl
6310n "DG_state"
6311t "std_logic_vector"
6312b "(7 downto 0)"
6313prec "-- for debugging"
6314preAdd 0
6315o 19
6316suid 108,0
6317)
6318)
6319)
6320*194 (CptPort
6321uid 18471,0
6322ps "OnEdgeStrategy"
6323shape (Triangle
6324uid 18472,0
6325ro 90
6326va (VaSet
6327vasetType 1
6328fg "0,65535,0"
6329)
6330xt "80000,150625,80750,151375"
6331)
6332tg (CPTG
6333uid 18473,0
6334ps "CptPortTextPlaceStrategy"
6335stg "RightVerticalLayoutStrategy"
6336f (Text
6337uid 18474,0
6338va (VaSet
6339)
6340xt "67100,150500,79000,151500"
6341st "socket_tx_free_out : (16:0)"
6342ju 2
6343blo "79000,151300"
6344)
6345)
6346thePort (LogicalPort
6347m 1
6348decl (Decl
6349n "socket_tx_free_out"
6350t "std_logic_vector"
6351b "(16 DOWNTO 0)"
6352eolc "-- 17bit value .. that's true"
6353posAdd 0
6354o 44
6355suid 109,0
6356)
6357)
6358)
6359]
6360shape (Rectangle
6361uid 17196,0
6362va (VaSet
6363vasetType 1
6364fg "0,65535,0"
6365lineColor "0,32896,0"
6366lineWidth 2
6367)
6368xt "52000,66000,80000,153000"
6369)
6370oxt "15000,-8000,43000,70000"
6371ttg (MlTextGroup
6372uid 17197,0
6373ps "CenterOffsetStrategy"
6374stg "VerticalLayoutStrategy"
6375textVec [
6376*195 (Text
6377uid 17198,0
6378va (VaSet
6379font "Arial,8,1"
6380)
6381xt "55200,141000,61400,142000"
6382st "FACT_FAD_lib"
6383blo "55200,141800"
6384tm "BdLibraryNameMgr"
6385)
6386*196 (Text
6387uid 17199,0
6388va (VaSet
6389font "Arial,8,1"
6390)
6391xt "55200,142000,59400,143000"
6392st "FAD_main"
6393blo "55200,142800"
6394tm "CptNameMgr"
6395)
6396*197 (Text
6397uid 17200,0
6398va (VaSet
6399font "Arial,8,1"
6400)
6401xt "55200,143000,61000,144000"
6402st "I_board_main"
6403blo "55200,143800"
6404tm "InstanceNameMgr"
6405)
6406]
6407)
6408ga (GenericAssociation
6409uid 17201,0
6410ps "EdgeToEdgeStrategy"
6411matrix (Matrix
6412uid 17202,0
6413text (MLText
6414uid 17203,0
6415va (VaSet
6416font "Courier New,8,0"
6417)
6418xt "52000,65200,81500,66000"
6419st "RAMADDRWIDTH64b = LOG2_OF_RAM_SIZE_64B ( integer ) "
6420)
6421header ""
6422)
6423elements [
6424(GiElement
6425name "RAMADDRWIDTH64b"
6426type "integer"
6427value "LOG2_OF_RAM_SIZE_64B"
6428)
6429]
6430)
6431viewicon (ZoomableIcon
6432uid 17204,0
6433sl 0
6434va (VaSet
6435vasetType 1
6436fg "49152,49152,49152"
6437)
6438xt "52250,151250,53750,152750"
6439iconName "BlockDiagram.png"
6440iconMaskName "BlockDiagram.msk"
6441ftype 1
6442)
6443viewiconposition 0
6444portVis (PortSigDisplay
6445)
6446archFileType "UNKNOWN"
6447)
6448*198 (Net
6449uid 17294,0
6450lang 2
6451decl (Decl
6452n "ADC_CLK"
6453t "std_logic"
6454o 53
6455suid 231,0
6456)
6457declText (MLText
6458uid 17295,0
6459va (VaSet
6460font "Courier New,8,0"
6461)
6462xt "39000,46400,61000,47200"
6463st "SIGNAL ADC_CLK : std_logic"
6464)
6465)
6466*199 (PortIoOut
6467uid 17401,0
6468shape (CompositeShape
6469uid 17402,0
6470va (VaSet
6471vasetType 1
6472fg "0,0,32768"
6473)
6474optionalChildren [
6475(Pentagon
6476uid 17403,0
6477sl 0
6478ro 270
6479xt "100500,143625,102000,144375"
6480)
6481(Line
6482uid 17404,0
6483sl 0
6484ro 270
6485xt "100000,144000,100500,144000"
6486pts [
6487"100000,144000"
6488"100500,144000"
6489]
6490)
6491]
6492)
6493stc 0
6494sf 1
6495tg (WTG
6496uid 17405,0
6497ps "PortIoTextPlaceStrategy"
6498stg "STSignalDisplayStrategy"
6499f (Text
6500uid 17406,0
6501va (VaSet
6502)
6503xt "103000,143500,105900,144500"
6504st "TRG_V"
6505blo "103000,144300"
6506tm "WireNameMgr"
6507)
6508)
6509)
6510*200 (Net
6511uid 17413,0
6512lang 2
6513decl (Decl
6514n "TRG_V"
6515t "std_logic"
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8344)
8345sed 1
8346awe 1
8347portVis (PortSigDisplay
8348disp 1
8349sN 0
8350sTC 0
8351selT 0
8352)
8353prms (Property
8354pclass "params"
8355pname "params"
8356ptn "String"
8357)
8358visOptions (mwParamsVisibilityOptions
8359)
8360)
8361*278 (Net
8362uid 20219,0
8363decl (Decl
8364n "trigger_veto"
8365t "std_logic"
8366o 73
8367suid 249,0
8368i "'1'"
8369)
8370declText (MLText
8371uid 20220,0
8372va (VaSet
8373font "Courier New,8,0"
8374)
8375xt "39000,62400,75000,63200"
8376st "SIGNAL trigger_veto : std_logic := '1'"
8377)
8378)
8379*279 (Wire
8380uid 245,0
8381shape (OrthoPolyLine
8382uid 246,0
8383va (VaSet
8384vasetType 3
8385)
8386xt "21000,68000,51250,68000"
8387pts [
8388"51250,68000"
8389"21000,68000"
8390]
8391)
8392start &156
8393end &13
8394sat 32
8395eat 32
8396stc 0
8397st 0
8398sf 1
8399si 0
8400tg (WTG
8401uid 249,0
8402ps "ConnStartEndStrategy"
8403stg "STSignalDisplayStrategy"
8404f (Text
8405uid 250,0
8406va (VaSet
8407isHidden 1
8408)
8409xt "53250,67000,56450,68000"
8410st "X_50M"
8411blo "53250,67800"
8412tm "WireNameMgr"
8413)
8414)
8415on &32
8416)
8417*280 (Wire
8418uid 277,0
8419shape (OrthoPolyLine
8420uid 278,0
8421va (VaSet
8422vasetType 3
8423lineWidth 2
8424)
8425xt "32000,81000,51250,81000"
8426pts [
8427"51250,81000"
8428"32000,81000"
8429]
8430)
8431start &146
8432end &14
8433sat 32
8434eat 2
8435sty 1
8436st 0
8437sf 1
8438si 0
8439tg (WTG
8440uid 281,0
8441ps "ConnStartEndStrategy"
8442stg "STSignalDisplayStrategy"
8443f (Text
8444uid 282,0
8445va (VaSet
8446)
8447xt "44000,80000,50700,81000"
8448st "board_id : (3:0)"
8449blo "44000,80800"
8450tm "WireNameMgr"
8451)
8452)
8453on &18
8454)
8455*281 (Wire
8456uid 285,0
8457shape (OrthoPolyLine
8458uid 286,0
8459va (VaSet
8460vasetType 3
8461lineWidth 2
8462)
8463xt "32000,82000,51250,82000"
8464pts [
8465"51250,82000"
8466"32000,82000"
8467]
8468)
8469start &147
8470end &14
8471sat 32
8472eat 2
8473sty 1
8474st 0
8475sf 1
8476si 0
8477tg (WTG
8478uid 289,0
8479ps "ConnStartEndStrategy"
8480stg "STSignalDisplayStrategy"
8481f (Text
8482uid 290,0
8483va (VaSet
8484)
8485xt "44000,81000,50400,82000"
8486st "crate_id : (1:0)"
8487blo "44000,81800"
8488tm "WireNameMgr"
8489)
8490)
8491on &19
8492)
8493*282 (Wire
8494uid 362,0
8495shape (OrthoPolyLine
8496uid 363,0
8497va (VaSet
8498vasetType 3
8499)
8500xt "21000,90000,51250,90000"
8501pts [
8502"21000,90000"
8503"51250,90000"
8504]
8505)
8506start &39
8507end &145
8508sat 32
8509eat 32
8510stc 0
8511st 0
8512sf 1
8513si 0
8514tg (WTG
8515uid 364,0
8516ps "ConnStartEndStrategy"
8517stg "STSignalDisplayStrategy"
8518f (Text
8519uid 365,0
8520va (VaSet
8521isHidden 1
8522)
8523xt "22000,89000,25700,90000"
8524st "OE_ADC"
8525blo "22000,89800"
8526tm "WireNameMgr"
8527)
8528)
8529on &40
8530)
8531*283 (Wire
8532uid 418,0
8533shape (OrthoPolyLine
8534uid 419,0
8535va (VaSet
8536vasetType 3
8537)
8538xt "80750,71000,90000,71000"
8539pts [
8540"80750,71000"
8541"90000,71000"
8542]
8543)
8544start &142
8545end &20
8546sat 32
8547eat 32
8548stc 0
8549st 0
8550sf 1
8551si 0
8552tg (WTG
8553uid 422,0
8554ps "ConnStartEndStrategy"
8555stg "STSignalDisplayStrategy"
8556f (Text
8557uid 423,0
8558va (VaSet
8559isHidden 1
8560)
8561xt "82000,70000,85400,71000"
8562st "W_RES"
8563blo "82000,70800"
8564tm "WireNameMgr"
8565)
8566)
8567on &72
8568)
8569*284 (Wire
8570uid 426,0
8571shape (OrthoPolyLine
8572uid 427,0
8573va (VaSet
8574vasetType 3
8575lineWidth 2
8576)
8577xt "80750,68000,90000,68000"
8578pts [
8579"80750,68000"
8580"90000,68000"
8581]
8582)
8583start &148
8584end &21
8585sat 32
8586eat 32
8587sty 1
8588stc 0
8589st 0
8590sf 1
8591si 0
8592tg (WTG
8593uid 430,0
8594ps "ConnStartEndStrategy"
8595stg "STSignalDisplayStrategy"
8596f (Text
8597uid 431,0
8598va (VaSet
8599isHidden 1
8600)
8601xt "82000,67000,84400,68000"
8602st "W_A"
8603blo "82000,67800"
8604tm "WireNameMgr"
8605)
8606)
8607on &70
8608)
8609*285 (Wire
8610uid 434,0
8611shape (OrthoPolyLine
8612uid 435,0
8613va (VaSet
8614vasetType 3
8615)
8616xt "80750,75000,90000,75000"
8617pts [
8618"80750,75000"
8619"90000,75000"
8620]
8621)
8622start &150
8623end &22
8624sat 32
8625eat 32
8626stc 0
8627st 0
8628sf 1
8629si 0
8630tg (WTG
8631uid 438,0
8632ps "ConnStartEndStrategy"
8633stg "STSignalDisplayStrategy"
8634f (Text
8635uid 439,0
8636va (VaSet
8637isHidden 1
8638)
8639xt "82000,74000,84900,75000"
8640st "W_CS"
8641blo "82000,74800"
8642tm "WireNameMgr"
8643)
8644)
8645on &76
8646)
8647*286 (Wire
8648uid 442,0
8649shape (OrthoPolyLine
8650uid 443,0
8651va (VaSet
8652vasetType 3
8653lineWidth 2
8654)
8655xt "80750,69000,90000,69000"
8656pts [
8657"80750,69000"
8658"90000,69000"
8659]
8660)
8661start &149
8662end &23
8663sat 32
8664eat 32
8665sty 1
8666stc 0
8667st 0
8668sf 1
8669si 0
8670tg (WTG
8671uid 446,0
8672ps "ConnStartEndStrategy"
8673stg "STSignalDisplayStrategy"
8674f (Text
8675uid 447,0
8676va (VaSet
8677isHidden 1
8678)
8679xt "82000,68000,84400,69000"
8680st "W_D"
8681blo "82000,68800"
8682tm "WireNameMgr"
8683)
8684)
8685on &71
8686)
8687*287 (Wire
8688uid 450,0
8689shape (OrthoPolyLine
8690uid 451,0
8691va (VaSet
8692vasetType 3
8693)
8694xt "80750,74000,90000,74000"
8695pts [
8696"90000,74000"
8697"80750,74000"
8698]
8699)
8700start &24
8701end &153
8702sat 32
8703eat 32
8704stc 0
8705st 0
8706sf 1
8707si 0
8708tg (WTG
8709uid 454,0
8710ps "ConnStartEndStrategy"
8711stg "STSignalDisplayStrategy"
8712f (Text
8713uid 455,0
8714va (VaSet
8715isHidden 1
8716)
8717xt "82000,73000,85300,74000"
8718st "W_INT"
8719blo "82000,73800"
8720tm "WireNameMgr"
8721)
8722)
8723on &75
8724)
8725*288 (Wire
8726uid 458,0
8727shape (OrthoPolyLine
8728uid 459,0
8729va (VaSet
8730vasetType 3
8731)
8732xt "80750,72000,90000,72000"
8733pts [
8734"80750,72000"
8735"90000,72000"
8736]
8737)
8738start &152
8739end &25
8740sat 32
8741eat 32
8742stc 0
8743st 0
8744sf 1
8745si 0
8746tg (WTG
8747uid 462,0
8748ps "ConnStartEndStrategy"
8749stg "STSignalDisplayStrategy"
8750f (Text
8751uid 463,0
8752va (VaSet
8753isHidden 1
8754)
8755xt "82000,71000,84900,72000"
8756st "W_RD"
8757blo "82000,71800"
8758tm "WireNameMgr"
8759)
8760)
8761on &73
8762)
8763*289 (Wire
8764uid 466,0
8765shape (OrthoPolyLine
8766uid 467,0
8767va (VaSet
8768vasetType 3
8769)
8770xt "80750,73000,90000,73000"
8771pts [
8772"80750,73000"
8773"90000,73000"
8774]
8775)
8776start &151
8777end &26
8778sat 32
8779eat 32
8780stc 0
8781st 0
8782sf 1
8783si 0
8784tg (WTG
8785uid 470,0
8786ps "ConnStartEndStrategy"
8787stg "STSignalDisplayStrategy"
8788f (Text
8789uid 471,0
8790va (VaSet
8791isHidden 1
8792)
8793xt "82000,72000,85200,73000"
8794st "W_WR"
8795blo "82000,72800"
8796tm "WireNameMgr"
8797)
8798)
8799on &74
8800)
8801*290 (Wire
8802uid 1467,0
8803shape (OrthoPolyLine
8804uid 1468,0
8805va (VaSet
8806vasetType 3
8807)
8808xt "30000,95000,51250,95000"
8809pts [
8810"30000,95000"
8811"41000,95000"
8812"51250,95000"
8813]
8814)
8815start &43
8816end &158
8817sat 2
8818eat 32
8819st 0
8820sf 1
8821si 0
8822tg (WTG
8823uid 1471,0
8824ps "ConnStartEndStrategy"
8825stg "STSignalDisplayStrategy"
8826f (Text
8827uid 1472,0
8828va (VaSet
8829)
8830xt "32000,94000,38900,95000"
8831st "adc_data_array"
8832blo "32000,94800"
8833tm "WireNameMgr"
8834)
8835)
8836on &27
8837)
8838*291 (Wire
8839uid 1730,0
8840shape (OrthoPolyLine
8841uid 1731,0
8842va (VaSet
8843vasetType 3
8844lineWidth 2
8845)
8846xt "21000,89000,51250,89000"
8847pts [
8848"21000,89000"
8849"51250,89000"
8850]
8851)
8852start &41
8853end &157
8854sat 32
8855eat 32
8856sty 1
8857stc 0
8858st 0
8859sf 1
8860si 0
8861tg (WTG
8862uid 1734,0
8863ps "ConnStartEndStrategy"
8864stg "STSignalDisplayStrategy"
8865f (Text
8866uid 1735,0
8867va (VaSet
8868isHidden 1
8869)
8870xt "22000,88000,25000,89000"
8871st "A_OTR"
8872blo "22000,88800"
8873tm "WireNameMgr"
8874)
8875)
8876on &42
8877)
8878*292 (Wire
8879uid 1833,0
8880shape (OrthoPolyLine
8881uid 1834,0
8882va (VaSet
8883vasetType 3
8884lineWidth 2
8885)
8886xt "21000,109000,51250,109000"
8887pts [
8888"51250,109000"
8889"21000,109000"
8890]
8891)
8892start &159
8893end &63
8894sat 32
8895eat 32
8896sty 1
8897stc 0
8898st 0
8899sf 1
8900si 0
8901tg (WTG
8902uid 1837,0
8903ps "ConnStartEndStrategy"
8904stg "STSignalDisplayStrategy"
8905f (Text
8906uid 1838,0
8907va (VaSet
8908isHidden 1
8909)
8910xt "22000,108000,24100,109000"
8911st "D_A"
8912blo "22000,108800"
8913tm "WireNameMgr"
8914)
8915)
8916on &64
8917)
8918*293 (Wire
8919uid 1841,0
8920shape (OrthoPolyLine
8921uid 1842,0
8922va (VaSet
8923vasetType 3
8924)
8925xt "21000,110000,51250,110000"
8926pts [
8927"51250,110000"
8928"21000,110000"
8929]
8930)
8931start &160
8932end &65
8933sat 32
8934eat 32
8935stc 0
8936st 0
8937sf 1
8938si 0
8939tg (WTG
8940uid 1845,0
8941ps "ConnStartEndStrategy"
8942stg "STSignalDisplayStrategy"
8943f (Text
8944uid 1846,0
8945va (VaSet
8946isHidden 1
8947)
8948xt "22000,109000,25800,110000"
8949st "DWRITE"
8950blo "22000,109800"
8951tm "WireNameMgr"
8952)
8953)
8954on &66
8955)
8956*294 (Wire
8957uid 1865,0
8958shape (OrthoPolyLine
8959uid 1866,0
8960va (VaSet
8961vasetType 3
8962)
8963xt "21000,105000,51250,105000"
8964pts [
8965"21000,105000"
8966"51250,105000"
8967]
8968)
8969start &55
8970end &161
8971sat 32
8972eat 32
8973stc 0
8974st 0
8975sf 1
8976si 0
8977tg (WTG
8978uid 1869,0
8979ps "ConnStartEndStrategy"
8980stg "STSignalDisplayStrategy"
8981f (Text
8982uid 1870,0
8983va (VaSet
8984isHidden 1
8985)
8986xt "22000,104000,26600,105000"
8987st "D0_SROUT"
8988blo "22000,104800"
8989tm "WireNameMgr"
8990)
8991)
8992on &59
8993)
8994*295 (Wire
8995uid 1873,0
8996shape (OrthoPolyLine
8997uid 1874,0
8998va (VaSet
8999vasetType 3
9000)
9001xt "21000,106000,51250,106000"
9002pts [
9003"21000,106000"
9004"51250,106000"
9005]
9006)
9007start &56
9008end &162
9009sat 32
9010eat 32
9011stc 0
9012st 0
9013sf 1
9014si 0
9015tg (WTG
9016uid 1877,0
9017ps "ConnStartEndStrategy"
9018stg "STSignalDisplayStrategy"
9019f (Text
9020uid 1878,0
9021va (VaSet
9022isHidden 1
9023)
9024xt "22000,105000,26600,106000"
9025st "D1_SROUT"
9026blo "22000,105800"
9027tm "WireNameMgr"
9028)
9029)
9030on &60
9031)
9032*296 (Wire
9033uid 1881,0
9034shape (OrthoPolyLine
9035uid 1882,0
9036va (VaSet
9037vasetType 3
9038)
9039xt "21000,107000,51250,107000"
9040pts [
9041"21000,107000"
9042"51250,107000"
9043]
9044)
9045start &57
9046end &163
9047sat 32
9048eat 32
9049stc 0
9050st 0
9051sf 1
9052si 0
9053tg (WTG
9054uid 1885,0
9055ps "ConnStartEndStrategy"
9056stg "STSignalDisplayStrategy"
9057f (Text
9058uid 1886,0
9059va (VaSet
9060isHidden 1
9061)
9062xt "22000,106000,26600,107000"
9063st "D2_SROUT"
9064blo "22000,106800"
9065tm "WireNameMgr"
9066)
9067)
9068on &61
9069)
9070*297 (Wire
9071uid 1889,0
9072shape (OrthoPolyLine
9073uid 1890,0
9074va (VaSet
9075vasetType 3
9076)
9077xt "21000,108000,51250,108000"
9078pts [
9079"21000,108000"
9080"51250,108000"
9081]
9082)
9083start &58
9084end &164
9085sat 32
9086eat 32
9087stc 0
9088st 0
9089sf 1
9090si 0
9091tg (WTG
9092uid 1893,0
9093ps "ConnStartEndStrategy"
9094stg "STSignalDisplayStrategy"
9095f (Text
9096uid 1894,0
9097va (VaSet
9098isHidden 1
9099)
9100xt "22000,107000,26600,108000"
9101st "D3_SROUT"
9102blo "22000,107800"
9103tm "WireNameMgr"
9104)
9105)
9106on &62
9107)
9108*298 (Wire
9109uid 2409,0
9110shape (OrthoPolyLine
9111uid 2410,0
9112va (VaSet
9113vasetType 3
9114)
9115xt "21000,111000,51250,111000"
9116pts [
9117"51250,111000"
9118"21000,111000"
9119]
9120)
9121start &165
9122end &29
9123sat 32
9124eat 32
9125stc 0
9126st 0
9127sf 1
9128si 0
9129tg (WTG
9130uid 2413,0
9131ps "ConnStartEndStrategy"
9132stg "STSignalDisplayStrategy"
9133f (Text
9134uid 2414,0
9135va (VaSet
9136isHidden 1
9137)
9138xt "22000,110000,26200,111000"
9139st "RSRLOAD"
9140blo "22000,110800"
9141tm "WireNameMgr"
9142)
9143)
9144on &28
9145)
9146*299 (Wire
9147uid 3009,0
9148shape (OrthoPolyLine
9149uid 3010,0
9150va (VaSet
9151vasetType 3
9152)
9153xt "86000,95000,99000,97000"
9154pts [
9155"86000,95000"
9156"99000,97000"
9157]
9158)
9159start &238
9160end &68
9161sat 32
9162eat 32
9163stc 0
9164st 0
9165sf 1
9166si 0
9167tg (WTG
9168uid 3011,0
9169ps "ConnStartEndStrategy"
9170stg "STSignalDisplayStrategy"
9171f (Text
9172uid 3012,0
9173va (VaSet
9174isHidden 1
9175)
9176xt "87000,94000,89900,95000"
9177st "S_CLK"
9178blo "87000,94800"
9179tm "WireNameMgr"
9180)
9181)
9182on &69
9183)
9184*300 (Wire
9185uid 3015,0
9186shape (OrthoPolyLine
9187uid 3016,0
9188va (VaSet
9189vasetType 3
9190)
9191xt "80750,99000,90000,99000"
9192pts [
9193"80750,99000"
9194"90000,99000"
9195]
9196)
9197start &168
9198end &77
9199sat 32
9200eat 32
9201stc 0
9202st 0
9203sf 1
9204si 0
9205tg (WTG
9206uid 3017,0
9207ps "ConnStartEndStrategy"
9208stg "STSignalDisplayStrategy"
9209f (Text
9210uid 3018,0
9211va (VaSet
9212isHidden 1
9213)
9214xt "82750,98000,85450,99000"
9215st "MISO"
9216blo "82750,98800"
9217tm "WireNameMgr"
9218)
9219)
9220on &80
9221)
9222*301 (Wire
9223uid 3027,0
9224shape (OrthoPolyLine
9225uid 3028,0
9226va (VaSet
9227vasetType 3
9228)
9229xt "85000,84000,97000,85000"
9230pts [
9231"85000,85000"
9232"97000,84000"
9233]
9234)
9235start &212
9236end &67
9237ss 0
9238sat 32
9239eat 32
9240stc 0
9241st 0
9242sf 1
9243si 0
9244tg (WTG
9245uid 3031,0
9246ps "ConnStartEndStrategy"
9247stg "STSignalDisplayStrategy"
9248f (Text
9249uid 3032,0
9250va (VaSet
9251isHidden 1
9252)
9253xt "86000,84000,89700,85000"
9254st "DAC_CS"
9255blo "86000,84800"
9256tm "WireNameMgr"
9257)
9258)
9259on &30
9260)
9261*302 (Wire
9262uid 3218,0
9263shape (OrthoPolyLine
9264uid 3219,0
9265va (VaSet
9266vasetType 3
9267)
9268xt "22000,78000,51250,78000"
9269pts [
9270"22000,78000"
9271"51250,78000"
9272]
9273)
9274start &12
9275end &144
9276sat 32
9277eat 32
9278stc 0
9279st 0
9280sf 1
9281si 0
9282tg (WTG
9283uid 3220,0
9284ps "ConnStartEndStrategy"
9285stg "STSignalDisplayStrategy"
9286f (Text
9287uid 3221,0
9288va (VaSet
9289isHidden 1
9290)
9291xt "33000,77000,34900,78000"
9292st "TRG"
9293blo "33000,77800"
9294tm "WireNameMgr"
9295)
9296)
9297on &33
9298)
9299*303 (Wire
9300uid 3260,0
9301shape (OrthoPolyLine
9302uid 3261,0
9303va (VaSet
9304vasetType 3
9305lineWidth 2
9306)
9307xt "-1000,71000,5000,71000"
9308pts [
9309"-1000,71000"
9310"5000,71000"
9311]
9312)
9313start &31
9314end &34
9315sat 32
9316eat 2
9317sty 1
9318stc 0
9319st 0
9320sf 1
9321si 0
9322tg (WTG
9323uid 3264,0
9324ps "ConnStartEndStrategy"
9325stg "STSignalDisplayStrategy"
9326f (Text
9327uid 3265,0
9328va (VaSet
9329isHidden 1
9330)
9331xt "-23000,70000,-20100,71000"
9332st "A_CLK"
9333blo "-23000,70800"
9334tm "WireNameMgr"
9335)
9336)
9337on &38
9338)
9339*304 (Wire
9340uid 3318,0
9341shape (OrthoPolyLine
9342uid 3319,0
9343va (VaSet
9344vasetType 3
9345lineWidth 2
9346)
9347xt "21000,95000,24000,95000"
9348pts [
9349"21000,95000"
9350"24000,95000"
9351]
9352)
9353start &47
9354end &43
9355sat 32
9356eat 1
9357sty 1
9358stc 0
9359st 0
9360sf 1
9361si 0
9362tg (WTG
9363uid 3322,0
9364ps "ConnStartEndStrategy"
9365stg "STSignalDisplayStrategy"
9366f (Text
9367uid 3323,0
9368va (VaSet
9369isHidden 1
9370)
9371xt "23000,94000,25300,95000"
9372st "A0_D"
9373blo "23000,94800"
9374tm "WireNameMgr"
9375)
9376)
9377on &51
9378)
9379*305 (Wire
9380uid 3352,0
9381shape (OrthoPolyLine
9382uid 3353,0
9383va (VaSet
9384vasetType 3
9385lineWidth 2
9386)
9387xt "21000,96000,24000,96000"
9388pts [
9389"21000,96000"
9390"24000,96000"
9391]
9392)
9393start &48
9394end &43
9395sat 32
9396eat 1
9397sty 1
9398stc 0
9399st 0
9400sf 1
9401si 0
9402tg (WTG
9403uid 3356,0
9404ps "ConnStartEndStrategy"
9405stg "STSignalDisplayStrategy"
9406f (Text
9407uid 3357,0
9408va (VaSet
9409isHidden 1
9410)
9411xt "23000,95000,25300,96000"
9412st "A1_D"
9413blo "23000,95800"
9414tm "WireNameMgr"
9415)
9416)
9417on &52
9418)
9419*306 (Wire
9420uid 3360,0
9421shape (OrthoPolyLine
9422uid 3361,0
9423va (VaSet
9424vasetType 3
9425lineWidth 2
9426)
9427xt "21000,97000,24000,97000"
9428pts [
9429"21000,97000"
9430"24000,97000"
9431]
9432)
9433start &49
9434end &43
9435sat 32
9436eat 1
9437sty 1
9438stc 0
9439st 0
9440sf 1
9441si 0
9442tg (WTG
9443uid 3364,0
9444ps "ConnStartEndStrategy"
9445stg "STSignalDisplayStrategy"
9446f (Text
9447uid 3365,0
9448va (VaSet
9449isHidden 1
9450)
9451xt "23000,96000,25300,97000"
9452st "A2_D"
9453blo "23000,96800"
9454tm "WireNameMgr"
9455)
9456)
9457on &53
9458)
9459*307 (Wire
9460uid 3368,0
9461shape (OrthoPolyLine
9462uid 3369,0
9463va (VaSet
9464vasetType 3
9465lineWidth 2
9466)
9467xt "21000,98000,24000,98000"
9468pts [
9469"21000,98000"
9470"24000,98000"
9471]
9472)
9473start &50
9474end &43
9475sat 32
9476eat 1
9477sty 1
9478stc 0
9479st 0
9480sf 1
9481si 0
9482tg (WTG
9483uid 3372,0
9484ps "ConnStartEndStrategy"
9485stg "STSignalDisplayStrategy"
9486f (Text
9487uid 3373,0
9488va (VaSet
9489isHidden 1
9490)
9491xt "23000,97000,25300,98000"
9492st "A3_D"
9493blo "23000,97800"
9494tm "WireNameMgr"
9495)
9496)
9497on &54
9498)
9499*308 (Wire
9500uid 3682,0
9501shape (OrthoPolyLine
9502uid 3683,0
9503va (VaSet
9504vasetType 3
9505)
9506xt "86000,100000,99000,102000"
9507pts [
9508"86000,102000"
9509"99000,100000"
9510]
9511)
9512start &251
9513end &79
9514sat 32
9515eat 32
9516stc 0
9517st 0
9518sf 1
9519si 0
9520tg (WTG
9521uid 3686,0
9522ps "ConnStartEndStrategy"
9523stg "STSignalDisplayStrategy"
9524f (Text
9525uid 3687,0
9526va (VaSet
9527isHidden 1
9528)
9529xt "87000,101000,89700,102000"
9530st "MOSI"
9531blo "87000,101800"
9532tm "WireNameMgr"
9533)
9534)
9535on &78
9536)
9537*309 (Wire
9538uid 3834,0
9539shape (OrthoPolyLine
9540uid 3835,0
9541va (VaSet
9542vasetType 3
9543)
9544xt "132000,139000,137000,139000"
9545pts [
9546"137000,139000"
9547"132000,139000"
9548]
9549)
9550start &86
9551end &102
9552sat 32
9553eat 2
9554stc 0
9555st 0
9556sf 1
9557si 0
9558tg (WTG
9559uid 3838,0
9560ps "ConnStartEndStrategy"
9561stg "STSignalDisplayStrategy"
9562f (Text
9563uid 3839,0
9564va (VaSet
9565isHidden 1
9566)
9567xt "132000,138000,135000,139000"
9568st "EE_CS"
9569blo "132000,138800"
9570tm "WireNameMgr"
9571)
9572)
9573on &92
9574)
9575*310 (Wire
9576uid 4942,0
9577shape (OrthoPolyLine
9578uid 4943,0
9579va (VaSet
9580vasetType 3
9581lineWidth 2
9582)
9583xt "132000,118000,137000,118000"
9584pts [
9585"132000,118000"
9586"137000,118000"
9587]
9588)
9589start &102
9590end &93
9591sat 2
9592eat 32
9593sty 1
9594stc 0
9595st 0
9596sf 1
9597si 0
9598tg (WTG
9599uid 4948,0
9600ps "ConnStartEndStrategy"
9601stg "STSignalDisplayStrategy"
9602f (Text
9603uid 4949,0
9604va (VaSet
9605isHidden 1
9606)
9607xt "133750,115000,135750,116000"
9608st "D_T"
9609blo "133750,115800"
9610tm "WireNameMgr"
9611)
9612)
9613on &94
9614)
9615*311 (Wire
9616uid 6431,0
9617shape (OrthoPolyLine
9618uid 6432,0
9619va (VaSet
9620vasetType 3
9621)
9622xt "80750,121000,82000,121000"
9623pts [
9624"80750,121000"
9625"82000,121000"
9626]
9627)
9628start &172
9629end &85
9630sat 32
9631eat 32
9632stc 0
9633st 0
9634sf 1
9635si 0
9636tg (WTG
9637uid 6435,0
9638ps "ConnStartEndStrategy"
9639stg "STSignalDisplayStrategy"
9640f (Text
9641uid 6436,0
9642va (VaSet
9643isHidden 1
9644)
9645xt "92000,120000,96100,121000"
9646st "DENABLE"
9647blo "92000,120800"
9648tm "WireNameMgr"
9649)
9650)
9651on &91
9652)
9653*312 (Wire
9654uid 7144,0
9655shape (OrthoPolyLine
9656uid 7145,0
9657va (VaSet
9658vasetType 3
9659lineWidth 2
9660)
9661xt "132000,121000,137000,121000"
9662pts [
9663"132000,121000"
9664"137000,121000"
9665]
9666)
9667start &102
9668end &97
9669sat 2
9670eat 32
9671sty 1
9672st 0
9673sf 1
9674si 0
9675tg (WTG
9676uid 7148,0
9677ps "ConnStartEndStrategy"
9678stg "STSignalDisplayStrategy"
9679f (Text
9680uid 7149,0
9681va (VaSet
9682isHidden 1
9683)
9684xt "137000,133000,142300,134000"
9685st "A1_T : (7:0)"
9686blo "137000,133800"
9687tm "WireNameMgr"
9688)
9689)
9690on &98
9691)
9692*313 (Wire
9693uid 9502,0
9694shape (OrthoPolyLine
9695uid 9503,0
9696va (VaSet
9697vasetType 3
9698)
9699xt "80750,116000,85000,116000"
9700pts [
9701"80750,116000"
9702"85000,116000"
9703]
9704)
9705start &155
9706sat 32
9707eat 16
9708st 0
9709sf 1
9710si 0
9711tg (WTG
9712uid 9506,0
9713ps "ConnStartEndStrategy"
9714stg "STSignalDisplayStrategy"
9715f (Text
9716uid 9507,0
9717va (VaSet
9718)
9719xt "86000,115000,89300,116000"
9720st "CLK_50"
9721blo "86000,115800"
9722tm "WireNameMgr"
9723)
9724)
9725on &99
9726)
9727*314 (Wire
9728uid 10302,0
9729shape (OrthoPolyLine
9730uid 10303,0
9731va (VaSet
9732vasetType 3
9733lineWidth 2
9734)
9735xt "132000,120000,137000,120000"
9736pts [
9737"132000,120000"
9738"137000,120000"
9739]
9740)
9741start &102
9742end &100
9743sat 2
9744eat 32
9745sty 1
9746st 0
9747sf 1
9748si 0
9749tg (WTG
9750uid 10306,0
9751ps "ConnStartEndStrategy"
9752stg "STSignalDisplayStrategy"
9753f (Text
9754uid 10307,0
9755va (VaSet
9756isHidden 1
9757)
9758xt "133000,139000,138400,140000"
9759st "A0_T : (7:0)"
9760blo "133000,139800"
9761tm "WireNameMgr"
9762)
9763)
9764on &101
9765)
9766*315 (Wire
9767uid 11514,0
9768shape (OrthoPolyLine
9769uid 11515,0
9770va (VaSet
9771vasetType 3
9772)
9773xt "80750,150000,85000,150000"
9774pts [
9775"85000,150000"
9776"80750,150000"
9777]
9778)
9779start &108
9780end &185
9781es 0
9782sat 32
9783eat 32
9784st 0
9785sf 1
9786si 0
9787tg (WTG
9788uid 11518,0
9789ps "ConnStartEndStrategy"
9790stg "STSignalDisplayStrategy"
9791f (Text
9792uid 11519,0
9793va (VaSet
9794isHidden 1
9795)
9796xt "86000,149000,92000,150000"
9797st "RS485_E_DI"
9798blo "86000,149800"
9799tm "WireNameMgr"
9800)
9801)
9802on &109
9803)
9804*316 (Wire
9805uid 11528,0
9806shape (OrthoPolyLine
9807uid 11529,0
9808va (VaSet
9809vasetType 3
9810)
9811xt "80750,149000,85000,149000"
9812pts [
9813"80750,149000"
9814"85000,149000"
9815]
9816)
9817start &187
9818end &126
9819ss 0
9820sat 32
9821eat 32
9822st 0
9823sf 1
9824si 0
9825tg (WTG
9826uid 11532,0
9827ps "ConnStartEndStrategy"
9828stg "STSignalDisplayStrategy"
9829f (Text
9830uid 11533,0
9831va (VaSet
9832isHidden 1
9833)
9834xt "107000,148000,113200,149000"
9835st "RS485_E_DO"
9836blo "107000,148800"
9837tm "WireNameMgr"
9838)
9839)
9840on &110
9841)
9842*317 (Wire
9843uid 12320,0
9844shape (OrthoPolyLine
9845uid 12321,0
9846va (VaSet
9847vasetType 3
9848)
9849xt "80750,140000,87000,140000"
9850pts [
9851"80750,140000"
9852"87000,140000"
9853]
9854)
9855start &173
9856end &111
9857sat 32
9858eat 32
9859stc 0
9860st 0
9861sf 1
9862si 0
9863tg (WTG
9864uid 12324,0
9865ps "ConnStartEndStrategy"
9866stg "STSignalDisplayStrategy"
9867f (Text
9868uid 12325,0
9869va (VaSet
9870isHidden 1
9871)
9872xt "82000,139000,84500,140000"
9873st "SRIN"
9874blo "82000,139800"
9875tm "WireNameMgr"
9876)
9877)
9878on &112
9879)
9880*318 (Wire
9881uid 12545,0
9882shape (OrthoPolyLine
9883uid 12546,0
9884va (VaSet
9885vasetType 3
9886)
9887xt "80750,135000,87000,135000"
9888pts [
9889"80750,135000"
9890"87000,135000"
9891]
9892)
9893start &175
9894end &113
9895ss 0
9896sat 32
9897eat 32
9898st 0
9899sf 1
9900si 0
9901tg (WTG
9902uid 12549,0
9903ps "ConnStartEndStrategy"
9904stg "STSignalDisplayStrategy"
9905f (Text
9906uid 12550,0
9907va (VaSet
9908isHidden 1
9909)
9910xt "83000,134000,88200,135000"
9911st "AMBER_LED"
9912blo "83000,134800"
9913tm "WireNameMgr"
9914)
9915)
9916on &116
9917)
9918*319 (Wire
9919uid 12559,0
9920shape (OrthoPolyLine
9921uid 12560,0
9922va (VaSet
9923vasetType 3
9924)
9925xt "80750,134000,87000,134000"
9926pts [
9927"80750,134000"
9928"87000,134000"
9929]
9930)
9931start &174
9932end &114
9933ss 0
9934sat 32
9935eat 32
9936st 0
9937sf 1
9938si 0
9939tg (WTG
9940uid 12563,0
9941ps "ConnStartEndStrategy"
9942stg "STSignalDisplayStrategy"
9943f (Text
9944uid 12564,0
9945va (VaSet
9946isHidden 1
9947)
9948xt "83000,133000,88000,134000"
9949st "GREEN_LED"
9950blo "83000,133800"
9951tm "WireNameMgr"
9952)
9953)
9954on &117
9955)
9956*320 (Wire
9957uid 12573,0
9958shape (OrthoPolyLine
9959uid 12574,0
9960va (VaSet
9961vasetType 3
9962)
9963xt "80750,136000,87000,136000"
9964pts [
9965"80750,136000"
9966"87000,136000"
9967]
9968)
9969start &176
9970end &115
9971ss 0
9972sat 32
9973eat 32
9974st 0
9975sf 1
9976si 0
9977tg (WTG
9978uid 12577,0
9979ps "ConnStartEndStrategy"
9980stg "STSignalDisplayStrategy"
9981f (Text
9982uid 12578,0
9983va (VaSet
9984isHidden 1
9985)
9986xt "83000,143000,87000,144000"
9987st "RED_LED"
9988blo "83000,143800"
9989tm "WireNameMgr"
9990)
9991)
9992on &118
9993)
9994*321 (Wire
9995uid 13522,0
9996shape (OrthoPolyLine
9997uid 13523,0
9998va (VaSet
9999vasetType 3
10000lineWidth 2
10001)
10002xt "22000,81000,28000,81000"
10003pts [
10004"22000,81000"
10005"28000,81000"
10006]
10007)
10008start &119
10009end &14
10010sat 32
10011eat 1
10012sty 1
10013st 0
10014sf 1
10015si 0
10016tg (WTG
10017uid 13526,0
10018ps "ConnStartEndStrategy"
10019stg "STSignalDisplayStrategy"
10020f (Text
10021uid 13527,0
10022va (VaSet
10023)
10024xt "22000,80000,27200,81000"
10025st "LINE : (5:0)"
10026blo "22000,80800"
10027tm "WireNameMgr"
10028)
10029)
10030on &120
10031)
10032*322 (Wire
10033uid 13618,0
10034shape (OrthoPolyLine
10035uid 13619,0
10036va (VaSet
10037vasetType 3
10038lineWidth 2
10039)
10040xt "132000,128000,137000,128000"
10041pts [
10042"132000,128000"
10043"137000,128000"
10044]
10045)
10046start &102
10047end &95
10048sat 2
10049eat 32
10050sty 1
10051st 0
10052sf 1
10053si 0
10054tg (WTG
10055uid 13624,0
10056ps "ConnStartEndStrategy"
10057stg "STSignalDisplayStrategy"
10058f (Text
10059uid 13625,0
10060va (VaSet
10061isHidden 1
10062)
10063xt "134000,133000,139300,134000"
10064st "D_T2 : (1:0)"
10065blo "134000,133800"
10066tm "WireNameMgr"
10067)
10068)
10069on &96
10070)
10071*323 (Wire
10072uid 13634,0
10073shape (OrthoPolyLine
10074uid 13635,0
10075va (VaSet
10076vasetType 3
10077)
10078xt "49000,133000,51250,133000"
10079pts [
10080"49000,133000"
10081"51250,133000"
10082]
10083)
10084start &121
10085end &178
10086sat 32
10087eat 32
10088st 0
10089sf 1
10090si 0
10091tg (WTG
10092uid 13638,0
10093ps "ConnStartEndStrategy"
10094stg "STSignalDisplayStrategy"
10095f (Text
10096uid 13639,0
10097va (VaSet
10098isHidden 1
10099)
10100xt "51000,141000,54300,142000"
10101st "REFCLK"
10102blo "51000,141800"
10103tm "WireNameMgr"
10104)
10105)
10106on &122
10107)
10108*324 (Wire
10109uid 13658,0
10110shape (OrthoPolyLine
10111uid 13659,0
10112va (VaSet
10113vasetType 3
10114)
10115xt "80750,147000,85000,147000"
10116pts [
10117"80750,147000"
10118"85000,147000"
10119]
10120)
10121start &188
10122end &84
10123ss 0
10124sat 32
10125eat 32
10126st 0
10127sf 1
10128si 0
10129tg (WTG
10130uid 13664,0
10131ps "ConnStartEndStrategy"
10132stg "STSignalDisplayStrategy"
10133f (Text
10134uid 13665,0
10135va (VaSet
10136isHidden 1
10137)
10138xt "84000,145000,90100,146000"
10139st "RS485_E_DE"
10140blo "84000,145800"
10141tm "WireNameMgr"
10142)
10143)
10144on &90
10145)
10146*325 (Wire
10147uid 14328,0
10148shape (OrthoPolyLine
10149uid 14329,0
10150va (VaSet
10151vasetType 3
10152lineWidth 2
10153)
10154xt "49000,132000,51250,132000"
10155pts [
10156"49000,132000"
10157"51250,132000"
10158]
10159)
10160start &123
10161end &177
10162sat 32
10163eat 32
10164sty 1
10165st 0
10166sf 1
10167si 0
10168tg (WTG
10169uid 14332,0
10170ps "ConnStartEndStrategy"
10171stg "STSignalDisplayStrategy"
10172f (Text
10173uid 14333,0
10174va (VaSet
10175isHidden 1
10176)
10177xt "52000,138000,57900,139000"
10178st "D_T_in : (1:0)"
10179blo "52000,138800"
10180tm "WireNameMgr"
10181)
10182)
10183on &124
10184)
10185*326 (Wire
10186uid 15175,0
10187shape (OrthoPolyLine
10188uid 15176,0
10189va (VaSet
10190vasetType 3
10191lineWidth 2
10192)
10193xt "80750,120000,87000,120000"
10194pts [
10195"80750,120000"
10196"87000,120000"
10197]
10198)
10199start &143
10200sat 32
10201eat 16
10202sty 1
10203st 0
10204sf 1
10205si 0
10206tg (WTG
10207uid 15179,0
10208ps "ConnStartEndStrategy"
10209stg "STSignalDisplayStrategy"
10210f (Text
10211uid 15180,0
10212va (VaSet
10213)
10214xt "82000,119000,86400,120000"
10215st "led : (7:0)"
10216blo "82000,119800"
10217tm "WireNameMgr"
10218)
10219)
10220on &125
10221)
10222*327 (Wire
10223uid 15517,0
10224shape (OrthoPolyLine
10225uid 15518,0
10226va (VaSet
10227vasetType 3
10228)
10229xt "132000,131000,137000,131000"
10230pts [
10231"132000,131000"
10232"137000,131000"
10233]
10234)
10235start &102
10236end &81
10237sat 2
10238eat 32
10239st 0
10240sf 1
10241si 0
10242tg (WTG
10243uid 15523,0
10244ps "ConnStartEndStrategy"
10245stg "STSignalDisplayStrategy"
10246f (Text
10247uid 15524,0
10248va (VaSet
10249isHidden 1
10250)
10251xt "134000,130000,140100,131000"
10252st "RS485_C_DE"
10253blo "134000,130800"
10254tm "WireNameMgr"
10255)
10256)
10257on &88
10258)
10259*328 (Wire
10260uid 15525,0
10261shape (OrthoPolyLine
10262uid 15526,0
10263va (VaSet
10264vasetType 3
10265)
10266xt "132000,132000,137000,132000"
10267pts [
10268"132000,132000"
10269"137000,132000"
10270]
10271)
10272start &102
10273end &82
10274sat 2
10275eat 32
10276st 0
10277sf 1
10278si 0
10279tg (WTG
10280uid 15531,0
10281ps "ConnStartEndStrategy"
10282stg "STSignalDisplayStrategy"
10283f (Text
10284uid 15532,0
10285va (VaSet
10286isHidden 1
10287)
10288xt "134000,131000,140200,132000"
10289st "RS485_C_DO"
10290blo "134000,131800"
10291tm "WireNameMgr"
10292)
10293)
10294on &107
10295)
10296*329 (Wire
10297uid 15533,0
10298shape (OrthoPolyLine
10299uid 15534,0
10300va (VaSet
10301vasetType 3
10302)
10303xt "132000,133000,137000,133000"
10304pts [
10305"132000,133000"
10306"137000,133000"
10307]
10308)
10309start &102
10310end &106
10311sat 2
10312eat 32
10313st 0
10314sf 1
10315si 0
10316tg (WTG
10317uid 15539,0
10318ps "ConnStartEndStrategy"
10319stg "STSignalDisplayStrategy"
10320f (Text
10321uid 15540,0
10322va (VaSet
10323isHidden 1
10324)
10325xt "134000,132000,140000,133000"
10326st "RS485_C_RE"
10327blo "134000,132800"
10328tm "WireNameMgr"
10329)
10330)
10331on &87
10332)
10333*330 (Wire
10334uid 15563,0
10335shape (OrthoPolyLine
10336uid 15564,0
10337va (VaSet
10338vasetType 3
10339)
10340xt "80750,148000,85000,148000"
10341pts [
10342"80750,148000"
10343"85000,148000"
10344]
10345)
10346start &186
10347end &83
10348ss 0
10349sat 32
10350eat 32
10351st 0
10352sf 1
10353si 0
10354tg (WTG
10355uid 15569,0
10356ps "ConnStartEndStrategy"
10357stg "STSignalDisplayStrategy"
10358f (Text
10359uid 15570,0
10360va (VaSet
10361isHidden 1
10362)
10363xt "83000,147000,89000,148000"
10364st "RS485_E_RE"
10365blo "83000,147800"
10366tm "WireNameMgr"
10367)
10368)
10369on &89
10370)
10371*331 (Wire
10372uid 15712,0
10373shape (OrthoPolyLine
10374uid 15713,0
10375va (VaSet
10376vasetType 3
10377lineWidth 2
10378)
10379xt "49000,137000,51250,137000"
10380pts [
10381"49000,137000"
10382"51250,137000"
10383]
10384)
10385start &127
10386end &179
10387sat 32
10388eat 32
10389sty 1
10390st 0
10391sf 1
10392si 0
10393tg (WTG
10394uid 15716,0
10395ps "ConnStartEndStrategy"
10396stg "STSignalDisplayStrategy"
10397f (Text
10398uid 15717,0
10399va (VaSet
10400isHidden 1
10401)
10402xt "51000,136000,58000,137000"
10403st "D_PLLLCK : (3:0)"
10404blo "51000,136800"
10405tm "WireNameMgr"
10406)
10407)
10408on &128
10409)
10410*332 (Wire
10411uid 15851,0
10412shape (OrthoPolyLine
10413uid 15852,0
10414va (VaSet
10415vasetType 3
10416lineWidth 2
10417)
10418xt "85000,88000,95000,90000"
10419pts [
10420"85000,90000"
10421"95000,88000"
10422]
10423)
10424start &225
10425end &129
10426ss 0
10427sat 32
10428eat 32
10429sty 1
10430st 0
10431sf 1
10432si 0
10433tg (WTG
10434uid 15855,0
10435ps "ConnStartEndStrategy"
10436stg "STSignalDisplayStrategy"
10437f (Text
10438uid 15856,0
10439va (VaSet
10440isHidden 1
10441)
10442xt "87000,89000,91900,90000"
10443st "TCS : (3:0)"
10444blo "87000,89800"
10445tm "WireNameMgr"
10446)
10447)
10448on &130
10449)
10450*333 (Wire
10451uid 16063,0
10452shape (OrthoPolyLine
10453uid 16064,0
10454va (VaSet
10455vasetType 3
10456lineWidth 2
10457)
10458xt "21000,113000,30000,113000"
10459pts [
10460"30000,113000"
10461"21000,113000"
10462]
10463)
10464start &134
10465end &131
10466sat 2
10467eat 32
10468sty 1
10469st 0
10470sf 1
10471si 0
10472tg (WTG
10473uid 16067,0
10474ps "ConnStartEndStrategy"
10475stg "STSignalDisplayStrategy"
10476f (Text
10477uid 16068,0
10478va (VaSet
10479isHidden 1
10480)
10481xt "24000,112000,30400,113000"
10482st "DSRCLK : (3:0)"
10483blo "24000,112800"
10484tm "WireNameMgr"
10485)
10486)
10487on &132
10488)
10489*334 (Wire
10490uid 16247,0
10491shape (OrthoPolyLine
10492uid 16248,0
10493va (VaSet
10494vasetType 3
10495)
10496xt "34000,113000,51250,113000"
10497pts [
10498"51250,113000"
10499"34000,113000"
10500]
10501)
10502start &166
10503end &134
10504sat 32
10505eat 1
10506st 0
10507sf 1
10508si 0
10509tg (WTG
10510uid 16251,0
10511ps "ConnStartEndStrategy"
10512stg "STSignalDisplayStrategy"
10513f (Text
10514uid 16252,0
10515va (VaSet
10516)
10517xt "35000,112000,37900,113000"
10518st "SRCLK"
10519blo "35000,112800"
10520tm "WireNameMgr"
10521)
10522)
10523on &133
10524)
10525*335 (Wire
10526uid 16538,0
10527shape (OrthoPolyLine
10528uid 16539,0
10529va (VaSet
10530vasetType 3
10531)
10532xt "80750,130000,92000,130000"
10533pts [
10534"80750,130000"
10535"92000,130000"
10536]
10537)
10538start &181
10539sat 32
10540eat 16
10541st 0
10542sf 1
10543si 0
10544tg (WTG
10545uid 16542,0
10546ps "ConnStartEndStrategy"
10547stg "STSignalDisplayStrategy"
10548f (Text
10549uid 16543,0
10550va (VaSet
10551)
10552xt "82000,129000,92000,130000"
10553st "alarm_refclk_too_high"
10554blo "82000,129800"
10555tm "WireNameMgr"
10556)
10557)
10558on &138
10559)
10560*336 (Wire
10561uid 16546,0
10562shape (OrthoPolyLine
10563uid 16547,0
10564va (VaSet
10565vasetType 3
10566)
10567xt "80750,131000,91000,131000"
10568pts [
10569"80750,131000"
10570"91000,131000"
10571]
10572)
10573start &182
10574sat 32
10575eat 16
10576st 0
10577sf 1
10578si 0
10579tg (WTG
10580uid 16550,0
10581ps "ConnStartEndStrategy"
10582stg "STSignalDisplayStrategy"
10583f (Text
10584uid 16551,0
10585va (VaSet
10586)
10587xt "82000,130000,91600,131000"
10588st "alarm_refclk_too_low"
10589blo "82000,130800"
10590tm "WireNameMgr"
10591)
10592)
10593on &139
10594)
10595*337 (Wire
10596uid 16576,0
10597shape (OrthoPolyLine
10598uid 16577,0
10599va (VaSet
10600vasetType 3
10601lineWidth 2
10602)
10603xt "80750,132000,92000,132000"
10604pts [
10605"80750,132000"
10606"92000,132000"
10607]
10608)
10609start &180
10610sat 32
10611eat 16
10612sty 1
10613st 0
10614sf 1
10615si 0
10616tg (WTG
10617uid 16580,0
10618ps "ConnStartEndStrategy"
10619stg "STSignalDisplayStrategy"
10620f (Text
10621uid 16581,0
10622va (VaSet
10623)
10624xt "82000,131000,91600,132000"
10625st "counter_result : (11:0)"
10626blo "82000,131800"
10627tm "WireNameMgr"
10628)
10629)
10630on &140
10631)
10632*338 (Wire
10633uid 17296,0
10634shape (OrthoPolyLine
10635uid 17297,0
10636va (VaSet
10637vasetType 3
10638)
10639xt "13000,71000,51250,71000"
10640pts [
10641"51250,71000"
10642"13000,71000"
10643]
10644)
10645start &183
10646end &34
10647sat 32
10648eat 1
10649st 0
10650sf 1
10651si 0
10652tg (WTG
10653uid 17300,0
10654ps "ConnStartEndStrategy"
10655stg "STSignalDisplayStrategy"
10656f (Text
10657uid 17301,0
10658va (VaSet
10659)
10660xt "14000,70000,18000,71000"
10661st "ADC_CLK"
10662blo "14000,70800"
10663tm "WireNameMgr"
10664)
10665)
10666on &198
10667)
10668*339 (Wire
10669uid 17407,0
10670shape (OrthoPolyLine
10671uid 17408,0
10672va (VaSet
10673vasetType 3
10674)
10675xt "98000,144000,100000,144000"
10676pts [
10677"98000,144000"
10678"100000,144000"
10679]
10680)
10681start &268
10682end &199
10683ss 0
10684sat 32
10685eat 32
10686st 0
10687sf 1
10688si 0
10689tg (WTG
10690uid 17411,0
10691ps "ConnStartEndStrategy"
10692stg "STSignalDisplayStrategy"
10693f (Text
10694uid 17412,0
10695va (VaSet
10696isHidden 1
10697)
10698xt "100000,143000,102900,144000"
10699st "TRG_V"
10700blo "100000,143800"
10701tm "WireNameMgr"
10702)
10703)
10704on &200
10705)
10706*340 (Wire
10707uid 17848,0
10708shape (OrthoPolyLine
10709uid 17849,0
10710va (VaSet
10711vasetType 3
10712lineWidth 2
10713)
10714xt "80750,106000,91000,106000"
10715pts [
10716"80750,106000"
10717"91000,106000"
10718]
10719)
10720start &189
10721sat 32
10722eat 16
10723sty 1
10724st 0
10725sf 1
10726si 0
10727tg (WTG
10728uid 17852,0
10729ps "ConnStartEndStrategy"
10730stg "STSignalDisplayStrategy"
10731f (Text
10732uid 17853,0
10733va (VaSet
10734)
10735xt "82000,105000,90400,106000"
10736st "w5300_state : (7:0)"
10737blo "82000,105800"
10738tm "WireNameMgr"
10739)
10740)
10741on &201
10742)
10743*341 (Wire
10744uid 17856,0
10745shape (OrthoPolyLine
10746uid 17857,0
10747va (VaSet
10748vasetType 3
10749lineWidth 2
10750)
10751xt "114000,118000,126000,118000"
10752pts [
10753"114000,118000"
10754"126000,118000"
10755]
10756)
10757end &102
10758sat 16
10759eat 1
10760sty 1
10761st 0
10762sf 1
10763si 0
10764tg (WTG
10765uid 17862,0
10766ps "ConnStartEndStrategy"
10767stg "STSignalDisplayStrategy"
10768f (Text
10769uid 17863,0
10770va (VaSet
10771)
10772xt "118000,117000,126400,118000"
10773st "w5300_state : (7:0)"
10774blo "118000,117800"
10775tm "WireNameMgr"
10776)
10777)
10778on &201
10779)
10780*342 (Wire
10781uid 18068,0
10782shape (OrthoPolyLine
10783uid 18069,0
10784va (VaSet
10785vasetType 3
10786)
10787xt "80750,107000,93000,107000"
10788pts [
10789"80750,107000"
10790"93000,107000"
10791]
10792)
10793start &190
10794sat 32
10795eat 16
10796st 0
10797sf 1
10798si 0
10799tg (WTG
10800uid 18072,0
10801ps "ConnStartEndStrategy"
10802stg "STSignalDisplayStrategy"
10803f (Text
10804uid 18073,0
10805va (VaSet
10806)
10807xt "82000,106000,92400,107000"
10808st "debug_data_ram_empty"
10809blo "82000,106800"
10810tm "WireNameMgr"
10811)
10812)
10813on &202
10814)
10815*343 (Wire
10816uid 18076,0
10817shape (OrthoPolyLine
10818uid 18077,0
10819va (VaSet
10820vasetType 3
10821)
10822xt "80750,108000,91000,108000"
10823pts [
10824"80750,108000"
10825"91000,108000"
10826]
10827)
10828start &191
10829sat 32
10830eat 16
10831st 0
10832sf 1
10833si 0
10834tg (WTG
10835uid 18080,0
10836ps "ConnStartEndStrategy"
10837stg "STSignalDisplayStrategy"
10838f (Text
10839uid 18081,0
10840va (VaSet
10841)
10842xt "82000,107000,89500,108000"
10843st "debug_data_valid"
10844blo "82000,107800"
10845tm "WireNameMgr"
10846)
10847)
10848on &203
10849)
10850*344 (Wire
10851uid 18207,0
10852shape (OrthoPolyLine
10853uid 18208,0
10854va (VaSet
10855vasetType 3
10856lineWidth 2
10857)
10858xt "80750,105000,94000,105000"
10859pts [
10860"80750,105000"
10861"94000,105000"
10862]
10863)
10864start &192
10865sat 32
10866eat 16
10867sty 1
10868st 0
10869sf 1
10870si 0
10871tg (WTG
10872uid 18211,0
10873ps "ConnStartEndStrategy"
10874stg "STSignalDisplayStrategy"
10875f (Text
10876uid 18212,0
10877va (VaSet
10878)
10879xt "82000,104000,93400,105000"
10880st "mem_manager_state : (3:0)"
10881blo "82000,104800"
10882tm "WireNameMgr"
10883)
10884)
10885on &204
10886)
10887*345 (Wire
10888uid 18328,0
10889shape (OrthoPolyLine
10890uid 18329,0
10891va (VaSet
10892vasetType 3
10893lineWidth 2
10894)
10895xt "80750,109000,90000,109000"
10896pts [
10897"80750,109000"
10898"90000,109000"
10899]
10900)
10901start &193
10902sat 32
10903eat 16
10904sty 1
10905st 0
10906sf 1
10907si 0
10908tg (WTG
10909uid 18332,0
10910ps "ConnStartEndStrategy"
10911stg "STSignalDisplayStrategy"
10912f (Text
10913uid 18333,0
10914va (VaSet
10915)
10916xt "82000,108000,88900,109000"
10917st "DG_state : (7:0)"
10918blo "82000,108800"
10919tm "WireNameMgr"
10920)
10921)
10922on &205
10923)
10924*346 (Wire
10925uid 18336,0
10926shape (OrthoPolyLine
10927uid 18337,0
10928va (VaSet
10929vasetType 3
10930lineWidth 2
10931)
10932xt "111000,112000,121000,112000"
10933pts [
10934"111000,112000"
10935"121000,112000"
10936]
10937)
10938sat 16
10939eat 16
10940sty 1
10941st 0
10942sf 1
10943si 0
10944tg (WTG
10945uid 18342,0
10946ps "ConnStartEndStrategy"
10947stg "STSignalDisplayStrategy"
10948f (Text
10949uid 18343,0
10950va (VaSet
10951)
10952xt "113000,111000,119900,112000"
10953st "DG_state : (7:0)"
10954blo "113000,111800"
10955tm "WireNameMgr"
10956)
10957)
10958on &205
10959)
10960*347 (Wire
10961uid 18352,0
10962shape (OrthoPolyLine
10963uid 18353,0
10964va (VaSet
10965vasetType 3
10966)
10967xt "109000,114000,119000,114000"
10968pts [
10969"109000,114000"
10970"119000,114000"
10971]
10972)
10973sat 16
10974eat 16
10975st 0
10976sf 1
10977si 0
10978tg (WTG
10979uid 18358,0
10980ps "ConnStartEndStrategy"
10981stg "STSignalDisplayStrategy"
10982f (Text
10983uid 18359,0
10984va (VaSet
10985)
10986xt "111000,113000,118500,114000"
10987st "debug_data_valid"
10988blo "111000,113800"
10989tm "WireNameMgr"
10990)
10991)
10992on &203
10993)
10994*348 (Wire
10995uid 18360,0
10996shape (OrthoPolyLine
10997uid 18361,0
10998va (VaSet
10999vasetType 3
11000)
11001xt "113000,122000,126000,122000"
11002pts [
11003"113000,122000"
11004"126000,122000"
11005]
11006)
11007end &102
11008sat 16
11009eat 1
11010st 0
11011sf 1
11012si 0
11013tg (WTG
11014uid 18366,0
11015ps "ConnStartEndStrategy"
11016stg "STSignalDisplayStrategy"
11017f (Text
11018uid 18367,0
11019va (VaSet
11020)
11021xt "115000,121000,126400,122000"
11022st "mem_manager_state : (3:0)"
11023blo "115000,121800"
11024tm "WireNameMgr"
11025)
11026)
11027on &204
11028)
11029*349 (Wire
11030uid 18477,0
11031shape (OrthoPolyLine
11032uid 18478,0
11033va (VaSet
11034vasetType 3
11035lineWidth 2
11036)
11037xt "80750,151000,95000,151000"
11038pts [
11039"80750,151000"
11040"95000,151000"
11041]
11042)
11043start &194
11044sat 32
11045eat 16
11046sty 1
11047st 0
11048sf 1
11049si 0
11050tg (WTG
11051uid 18481,0
11052ps "ConnStartEndStrategy"
11053stg "STSignalDisplayStrategy"
11054f (Text
11055uid 18482,0
11056va (VaSet
11057)
11058xt "82000,150000,93900,151000"
11059st "socket_tx_free_out : (16:0)"
11060blo "82000,150800"
11061tm "WireNameMgr"
11062)
11063)
11064on &206
11065)
11066*350 (Wire
11067uid 18808,0
11068shape (OrthoPolyLine
11069uid 18809,0
11070va (VaSet
11071vasetType 3
11072lineWidth 2
11073)
11074xt "132000,122000,137000,122000"
11075pts [
11076"132000,122000"
11077"137000,122000"
11078]
11079)
11080start &102
11081end &207
11082sat 2
11083eat 32
11084sty 1
11085st 0
11086sf 1
11087si 0
11088tg (WTG
11089uid 18812,0
11090ps "ConnStartEndStrategy"
11091stg "STSignalDisplayStrategy"
11092f (Text
11093uid 18813,0
11094va (VaSet
11095isHidden 1
11096)
11097xt "134000,121000,139200,122000"
11098st "W_T : (3:0)"
11099blo "134000,121800"
11100tm "WireNameMgr"
11101)
11102)
11103on &208
11104)
11105*351 (Wire
11106uid 18923,0
11107shape (OrthoPolyLine
11108uid 18924,0
11109va (VaSet
11110vasetType 3
11111)
11112xt "113000,120000,126000,120000"
11113pts [
11114"113000,120000"
11115"126000,120000"
11116]
11117)
11118end &102
11119sat 16
11120eat 1
11121st 0
11122sf 1
11123si 0
11124tg (WTG
11125uid 18929,0
11126ps "ConnStartEndStrategy"
11127stg "STSignalDisplayStrategy"
11128f (Text
11129uid 18930,0
11130va (VaSet
11131)
11132xt "114000,119000,125900,120000"
11133st "socket_tx_free_out : (16:0)"
11134blo "114000,119800"
11135tm "WireNameMgr"
11136)
11137)
11138on &206
11139)
11140*352 (Wire
11141uid 19161,0
11142shape (OrthoPolyLine
11143uid 19162,0
11144va (VaSet
11145vasetType 3
11146)
11147xt "116000,123000,126000,123000"
11148pts [
11149"116000,123000"
11150"126000,123000"
11151]
11152)
11153end &102
11154sat 16
11155eat 1
11156st 0
11157sf 1
11158si 0
11159tg (WTG
11160uid 19167,0
11161ps "ConnStartEndStrategy"
11162stg "STSignalDisplayStrategy"
11163f (Text
11164uid 19168,0
11165va (VaSet
11166)
11167xt "118000,122000,120900,123000"
11168st "TRG_V"
11169blo "118000,122800"
11170tm "WireNameMgr"
11171)
11172)
11173on &200
11174)
11175*353 (Wire
11176uid 19169,0
11177shape (OrthoPolyLine
11178uid 19170,0
11179va (VaSet
11180vasetType 3
11181)
11182xt "116000,124000,126000,124000"
11183pts [
11184"116000,124000"
11185"126000,124000"
11186]
11187)
11188end &102
11189sat 16
11190eat 1
11191st 0
11192sf 1
11193si 0
11194tg (WTG
11195uid 19175,0
11196ps "ConnStartEndStrategy"
11197stg "STSignalDisplayStrategy"
11198f (Text
11199uid 19176,0
11200va (VaSet
11201)
11202xt "118000,123000,128400,124000"
11203st "debug_data_ram_empty"
11204blo "118000,123800"
11205tm "WireNameMgr"
11206)
11207)
11208on &202
11209)
11210*354 (Wire
11211uid 19533,0
11212shape (OrthoPolyLine
11213uid 19534,0
11214va (VaSet
11215vasetType 3
11216)
11217xt "80750,85000,82000,87000"
11218pts [
11219"80750,87000"
11220"82000,87000"
11221"82000,85000"
11222]
11223)
11224start &169
11225end &210
11226sat 32
11227eat 32
11228st 0
11229sf 1
11230si 0
11231tg (WTG
11232uid 19535,0
11233ps "ConnStartEndStrategy"
11234stg "STSignalDisplayStrategy"
11235f (Text
11236uid 19536,0
11237va (VaSet
11238)
11239xt "82750,86000,86150,87000"
11240st "dac_cs1"
11241blo "82750,86800"
11242tm "WireNameMgr"
11243)
11244)
11245on &261
11246)
11247*355 (Wire
11248uid 19539,0
11249shape (OrthoPolyLine
11250uid 19540,0
11251va (VaSet
11252vasetType 3
11253)
11254xt "80750,89000,82000,90000"
11255pts [
11256"80750,89000"
11257"82000,89000"
11258"82000,90000"
11259]
11260)
11261start &170
11262end &223
11263sat 32
11264eat 32
11265st 0
11266sf 1
11267si 0
11268tg (WTG
11269uid 19541,0
11270ps "ConnStartEndStrategy"
11271stg "STSignalDisplayStrategy"
11272f (Text
11273uid 19542,0
11274va (VaSet
11275)
11276xt "82750,88000,89750,89000"
11277st "sensor_cs : (3:0)"
11278blo "82750,88800"
11279tm "WireNameMgr"
11280)
11281)
11282on &262
11283)
11284*356 (Wire
11285uid 19545,0
11286shape (OrthoPolyLine
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12226tm "WireNameMgr"
12227)
12228)
12229)
12230defaultBundle (Bundle
12231shape (OrthoPolyLine
12232va (VaSet
12233vasetType 3
12234lineColor "32768,0,0"
12235lineWidth 2
12236)
12237pts [
12238"0,0"
12239"0,0"
12240]
12241)
12242ss 0
12243es 0
12244sat 32
12245eat 32
12246textGroup (BiTextGroup
12247ps "ConnStartEndStrategy"
12248stg "VerticalLayoutStrategy"
12249first (Text
12250va (VaSet
12251)
12252xt "0,0,3000,1000"
12253st "bundle0"
12254blo "0,800"
12255tm "BundleNameMgr"
12256)
12257second (MLText
12258va (VaSet
12259)
12260xt "0,1000,1000,2000"
12261st "()"
12262tm "BundleContentsMgr"
12263)
12264)
12265bundleNet &0
12266)
12267defaultPortMapFrame (PortMapFrame
12268ps "PortMapFrameStrategy"
12269shape (RectFrame
12270va (VaSet
12271vasetType 1
12272fg "65535,65535,65535"
12273lineColor "0,0,32768"
12274lineWidth 2
12275)
12276xt "0,0,10000,12000"
12277)
12278portMapText (BiTextGroup
12279ps "BottomRightOffsetStrategy"
12280stg "VerticalLayoutStrategy"
12281first (MLText
12282va (VaSet
12283)
12284)
12285second (MLText
12286va (VaSet
12287)
12288tm "PortMapTextMgr"
12289)
12290)
12291)
12292defaultGenFrame (Frame
12293shape (RectFrame
12294va (VaSet
12295vasetType 1
12296fg "65535,65535,65535"
12297lineColor "26368,26368,26368"
12298lineStyle 2
12299lineWidth 2
12300)
12301xt "0,0,20000,20000"
12302)
12303title (TextAssociate
12304ps "TopLeftStrategy"
12305text (MLText
12306va (VaSet
12307)
12308xt "0,-1100,12600,-100"
12309st "g0: FOR i IN 0 TO n GENERATE"
12310tm "FrameTitleTextMgr"
12311)
12312)
12313seqNum (FrameSequenceNumber
12314ps "TopLeftStrategy"
12315shape (Rectangle
12316va (VaSet
12317vasetType 1
12318fg "65535,65535,65535"
12319)
12320xt "50,50,1250,1450"
12321)
12322num (Text
12323va (VaSet
12324)
12325xt "250,250,1050,1250"
12326st "1"
12327blo "250,1050"
12328tm "FrameSeqNumMgr"
12329)
12330)
12331decls (MlTextGroup
12332ps "BottomRightOffsetStrategy"
12333stg "VerticalLayoutStrategy"
12334textVec [
12335*386 (Text
12336va (VaSet
12337font "Arial,8,1"
12338)
12339xt "14100,20000,22000,21000"
12340st "Frame Declarations"
12341blo "14100,20800"
12342)
12343*387 (MLText
12344va (VaSet
12345)
12346xt "14100,21000,14100,21000"
12347tm "BdFrameDeclTextMgr"
12348)
12349]
12350)
12351)
12352defaultBlockFrame (Frame
12353shape (RectFrame
12354va (VaSet
12355vasetType 1
12356fg "65535,65535,65535"
12357lineColor "26368,26368,26368"
12358lineStyle 1
12359lineWidth 2
12360)
12361xt "0,0,20000,20000"
12362)
12363title (TextAssociate
12364ps "TopLeftStrategy"
12365text (MLText
12366va (VaSet
12367)
12368xt "0,-1100,7400,-100"
12369st "b0: BLOCK (guard)"
12370tm "FrameTitleTextMgr"
12371)
12372)
12373seqNum (FrameSequenceNumber
12374ps "TopLeftStrategy"
12375shape (Rectangle
12376va (VaSet
12377vasetType 1
12378fg "65535,65535,65535"
12379)
12380xt "50,50,1250,1450"
12381)
12382num (Text
12383va (VaSet
12384)
12385xt "250,250,1050,1250"
12386st "1"
12387blo "250,1050"
12388tm "FrameSeqNumMgr"
12389)
12390)
12391decls (MlTextGroup
12392ps "BottomRightOffsetStrategy"
12393stg "VerticalLayoutStrategy"
12394textVec [
12395*388 (Text
12396va (VaSet
12397font "Arial,8,1"
12398)
12399xt "14100,20000,22000,21000"
12400st "Frame Declarations"
12401blo "14100,20800"
12402)
12403*389 (MLText
12404va (VaSet
12405)
12406xt "14100,21000,14100,21000"
12407tm "BdFrameDeclTextMgr"
12408)
12409]
12410)
12411style 3
12412)
12413defaultSaCptPort (CptPort
12414ps "OnEdgeStrategy"
12415shape (Triangle
12416ro 90
12417va (VaSet
12418vasetType 1
12419fg "0,65535,0"
12420)
12421xt "0,0,750,750"
12422)
12423tg (CPTG
12424ps "CptPortTextPlaceStrategy"
12425stg "VerticalLayoutStrategy"
12426f (Text
12427va (VaSet
12428)
12429xt "0,750,1800,1750"
12430st "Port"
12431blo "0,1550"
12432)
12433)
12434thePort (LogicalPort
12435decl (Decl
12436n "Port"
12437t ""
12438o 0
12439)
12440)
12441)
12442defaultSaCptPortBuffer (CptPort
12443ps "OnEdgeStrategy"
12444shape (Diamond
12445va (VaSet
12446vasetType 1
12447fg "65535,65535,65535"
12448)
12449xt "0,0,750,750"
12450)
12451tg (CPTG
12452ps "CptPortTextPlaceStrategy"
12453stg "VerticalLayoutStrategy"
12454f (Text
12455va (VaSet
12456)
12457xt "0,750,1800,1750"
12458st "Port"
12459blo "0,1550"
12460)
12461)
12462thePort (LogicalPort
12463m 3
12464decl (Decl
12465n "Port"
12466t ""
12467o 0
12468)
12469)
12470)
12471defaultDeclText (MLText
12472va (VaSet
12473font "Courier New,8,0"
12474)
12475)
12476archDeclarativeBlock (BdArchDeclBlock
12477uid 1,0
12478stg "BdArchDeclBlockLS"
12479declLabel (Text
12480uid 2,0
12481va (VaSet
12482font "Arial,8,1"
12483)
12484xt "37000,1800,42400,2800"
12485st "Declarations"
12486blo "37000,2600"
12487)
12488portLabel (Text
12489uid 3,0
12490va (VaSet
12491font "Arial,8,1"
12492)
12493xt "37000,2800,39700,3800"
12494st "Ports:"
12495blo "37000,3600"
12496)
12497preUserLabel (Text
12498uid 4,0
12499va (VaSet
12500isHidden 1
12501font "Arial,8,1"
12502)
12503xt "37000,1800,40800,2800"
12504st "Pre User:"
12505blo "37000,2600"
12506)
12507preUserText (MLText
12508uid 5,0
12509va (VaSet
12510isHidden 1
12511font "Courier New,8,0"
12512)
12513xt "37000,1800,37000,1800"
12514tm "BdDeclarativeTextMgr"
12515)
12516diagSignalLabel (Text
12517uid 6,0
12518va (VaSet
12519font "Arial,8,1"
12520)
12521xt "37000,45400,44100,46400"
12522st "Diagram Signals:"
12523blo "37000,46200"
12524)
12525postUserLabel (Text
12526uid 7,0
12527va (VaSet
12528isHidden 1
12529font "Arial,8,1"
12530)
12531xt "37000,1800,41700,2800"
12532st "Post User:"
12533blo "37000,2600"
12534)
12535postUserText (MLText
12536uid 8,0
12537va (VaSet
12538isHidden 1
12539font "Courier New,8,0"
12540)
12541xt "37000,1800,37000,1800"
12542tm "BdDeclarativeTextMgr"
12543)
12544)
12545commonDM (CommonDM
12546ldm (LogicalDM
12547suid 249,0
12548usingSuid 1
12549emptyRow *390 (LEmptyRow
12550)
12551uid 54,0
12552optionalChildren [
12553*391 (RefLabelRowHdr
12554)
12555*392 (TitleRowHdr
12556)
12557*393 (FilterRowHdr
12558)
12559*394 (RefLabelColHdr
12560tm "RefLabelColHdrMgr"
12561)
12562*395 (RowExpandColHdr
12563tm "RowExpandColHdrMgr"
12564)
12565*396 (GroupColHdr
12566tm "GroupColHdrMgr"
12567)
12568*397 (NameColHdr
12569tm "BlockDiagramNameColHdrMgr"
12570)
12571*398 (ModeColHdr
12572tm "BlockDiagramModeColHdrMgr"
12573)
12574*399 (TypeColHdr
12575tm "BlockDiagramTypeColHdrMgr"
12576)
12577*400 (BoundsColHdr
12578tm "BlockDiagramBoundsColHdrMgr"
12579)
12580*401 (InitColHdr
12581tm "BlockDiagramInitColHdrMgr"
12582)
12583*402 (EolColHdr
12584tm "BlockDiagramEolColHdrMgr"
12585)
12586*403 (LeafLogPort
12587port (LogicalPort
12588m 4
12589decl (Decl
12590n "board_id"
12591t "std_logic_vector"
12592b "(3 downto 0)"
12593preAdd 0
12594posAdd 0
12595o 60
12596suid 5,0
12597)
12598)
12599uid 327,0
12600)
12601*404 (LeafLogPort
12602port (LogicalPort
12603m 4
12604decl (Decl
12605n "crate_id"
12606t "std_logic_vector"
12607b "(1 downto 0)"
12608o 62
12609suid 6,0
12610)
12611)
12612uid 329,0
12613)
12614*405 (LeafLogPort
12615port (LogicalPort
12616m 4
12617decl (Decl
12618n "adc_data_array"
12619t "adc_data_array_type"
12620o 57
12621suid 29,0
12622)
12623)
12624uid 1491,0
12625)
12626*406 (LeafLogPort
12627port (LogicalPort
12628m 1
12629decl (Decl
12630n "RSRLOAD"
12631t "std_logic"
12632o 40
12633suid 57,0
12634i "'0'"
12635)
12636)
12637uid 2435,0
12638)
12639*407 (LeafLogPort
12640port (LogicalPort
12641m 1
12642decl (Decl
12643n "DAC_CS"
12644t "std_logic"
12645o 22
12646suid 66,0
12647)
12648)
12649uid 3039,0
12650)
12651*408 (LeafLogPort
12652port (LogicalPort
12653decl (Decl
12654n "X_50M"
12655t "STD_LOGIC"
12656preAdd 0
12657posAdd 0
12658o 17
12659suid 67,0
12660)
12661)
12662uid 3276,0
12663)
12664*409 (LeafLogPort
12665port (LogicalPort
12666decl (Decl
12667n "TRG"
12668t "STD_LOGIC"
12669o 15
12670suid 68,0
12671)
12672)
12673uid 3278,0
12674)
12675*410 (LeafLogPort
12676port (LogicalPort
12677m 1
12678decl (Decl
12679n "A_CLK"
12680t "std_logic_vector"
12681b "(3 downto 0)"
12682o 21
12683suid 71,0
12684)
12685)
12686uid 3280,0
12687)
12688*411 (LeafLogPort
12689port (LogicalPort
12690m 1
12691decl (Decl
12692n "OE_ADC"
12693t "STD_LOGIC"
12694preAdd 0
12695posAdd 0
12696o 32
12697suid 73,0
12698)
12699)
12700uid 3382,0
12701)
12702*412 (LeafLogPort
12703port (LogicalPort
12704decl (Decl
12705n "A_OTR"
12706t "std_logic_vector"
12707b "(3 DOWNTO 0)"
12708o 5
12709suid 74,0
12710)
12711)
12712uid 3384,0
12713)
12714*413 (LeafLogPort
12715port (LogicalPort
12716decl (Decl
12717n "A0_D"
12718t "std_logic_vector"
12719b "(11 DOWNTO 0)"
12720o 1
12721suid 79,0
12722)
12723)
12724uid 3386,0
12725)
12726*414 (LeafLogPort
12727port (LogicalPort
12728decl (Decl
12729n "A1_D"
12730t "std_logic_vector"
12731b "(11 DOWNTO 0)"
12732o 2
12733suid 80,0
12734)
12735)
12736uid 3388,0
12737)
12738*415 (LeafLogPort
12739port (LogicalPort
12740decl (Decl
12741n "A2_D"
12742t "std_logic_vector"
12743b "(11 DOWNTO 0)"
12744o 3
12745suid 81,0
12746)
12747)
12748uid 3390,0
12749)
12750*416 (LeafLogPort
12751port (LogicalPort
12752decl (Decl
12753n "A3_D"
12754t "std_logic_vector"
12755b "(11 DOWNTO 0)"
12756o 4
12757suid 82,0
12758)
12759)
12760uid 3392,0
12761)
12762*417 (LeafLogPort
12763port (LogicalPort
12764decl (Decl
12765n "D0_SROUT"
12766t "std_logic"
12767o 6
12768suid 91,0
12769)
12770)
12771uid 3524,0
12772)
12773*418 (LeafLogPort
12774port (LogicalPort
12775decl (Decl
12776n "D1_SROUT"
12777t "std_logic"
12778o 7
12779suid 92,0
12780)
12781)
12782uid 3526,0
12783)
12784*419 (LeafLogPort
12785port (LogicalPort
12786decl (Decl
12787n "D2_SROUT"
12788t "std_logic"
12789o 8
12790suid 93,0
12791)
12792)
12793uid 3528,0
12794)
12795*420 (LeafLogPort
12796port (LogicalPort
12797decl (Decl
12798n "D3_SROUT"
12799t "std_logic"
12800o 9
12801suid 94,0
12802)
12803)
12804uid 3530,0
12805)
12806*421 (LeafLogPort
12807port (LogicalPort
12808m 1
12809decl (Decl
12810n "D_A"
12811t "std_logic_vector"
12812b "(3 DOWNTO 0)"
12813o 26
12814suid 95,0
12815i "(others => '0')"
12816)
12817)
12818uid 3532,0
12819)
12820*422 (LeafLogPort
12821port (LogicalPort
12822m 1
12823decl (Decl
12824n "DWRITE"
12825t "std_logic"
12826o 25
12827suid 96,0
12828i "'0'"
12829)
12830)
12831uid 3534,0
12832)
12833*423 (LeafLogPort
12834port (LogicalPort
12835m 1
12836decl (Decl
12837n "S_CLK"
12838t "std_logic"
12839o 42
12840suid 105,0
12841)
12842)
12843uid 3654,0
12844)
12845*424 (LeafLogPort
12846port (LogicalPort
12847m 1
12848decl (Decl
12849n "W_A"
12850t "std_logic_vector"
12851b "(9 DOWNTO 0)"
12852o 45
12853suid 106,0
12854)
12855)
12856uid 3656,0
12857)
12858*425 (LeafLogPort
12859port (LogicalPort
12860m 2
12861decl (Decl
12862n "W_D"
12863t "std_logic_vector"
12864b "(15 DOWNTO 0)"
12865o 52
12866suid 107,0
12867)
12868)
12869uid 3658,0
12870)
12871*426 (LeafLogPort
12872port (LogicalPort
12873m 1
12874decl (Decl
12875n "W_RES"
12876t "std_logic"
12877o 48
12878suid 108,0
12879i "'1'"
12880)
12881)
12882uid 3660,0
12883)
12884*427 (LeafLogPort
12885port (LogicalPort
12886m 1
12887decl (Decl
12888n "W_RD"
12889t "std_logic"
12890o 47
12891suid 109,0
12892i "'1'"
12893)
12894)
12895uid 3662,0
12896)
12897*428 (LeafLogPort
12898port (LogicalPort
12899m 1
12900decl (Decl
12901n "W_WR"
12902t "std_logic"
12903o 50
12904suid 110,0
12905i "'1'"
12906)
12907)
12908uid 3664,0
12909)
12910*429 (LeafLogPort
12911port (LogicalPort
12912decl (Decl
12913n "W_INT"
12914t "std_logic"
12915o 16
12916suid 111,0
12917)
12918)
12919uid 3666,0
12920)
12921*430 (LeafLogPort
12922port (LogicalPort
12923m 1
12924decl (Decl
12925n "W_CS"
12926t "std_logic"
12927o 46
12928suid 112,0
12929i "'1'"
12930)
12931)
12932uid 3668,0
12933)
12934*431 (LeafLogPort
12935port (LogicalPort
12936m 1
12937decl (Decl
12938n "MOSI"
12939t "std_logic"
12940o 31
12941suid 113,0
12942i "'0'"
12943)
12944)
12945uid 3696,0
12946)
12947*432 (LeafLogPort
12948port (LogicalPort
12949m 2
12950decl (Decl
12951n "MISO"
12952t "std_logic"
12953preAdd 0
12954posAdd 0
12955o 51
12956suid 114,0
12957)
12958)
12959uid 3698,0
12960)
12961*433 (LeafLogPort
12962port (LogicalPort
12963m 1
12964decl (Decl
12965n "RS485_C_RE"
12966t "std_logic"
12967o 36
12968suid 127,0
12969)
12970)
12971uid 3888,0
12972)
12973*434 (LeafLogPort
12974port (LogicalPort
12975m 1
12976decl (Decl
12977n "RS485_C_DE"
12978t "std_logic"
12979o 34
12980suid 128,0
12981)
12982)
12983uid 3890,0
12984)
12985*435 (LeafLogPort
12986port (LogicalPort
12987m 1
12988decl (Decl
12989n "RS485_E_RE"
12990t "std_logic"
12991o 39
12992suid 129,0
12993)
12994)
12995uid 3892,0
12996)
12997*436 (LeafLogPort
12998port (LogicalPort
12999m 1
13000decl (Decl
13001n "RS485_E_DE"
13002t "std_logic"
13003o 37
13004suid 130,0
13005)
13006)
13007uid 3894,0
13008)
13009*437 (LeafLogPort
13010port (LogicalPort
13011m 1
13012decl (Decl
13013n "DENABLE"
13014t "std_logic"
13015o 23
13016suid 131,0
13017i "'0'"
13018)
13019)
13020uid 3896,0
13021)
13022*438 (LeafLogPort
13023port (LogicalPort
13024m 1
13025decl (Decl
13026n "EE_CS"
13027t "std_logic"
13028o 29
13029suid 133,0
13030)
13031)
13032uid 3900,0
13033)
13034*439 (LeafLogPort
13035port (LogicalPort
13036m 1
13037decl (Decl
13038n "D_T"
13039t "std_logic_vector"
13040b "(7 DOWNTO 0)"
13041o 27
13042suid 141,0
13043i "(OTHERS => '0')"
13044)
13045)
13046uid 5322,0
13047)
13048*440 (LeafLogPort
13049port (LogicalPort
13050m 1
13051decl (Decl
13052n "D_T2"
13053t "std_logic_vector"
13054b "(1 DOWNTO 0)"
13055o 28
13056suid 154,0
13057i "(others => '0')"
13058)
13059)
13060uid 6872,0
13061scheme 0
13062)
13063*441 (LeafLogPort
13064port (LogicalPort
13065m 1
13066decl (Decl
13067n "A1_T"
13068t "std_logic_vector"
13069b "(7 DOWNTO 0)"
13070o 19
13071suid 155,0
13072i "(OTHERS => '0')"
13073)
13074)
13075uid 7134,0
13076scheme 0
13077)
13078*442 (LeafLogPort
13079port (LogicalPort
13080m 4
13081decl (Decl
13082n "CLK_50"
13083t "std_logic"
13084o 54
13085suid 163,0
13086)
13087)
13088uid 9516,0
13089)
13090*443 (LeafLogPort
13091port (LogicalPort
13092m 1
13093decl (Decl
13094n "A0_T"
13095t "std_logic_vector"
13096b "(7 DOWNTO 0)"
13097o 18
13098suid 166,0
13099i "(others => '0')"
13100)
13101)
13102uid 10294,0
13103scheme 0
13104)
13105*444 (LeafLogPort
13106port (LogicalPort
13107m 1
13108decl (Decl
13109n "RS485_C_DO"
13110t "std_logic"
13111o 35
13112suid 198,0
13113)
13114)
13115uid 11086,0
13116scheme 0
13117)
13118*445 (LeafLogPort
13119port (LogicalPort
13120decl (Decl
13121n "RS485_E_DI"
13122t "std_logic"
13123o 14
13124suid 200,0
13125)
13126)
13127uid 11504,0
13128scheme 0
13129)
13130*446 (LeafLogPort
13131port (LogicalPort
13132m 1
13133decl (Decl
13134n "RS485_E_DO"
13135t "std_logic"
13136o 38
13137suid 201,0
13138)
13139)
13140uid 11506,0
13141scheme 0
13142)
13143*447 (LeafLogPort
13144port (LogicalPort
13145m 1
13146decl (Decl
13147n "SRIN"
13148t "std_logic"
13149o 41
13150suid 203,0
13151i "'0'"
13152)
13153)
13154uid 12336,0
13155)
13156*448 (LeafLogPort
13157port (LogicalPort
13158m 1
13159decl (Decl
13160n "AMBER_LED"
13161t "std_logic"
13162o 20
13163suid 207,0
13164)
13165)
13166uid 12768,0
13167)
13168*449 (LeafLogPort
13169port (LogicalPort
13170m 1
13171decl (Decl
13172n "GREEN_LED"
13173t "std_logic"
13174o 30
13175suid 208,0
13176)
13177)
13178uid 12770,0
13179)
13180*450 (LeafLogPort
13181port (LogicalPort
13182m 1
13183decl (Decl
13184n "RED_LED"
13185t "std_logic"
13186o 33
13187suid 209,0
13188)
13189)
13190uid 12772,0
13191)
13192*451 (LeafLogPort
13193port (LogicalPort
13194decl (Decl
13195n "LINE"
13196t "std_logic_vector"
13197b "( 5 DOWNTO 0 )"
13198o 12
13199suid 210,0
13200)
13201)
13202uid 13514,0
13203scheme 0
13204)
13205*452 (LeafLogPort
13206port (LogicalPort
13207decl (Decl
13208n "REFCLK"
13209t "std_logic"
13210o 13
13211suid 211,0
13212)
13213)
13214uid 13626,0
13215scheme 0
13216)
13217*453 (LeafLogPort
13218port (LogicalPort
13219decl (Decl
13220n "D_T_in"
13221t "std_logic_vector"
13222b "(1 DOWNTO 0)"
13223o 11
13224suid 213,0
13225)
13226)
13227uid 14320,0
13228scheme 0
13229)
13230*454 (LeafLogPort
13231port (LogicalPort
13232m 4
13233decl (Decl
13234n "led"
13235t "std_logic_vector"
13236b "(7 DOWNTO 0)"
13237posAdd 0
13238o 65
13239suid 215,0
13240i "(OTHERS => '0')"
13241)
13242)
13243uid 15181,0
13244)
13245*455 (LeafLogPort
13246port (LogicalPort
13247decl (Decl
13248n "D_PLLLCK"
13249t "std_logic_vector"
13250b "(3 DOWNTO 0)"
13251o 10
13252suid 216,0
13253)
13254)
13255uid 15704,0
13256scheme 0
13257)
13258*456 (LeafLogPort
13259port (LogicalPort
13260m 1
13261decl (Decl
13262n "TCS"
13263t "std_logic_vector"
13264b "(3 DOWNTO 0)"
13265o 43
13266suid 217,0
13267)
13268)
13269uid 15843,0
13270scheme 0
13271)
13272*457 (LeafLogPort
13273port (LogicalPort
13274m 1
13275decl (Decl
13276n "DSRCLK"
13277t "std_logic_vector"
13278b "(3 DOWNTO 0)"
13279o 24
13280suid 222,0
13281i "(others => '0')"
13282)
13283)
13284uid 16055,0
13285scheme 0
13286)
13287*458 (LeafLogPort
13288port (LogicalPort
13289m 4
13290decl (Decl
13291n "SRCLK"
13292t "std_logic"
13293o 56
13294suid 225,0
13295i "'0'"
13296)
13297)
13298uid 16253,0
13299)
13300*459 (LeafLogPort
13301port (LogicalPort
13302m 4
13303decl (Decl
13304n "alarm_refclk_too_high"
13305t "std_logic"
13306o 58
13307suid 226,0
13308i "'0'"
13309)
13310)
13311uid 16582,0
13312)
13313*460 (LeafLogPort
13314port (LogicalPort
13315m 4
13316decl (Decl
13317n "alarm_refclk_too_low"
13318t "std_logic"
13319o 59
13320suid 227,0
13321i "'0'"
13322)
13323)
13324uid 16584,0
13325)
13326*461 (LeafLogPort
13327port (LogicalPort
13328m 4
13329decl (Decl
13330n "counter_result"
13331t "std_logic_vector"
13332b "(11 downto 0)"
13333o 61
13334suid 230,0
13335i "(others => '0')"
13336)
13337)
13338uid 16586,0
13339)
13340*462 (LeafLogPort
13341port (LogicalPort
13342lang 2
13343m 4
13344decl (Decl
13345n "ADC_CLK"
13346t "std_logic"
13347o 53
13348suid 231,0
13349)
13350)
13351uid 17310,0
13352)
13353*463 (LeafLogPort
13354port (LogicalPort
13355lang 2
13356m 1
13357decl (Decl
13358n "TRG_V"
13359t "std_logic"
13360o 44
13361suid 232,0
13362i "'0'"
13363)
13364)
13365uid 17399,0
13366scheme 0
13367)
13368*464 (LeafLogPort
13369port (LogicalPort
13370m 4
13371decl (Decl
13372n "w5300_state"
13373t "std_logic_vector"
13374b "(7 DOWNTO 0)"
13375eolc "-- state is encoded here ... useful for debugging."
13376posAdd 0
13377o 68
13378suid 233,0
13379)
13380)
13381uid 17854,0
13382)
13383*465 (LeafLogPort
13384port (LogicalPort
13385m 4
13386decl (Decl
13387n "debug_data_ram_empty"
13388t "std_logic"
13389o 63
13390suid 234,0
13391)
13392)
13393uid 18082,0
13394)
13395*466 (LeafLogPort
13396port (LogicalPort
13397m 4
13398decl (Decl
13399n "debug_data_valid"
13400t "std_logic"
13401o 64
13402suid 235,0
13403)
13404)
13405uid 18084,0
13406)
13407*467 (LeafLogPort
13408port (LogicalPort
13409lang 2
13410m 4
13411decl (Decl
13412n "mem_manager_state"
13413t "std_logic_vector"
13414b "(3 DOWNTO 0)"
13415eolc "-- state is encoded here ... useful for debugging."
13416posAdd 0
13417o 66
13418suid 237,0
13419)
13420)
13421uid 18213,0
13422)
13423*468 (LeafLogPort
13424port (LogicalPort
13425m 4
13426decl (Decl
13427n "DG_state"
13428t "std_logic_vector"
13429b "(7 downto 0)"
13430prec "-- for debugging"
13431preAdd 0
13432o 55
13433suid 238,0
13434)
13435)
13436uid 18334,0
13437)
13438*469 (LeafLogPort
13439port (LogicalPort
13440m 4
13441decl (Decl
13442n "socket_tx_free_out"
13443t "std_logic_vector"
13444b "(16 DOWNTO 0)"
13445eolc "-- 17bit value .. that's true"
13446posAdd 0
13447o 67
13448suid 239,0
13449)
13450)
13451uid 18483,0
13452)
13453*470 (LeafLogPort
13454port (LogicalPort
13455m 1
13456decl (Decl
13457n "W_T"
13458t "std_logic_vector"
13459b "( 3 DOWNTO 0 )"
13460o 49
13461suid 240,0
13462i "(others => '0')"
13463)
13464)
13465uid 18800,0
13466scheme 0
13467)
13468*471 (LeafLogPort
13469port (LogicalPort
13470m 4
13471decl (Decl
13472n "dac_cs1"
13473t "std_logic"
13474o 69
13475suid 241,0
13476)
13477)
13478uid 19557,0
13479)
13480*472 (LeafLogPort
13481port (LogicalPort
13482m 4
13483decl (Decl
13484n "sensor_cs"
13485t "std_logic_vector"
13486b "(3 DOWNTO 0)"
13487o 70
13488suid 242,0
13489)
13490)
13491uid 19559,0
13492)
13493*473 (LeafLogPort
13494port (LogicalPort
13495m 4
13496decl (Decl
13497n "sclk"
13498t "std_logic"
13499o 71
13500suid 243,0
13501)
13502)
13503uid 19561,0
13504)
13505*474 (LeafLogPort
13506port (LogicalPort
13507m 4
13508decl (Decl
13509n "mosi1"
13510t "std_logic"
13511o 72
13512suid 245,0
13513)
13514)
13515uid 19563,0
13516)
13517*475 (LeafLogPort
13518port (LogicalPort
13519m 4
13520decl (Decl
13521n "trigger_veto"
13522t "std_logic"
13523o 73
13524suid 249,0
13525i "'1'"
13526)
13527)
13528uid 20225,0
13529)
13530]
13531)
13532pdm (PhysicalDM
13533displayShortBounds 1
13534editShortBounds 1
13535uid 67,0
13536optionalChildren [
13537*476 (Sheet
13538sheetRow (SheetRow
13539headerVa (MVa
13540cellColor "49152,49152,49152"
13541fontColor "0,0,0"
13542font "Tahoma,10,0"
13543)
13544cellVa (MVa
13545cellColor "65535,65535,65535"
13546fontColor "0,0,0"
13547font "Tahoma,10,0"
13548)
13549groupVa (MVa
13550cellColor "39936,56832,65280"
13551fontColor "0,0,0"
13552font "Tahoma,10,0"
13553)
13554emptyMRCItem *477 (MRCItem
13555litem &390
13556pos 73
13557dimension 20
13558)
13559uid 69,0
13560optionalChildren [
13561*478 (MRCItem
13562litem &391
13563pos 0
13564dimension 20
13565uid 70,0
13566)
13567*479 (MRCItem
13568litem &392
13569pos 1
13570dimension 23
13571uid 71,0
13572)
13573*480 (MRCItem
13574litem &393
13575pos 2
13576hidden 1
13577dimension 20
13578uid 72,0
13579)
13580*481 (MRCItem
13581litem &403
13582pos 52
13583dimension 20
13584uid 328,0
13585)
13586*482 (MRCItem
13587litem &404
13588pos 53
13589dimension 20
13590uid 330,0
13591)
13592*483 (MRCItem
13593litem &405
13594pos 54
13595dimension 20
13596uid 1492,0
13597)
13598*484 (MRCItem
13599litem &406
13600pos 0
13601dimension 20
13602uid 2436,0
13603)
13604*485 (MRCItem
13605litem &407
13606pos 1
13607dimension 20
13608uid 3040,0
13609)
13610*486 (MRCItem
13611litem &408
13612pos 2
13613dimension 20
13614uid 3277,0
13615)
13616*487 (MRCItem
13617litem &409
13618pos 3
13619dimension 20
13620uid 3279,0
13621)
13622*488 (MRCItem
13623litem &410
13624pos 4
13625dimension 20
13626uid 3281,0
13627)
13628*489 (MRCItem
13629litem &411
13630pos 5
13631dimension 20
13632uid 3383,0
13633)
13634*490 (MRCItem
13635litem &412
13636pos 6
13637dimension 20
13638uid 3385,0
13639)
13640*491 (MRCItem
13641litem &413
13642pos 7
13643dimension 20
13644uid 3387,0
13645)
13646*492 (MRCItem
13647litem &414
13648pos 8
13649dimension 20
13650uid 3389,0
13651)
13652*493 (MRCItem
13653litem &415
13654pos 9
13655dimension 20
13656uid 3391,0
13657)
13658*494 (MRCItem
13659litem &416
13660pos 10
13661dimension 20
13662uid 3393,0
13663)
13664*495 (MRCItem
13665litem &417
13666pos 11
13667dimension 20
13668uid 3525,0
13669)
13670*496 (MRCItem
13671litem &418
13672pos 12
13673dimension 20
13674uid 3527,0
13675)
13676*497 (MRCItem
13677litem &419
13678pos 13
13679dimension 20
13680uid 3529,0
13681)
13682*498 (MRCItem
13683litem &420
13684pos 14
13685dimension 20
13686uid 3531,0
13687)
13688*499 (MRCItem
13689litem &421
13690pos 15
13691dimension 20
13692uid 3533,0
13693)
13694*500 (MRCItem
13695litem &422
13696pos 16
13697dimension 20
13698uid 3535,0
13699)
13700*501 (MRCItem
13701litem &423
13702pos 17
13703dimension 20
13704uid 3655,0
13705)
13706*502 (MRCItem
13707litem &424
13708pos 18
13709dimension 20
13710uid 3657,0
13711)
13712*503 (MRCItem
13713litem &425
13714pos 19
13715dimension 20
13716uid 3659,0
13717)
13718*504 (MRCItem
13719litem &426
13720pos 20
13721dimension 20
13722uid 3661,0
13723)
13724*505 (MRCItem
13725litem &427
13726pos 21
13727dimension 20
13728uid 3663,0
13729)
13730*506 (MRCItem
13731litem &428
13732pos 22
13733dimension 20
13734uid 3665,0
13735)
13736*507 (MRCItem
13737litem &429
13738pos 23
13739dimension 20
13740uid 3667,0
13741)
13742*508 (MRCItem
13743litem &430
13744pos 24
13745dimension 20
13746uid 3669,0
13747)
13748*509 (MRCItem
13749litem &431
13750pos 25
13751dimension 20
13752uid 3697,0
13753)
13754*510 (MRCItem
13755litem &432
13756pos 26
13757dimension 20
13758uid 3699,0
13759)
13760*511 (MRCItem
13761litem &433
13762pos 27
13763dimension 20
13764uid 3889,0
13765)
13766*512 (MRCItem
13767litem &434
13768pos 28
13769dimension 20
13770uid 3891,0
13771)
13772*513 (MRCItem
13773litem &435
13774pos 29
13775dimension 20
13776uid 3893,0
13777)
13778*514 (MRCItem
13779litem &436
13780pos 30
13781dimension 20
13782uid 3895,0
13783)
13784*515 (MRCItem
13785litem &437
13786pos 31
13787dimension 20
13788uid 3897,0
13789)
13790*516 (MRCItem
13791litem &438
13792pos 32
13793dimension 20
13794uid 3901,0
13795)
13796*517 (MRCItem
13797litem &439
13798pos 33
13799dimension 20
13800uid 5323,0
13801)
13802*518 (MRCItem
13803litem &440
13804pos 34
13805dimension 20
13806uid 6873,0
13807)
13808*519 (MRCItem
13809litem &441
13810pos 35
13811dimension 20
13812uid 7135,0
13813)
13814*520 (MRCItem
13815litem &442
13816pos 55
13817dimension 20
13818uid 9517,0
13819)
13820*521 (MRCItem
13821litem &443
13822pos 36
13823dimension 20
13824uid 10295,0
13825)
13826*522 (MRCItem
13827litem &444
13828pos 37
13829dimension 20
13830uid 11087,0
13831)
13832*523 (MRCItem
13833litem &445
13834pos 38
13835dimension 20
13836uid 11505,0
13837)
13838*524 (MRCItem
13839litem &446
13840pos 39
13841dimension 20
13842uid 11507,0
13843)
13844*525 (MRCItem
13845litem &447
13846pos 40
13847dimension 20
13848uid 12337,0
13849)
13850*526 (MRCItem
13851litem &448
13852pos 41
13853dimension 20
13854uid 12769,0
13855)
13856*527 (MRCItem
13857litem &449
13858pos 42
13859dimension 20
13860uid 12771,0
13861)
13862*528 (MRCItem
13863litem &450
13864pos 43
13865dimension 20
13866uid 12773,0
13867)
13868*529 (MRCItem
13869litem &451
13870pos 44
13871dimension 20
13872uid 13515,0
13873)
13874*530 (MRCItem
13875litem &452
13876pos 45
13877dimension 20
13878uid 13627,0
13879)
13880*531 (MRCItem
13881litem &453
13882pos 46
13883dimension 20
13884uid 14321,0
13885)
13886*532 (MRCItem
13887litem &454
13888pos 56
13889dimension 20
13890uid 15182,0
13891)
13892*533 (MRCItem
13893litem &455
13894pos 47
13895dimension 20
13896uid 15705,0
13897)
13898*534 (MRCItem
13899litem &456
13900pos 48
13901dimension 20
13902uid 15844,0
13903)
13904*535 (MRCItem
13905litem &457
13906pos 49
13907dimension 20
13908uid 16056,0
13909)
13910*536 (MRCItem
13911litem &458
13912pos 57
13913dimension 20
13914uid 16254,0
13915)
13916*537 (MRCItem
13917litem &459
13918pos 58
13919dimension 20
13920uid 16583,0
13921)
13922*538 (MRCItem
13923litem &460
13924pos 59
13925dimension 20
13926uid 16585,0
13927)
13928*539 (MRCItem
13929litem &461
13930pos 60
13931dimension 20
13932uid 16587,0
13933)
13934*540 (MRCItem
13935litem &462
13936pos 61
13937dimension 20
13938uid 17311,0
13939)
13940*541 (MRCItem
13941litem &463
13942pos 50
13943dimension 20
13944uid 17400,0
13945)
13946*542 (MRCItem
13947litem &464
13948pos 62
13949dimension 20
13950uid 17855,0
13951)
13952*543 (MRCItem
13953litem &465
13954pos 63
13955dimension 20
13956uid 18083,0
13957)
13958*544 (MRCItem
13959litem &466
13960pos 64
13961dimension 20
13962uid 18085,0
13963)
13964*545 (MRCItem
13965litem &467
13966pos 65
13967dimension 20
13968uid 18214,0
13969)
13970*546 (MRCItem
13971litem &468
13972pos 66
13973dimension 20
13974uid 18335,0
13975)
13976*547 (MRCItem
13977litem &469
13978pos 67
13979dimension 20
13980uid 18484,0
13981)
13982*548 (MRCItem
13983litem &470
13984pos 51
13985dimension 20
13986uid 18801,0
13987)
13988*549 (MRCItem
13989litem &471
13990pos 68
13991dimension 20
13992uid 19558,0
13993)
13994*550 (MRCItem
13995litem &472
13996pos 69
13997dimension 20
13998uid 19560,0
13999)
14000*551 (MRCItem
14001litem &473
14002pos 70
14003dimension 20
14004uid 19562,0
14005)
14006*552 (MRCItem
14007litem &474
14008pos 71
14009dimension 20
14010uid 19564,0
14011)
14012*553 (MRCItem
14013litem &475
14014pos 72
14015dimension 20
14016uid 20226,0
14017)
14018]
14019)
14020sheetCol (SheetCol
14021propVa (MVa
14022cellColor "0,49152,49152"
14023fontColor "0,0,0"
14024font "Tahoma,10,0"
14025textAngle 90
14026)
14027uid 73,0
14028optionalChildren [
14029*554 (MRCItem
14030litem &394
14031pos 0
14032dimension 20
14033uid 74,0
14034)
14035*555 (MRCItem
14036litem &396
14037pos 1
14038dimension 50
14039uid 75,0
14040)
14041*556 (MRCItem
14042litem &397
14043pos 2
14044dimension 100
14045uid 76,0
14046)
14047*557 (MRCItem
14048litem &398
14049pos 3
14050dimension 50
14051uid 77,0
14052)
14053*558 (MRCItem
14054litem &399
14055pos 4
14056dimension 100
14057uid 78,0
14058)
14059*559 (MRCItem
14060litem &400
14061pos 5
14062dimension 100
14063uid 79,0
14064)
14065*560 (MRCItem
14066litem &401
14067pos 6
14068dimension 182
14069uid 80,0
14070)
14071*561 (MRCItem
14072litem &402
14073pos 7
14074dimension 80
14075uid 81,0
14076)
14077]
14078)
14079fixedCol 4
14080fixedRow 2
14081name "Ports"
14082uid 68,0
14083vaOverrides [
14084]
14085)
14086]
14087)
14088uid 53,0
14089)
14090genericsCommonDM (CommonDM
14091ldm (LogicalDM
14092emptyRow *562 (LEmptyRow
14093)
14094uid 83,0
14095optionalChildren [
14096*563 (RefLabelRowHdr
14097)
14098*564 (TitleRowHdr
14099)
14100*565 (FilterRowHdr
14101)
14102*566 (RefLabelColHdr
14103tm "RefLabelColHdrMgr"
14104)
14105*567 (RowExpandColHdr
14106tm "RowExpandColHdrMgr"
14107)
14108*568 (GroupColHdr
14109tm "GroupColHdrMgr"
14110)
14111*569 (NameColHdr
14112tm "GenericNameColHdrMgr"
14113)
14114*570 (TypeColHdr
14115tm "GenericTypeColHdrMgr"
14116)
14117*571 (InitColHdr
14118tm "GenericValueColHdrMgr"
14119)
14120*572 (PragmaColHdr
14121tm "GenericPragmaColHdrMgr"
14122)
14123*573 (EolColHdr
14124tm "GenericEolColHdrMgr"
14125)
14126]
14127)
14128pdm (PhysicalDM
14129displayShortBounds 1
14130editShortBounds 1
14131uid 95,0
14132optionalChildren [
14133*574 (Sheet
14134sheetRow (SheetRow
14135headerVa (MVa
14136cellColor "49152,49152,49152"
14137fontColor "0,0,0"
14138font "Tahoma,10,0"
14139)
14140cellVa (MVa
14141cellColor "65535,65535,65535"
14142fontColor "0,0,0"
14143font "Tahoma,10,0"
14144)
14145groupVa (MVa
14146cellColor "39936,56832,65280"
14147fontColor "0,0,0"
14148font "Tahoma,10,0"
14149)
14150emptyMRCItem *575 (MRCItem
14151litem &562
14152pos 0
14153dimension 20
14154)
14155uid 97,0
14156optionalChildren [
14157*576 (MRCItem
14158litem &563
14159pos 0
14160dimension 20
14161uid 98,0
14162)
14163*577 (MRCItem
14164litem &564
14165pos 1
14166dimension 23
14167uid 99,0
14168)
14169*578 (MRCItem
14170litem &565
14171pos 2
14172hidden 1
14173dimension 20
14174uid 100,0
14175)
14176]
14177)
14178sheetCol (SheetCol
14179propVa (MVa
14180cellColor "0,49152,49152"
14181fontColor "0,0,0"
14182font "Tahoma,10,0"
14183textAngle 90
14184)
14185uid 101,0
14186optionalChildren [
14187*579 (MRCItem
14188litem &566
14189pos 0
14190dimension 20
14191uid 102,0
14192)
14193*580 (MRCItem
14194litem &568
14195pos 1
14196dimension 50
14197uid 103,0
14198)
14199*581 (MRCItem
14200litem &569
14201pos 2
14202dimension 100
14203uid 104,0
14204)
14205*582 (MRCItem
14206litem &570
14207pos 3
14208dimension 100
14209uid 105,0
14210)
14211*583 (MRCItem
14212litem &571
14213pos 4
14214dimension 50
14215uid 106,0
14216)
14217*584 (MRCItem
14218litem &572
14219pos 5
14220dimension 50
14221uid 107,0
14222)
14223*585 (MRCItem
14224litem &573
14225pos 6
14226dimension 80
14227uid 108,0
14228)
14229]
14230)
14231fixedCol 3
14232fixedRow 2
14233name "Ports"
14234uid 96,0
14235vaOverrides [
14236]
14237)
14238]
14239)
14240uid 82,0
14241type 1
14242)
14243activeModelName "BlockDiag"
14244)
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