DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
)
(DmPackageRef
library "ieee"
unitName "STD_LOGIC_UNSIGNED"
)
(DmPackageRef
library "fact_fad_lib"
unitName "fad_definitions"
)
(DmPackageRef
library "IEEE"
unitName "NUMERIC_STD"
)
(DmPackageRef
library "IEEE"
unitName "std_logic_signed"
)
(DmPackageRef
library "fact_fad_lib"
unitName "fad_rs485_constants"
)
(DmPackageRef
library "hds_package_library"
unitName "random_generators"
)
]
instances [
(Instance
name "I_main_data_generator"
duLibraryName "FACT_FAD_lib"
duName "data_generator"
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b"
)
]
mwi 0
uid 1399,0
)
(Instance
name "w5300_modul_instance"
duLibraryName "FACT_FAD_lib"
duName "w5300_modul"
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
mwi 0
uid 1606,0
)
(Instance
name "trigger_counter_instance"
duLibraryName "FACT_FAD_LIB"
duName "trigger_counter"
elements [
]
mwi 0
uid 1768,0
)
(Instance
name "I_main_drs_pulser"
duLibraryName "FACT_FAD_LIB"
duName "drs_pulser"
elements [
]
mwi 0
uid 4903,0
)
(Instance
name "I_main_adc_buffer"
duLibraryName "FACT_FAD_lib"
duName "adc_buffer"
elements [
]
mwi 0
uid 5678,0
)
(Instance
name "I_main_SPI_interface"
duLibraryName "FACT_FAD_lib"
duName "spi_interface"
elements [
]
mwi 0
uid 5793,0
)
(Instance
name "and_5"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 6529,0
)
(Instance
name "clock_generator_instance"
duLibraryName "FACT_FAD_lib"
duName "clock_generator_var_ps"
elements [
]
mwi 0
uid 9175,0
)
(Instance
name "I6"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 9957,0
)
(Instance
name "or_5"
duLibraryName "moduleware"
duName "or"
elements [
]
mwi 1
uid 10380,0
)
(Instance
name "led_controller_instance"
duLibraryName "FACT_FAD_lib"
duName "led_controller"
elements [
(GiElement
name "HEARTBEAT_PWM_DIVIDER"
type "integer"
value "50000"
)
(GiElement
name "WAITING_DIVIDER"
type "integer"
value "50000000"
)
]
mwi 0
uid 11209,0
)
(Instance
name "and_4"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 12295,0
)
(Instance
name "trigger_manager_instance"
duLibraryName "FACT_FAD_lib"
duName "trigger_manager"
elements [
]
mwi 0
uid 12625,0
)
(Instance
name "continous_pulser_instance"
duLibraryName "FACT_FAD_lib"
duName "continous_pulser"
elements [
(GiElement
name "MINIMAL_TRIGGER_WAIT_TIME"
type "integer"
value "25000"
)
(GiElement
name "TRIGGER_WIDTH"
type "integer"
value "5"
)
]
mwi 0
uid 13117,0
)
(Instance
name "REFCLK_counter_main"
duLibraryName "FACT_FAD_lib"
duName "REFCLK_counter"
elements [
]
mwi 0
uid 14417,0
)
(Instance
name "and_2"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 14991,0
)
(Instance
name "inverter_1"
duLibraryName "moduleware"
duName "inv"
elements [
]
mwi 1
uid 15058,0
)
(Instance
name "dna_gen_instance"
duLibraryName "FACT_FAD_lib"
duName "dna_gen"
elements [
]
mwi 0
uid 16404,0
)
(Instance
name "timer_instance"
duLibraryName "FACT_FAD_lib"
duName "timer"
elements [
(GiElement
name "TIMER_WIDTH"
type "integer"
value "32"
)
(GiElement
name "PRESCALER"
type "integer"
value "5000"
)
]
mwi 0
uid 16865,0
)
(Instance
name "U_14"
duLibraryName "moduleware"
duName "vdd"
elements [
]
mwi 1
uid 16902,0
)
(Instance
name "U_15"
duLibraryName "moduleware"
duName "gnd"
elements [
]
mwi 1
uid 16927,0
)
(Instance
name "and_1"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 19265,0
)
(Instance
name "U_0"
duLibraryName "moduleware"
duName "split"
elements [
]
mwi 1
uid 21806,0
)
(Instance
name "U_1"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 21871,0
)
(Instance
name "U_2"
duLibraryName "moduleware"
duName "or"
elements [
]
mwi 1
uid 21975,0
)
(Instance
name "U_4"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 22116,0
)
(Instance
name "U_3"
duLibraryName "moduleware"
duName "vdd"
elements [
]
mwi 1
uid 23004,0
)
(Instance
name "U_5"
duLibraryName "moduleware"
duName "assignment"
elements [
]
mwi 1
uid 23034,0
)
(Instance
name "Inst_rs485_receiver"
duLibraryName "FACT_FAD_lib"
duName "FAD_rs485_receiver"
elements [
(GiElement
name "RX_BYTES"
type "integer"
value "RS485_MESSAGE_LEN_BYTES"
e "-- no. of bytes to receive"
)
(GiElement
name "RX_WIDTH"
type "integer"
value "RS485_MESSAGE_LEN_BYTES * 8"
e "-- no. of bits to receive"
)
]
mwi 0
uid 24570,0
)
(Instance
name "U_6"
duLibraryName "moduleware"
duName "gnd"
elements [
]
mwi 1
uid 25830,0
)
(Instance
name "Inst_memory_manager_2"
duLibraryName "FACT_FAD_lib"
duName "memory_manager_2"
elements [
(GiElement
name "RAM_ADDR_WIDTH_64B"
type "integer"
value "RAMADDRWIDTH64b"
)
(GiElement
name "RAM_ADDR_WIDTH_16B"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
mwi 0
uid 27117,0
)
(Instance
name "or_2"
duLibraryName "moduleware"
duName "or"
elements [
]
mwi 1
uid 29010,0
)
(Instance
name "inverter_2"
duLibraryName "moduleware"
duName "inv"
elements [
]
mwi 1
uid 29055,0
)
(Instance
name "or_1"
duLibraryName "moduleware"
duName "or"
elements [
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mwi 1
uid 30674,0
)
(Instance
name "U_7"
duLibraryName "moduleware"
duName "and"
elements [
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mwi 1
uid 30733,0
)
(Instance
name "U_8"
duLibraryName "moduleware"
duName "assignment"
elements [
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mwi 1
uid 30812,0
)
(Instance
name "U_9"
duLibraryName "moduleware"
duName "assignment"
elements [
]
mwi 1
uid 30890,0
)
(Instance
name "inverter_3"
duLibraryName "moduleware"
duName "inv"
elements [
]
mwi 1
uid 31747,0
)
(Instance
name "U_10"
duLibraryName "moduleware"
duName "and"
elements [
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mwi 1
uid 31783,0
)
(Instance
name "or_3"
duLibraryName "moduleware"
duName "or"
elements [
]
mwi 1
uid 32288,0
)
(Instance
name "inverter_4"
duLibraryName "moduleware"
duName "inv"
elements [
]
mwi 1
uid 32642,0
)
(Instance
name "data_RAM_inst"
duLibraryName "FACT_FAD_lib"
duName "dataRAM_64b_16b_width14_5"
elements [
]
mwi 0
uid 33522,0
)
]
libraryRefs [
"ieee"
"fact_fad_lib"
"UNISIM"
"hds_package_library"
]
)
version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main"
)
(vvPair
variable "d_logical"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main"
)
(vvPair
variable "date"
value "02.08.2011"
)
(vvPair
variable "day"
value "Di"
)
(vvPair
variable "day_long"
value "Dienstag"
)
(vvPair
variable "dd"
value "02"
)
(vvPair
variable "entity_name"
value "FAD_main"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "FAD_main"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\FAD\\aug2_noon\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "14:38:47"
)
(vvPair
variable "unit"
value "FAD_main"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
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f (Text
uid 483,0
va (VaSet
)
xt "131000,55500,133700,56500"
st "wiz_wr"
blo "131000,56300"
tm "WireNameMgr"
)
)
)
*19 (PortIoOut
uid 484,0
shape (CompositeShape
uid 485,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 486,0
sl 0
ro 270
xt "130500,72625,132000,73375"
)
(Line
uid 487,0
sl 0
ro 270
xt "130000,73000,130500,73000"
pts [
"130000,73000"
"130500,73000"
]
)
]
)
sf 1
tg (WTG
uid 488,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 489,0
va (VaSet
)
xt "133000,72500,137000,73500"
st "led : (7:0)"
blo "133000,73300"
tm "WireNameMgr"
)
)
)
*20 (PortIoOut
uid 490,0
shape (CompositeShape
uid 491,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 492,0
sl 0
ro 270
xt "128500,56625,130000,57375"
)
(Line
uid 493,0
sl 0
ro 270
xt "128000,57000,128500,57000"
pts [
"128000,57000"
"128500,57000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 494,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 495,0
va (VaSet
)
xt "131000,56500,133600,57500"
st "wiz_rd"
blo "131000,57300"
tm "WireNameMgr"
)
)
)
*21 (PortIoIn
uid 496,0
shape (CompositeShape
uid 497,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 498,0
sl 0
ro 90
xt "128500,57625,130000,58375"
)
(Line
uid 499,0
sl 0
ro 90
xt "128000,58000,128500,58000"
pts [
"128500,58000"
"128000,58000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 500,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 501,0
va (VaSet
)
xt "131000,57500,133700,58500"
st "wiz_int"
blo "131000,58300"
tm "WireNameMgr"
)
)
)
*22 (SaComponent
uid 1399,0
optionalChildren [
*23 (CptPort
uid 1352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1353,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,53625,-24000,54375"
)
tg (CPTG
uid 1354,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1355,0
va (VaSet
)
xt "-23000,53500,-21500,54500"
st "clk"
blo "-23000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
eolc "-- CLK_25."
preAdd 0
posAdd 0
o 3
suid 1,0
)
)
)
*24 (CptPort
uid 1356,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1357,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,55625,3750,56375"
)
tg (CPTG
uid 1358,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1359,0
va (VaSet
)
xt "-5200,55500,2000,56500"
st "data_out : (63:0)"
ju 2
blo "2000,56300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 4
suid 2,0
)
)
)
*25 (CptPort
uid 1360,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1361,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,54625,3750,55375"
)
tg (CPTG
uid 1362,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1363,0
va (VaSet
)
xt "-13700,54500,2000,55500"
st "addr_out : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "2000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 3,0
)
)
)
*26 (CptPort
uid 1376,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2344,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,73625,3750,74375"
)
tg (CPTG
uid 1378,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1379,0
va (VaSet
)
xt "-16400,73500,2000,74500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "2000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 7
suid 7,0
)
)
)
*27 (CptPort
uid 1384,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1385,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,96625,-24000,97375"
)
tg (CPTG
uid 1386,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1387,0
va (VaSet
)
xt "-23000,96500,-16300,97500"
st "board_id : (3:0)"
blo "-23000,97300"
)
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
prec "-- EVT HEADER - part 4"
preAdd 0
posAdd 0
o 33
suid 9,0
)
)
)
*28 (CptPort
uid 1676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,97625,-24000,98375"
)
tg (CPTG
uid 1678,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1679,0
va (VaSet
)
xt "-23000,97500,-16600,98500"
st "crate_id : (1:0)"
blo "-23000,98300"
)
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
posAdd 0
o 34
suid 12,0
)
)
)
*29 (CptPort
uid 2562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2563,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,74625,3750,75375"
)
tg (CPTG
uid 2564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2565,0
va (VaSet
)
xt "-4100,74500,2000,75500"
st "ram_write_ea"
ju 2
blo "2000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 8
suid 16,0
)
)
)
*30 (CptPort
uid 2566,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2567,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,75625,3750,76375"
)
tg (CPTG
uid 2568,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2569,0
va (VaSet
)
xt "-5400,75500,2000,76500"
st "ram_write_ready"
ju 2
blo "2000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
posAdd 0
o 9
suid 17,0
i "'0'"
)
)
)
*31 (CptPort
uid 2570,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2571,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,81625,3750,82375"
)
tg (CPTG
uid 2572,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2573,0
va (VaSet
)
xt "-1400,81500,2000,82500"
st "roi_max"
ju 2
blo "2000,82300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 11
suid 18,0
)
)
)
*32 (CptPort
uid 2614,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2615,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,100625,3750,101375"
)
tg (CPTG
uid 2616,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2617,0
va (VaSet
)
xt "-1900,100500,2000,101500"
st "roi_array"
ju 2
blo "2000,101300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 10
suid 19,0
)
)
)
*33 (CptPort
uid 2624,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2625,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,82625,3750,83375"
)
tg (CPTG
uid 2626,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2627,0
va (VaSet
)
xt "-7900,82500,2000,83500"
st "package_length : (15:0)"
ju 2
blo "2000,83300"
)
)
thePort (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
prec "-- EVT HEADER - part 1"
preAdd 0
o 17
suid 20,0
)
)
)
*34 (CptPort
uid 2764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,88625,-24000,89375"
)
tg (CPTG
uid 2766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2767,0
va (VaSet
)
xt "-23000,88500,-16700,89500"
st "adc_otr : (3:0)"
blo "-23000,89300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 48
suid 24,0
)
)
)
*35 (CptPort
uid 3918,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3919,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,69625,-24000,70375"
)
tg (CPTG
uid 3920,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3921,0
va (VaSet
)
xt "-23000,69500,-13500,70500"
st "drs_channel_id : (3:0)"
blo "-23000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 49
suid 25,0
i "(others => '0')"
)
)
)
*36 (CptPort
uid 3922,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3923,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,58625,-24000,59375"
)
tg (CPTG
uid 3924,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3925,0
va (VaSet
)
xt "-23000,58500,-17900,59500"
st "drs_clk_en"
blo "-23000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 26,0
i "'0'"
)
)
)
*37 (CptPort
uid 3934,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3935,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,56625,-24000,57375"
)
tg (CPTG
uid 3936,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3937,0
va (VaSet
)
xt "-23000,56500,-12900,57500"
st "drs_read_s_cell_ready"
blo "-23000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 58
suid 34,0
)
)
)
*38 (CptPort
uid 3938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3939,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,57625,-24000,58375"
)
tg (CPTG
uid 3940,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3941,0
va (VaSet
)
xt "-23000,57500,-15700,58500"
st "drs_s_cell_array"
blo "-23000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 59
suid 35,0
)
)
)
*39 (CptPort
uid 4246,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4247,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,87625,-24000,88375"
)
tg (CPTG
uid 4248,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4249,0
va (VaSet
)
xt "-23000,87500,-16100,88500"
st "adc_data_array"
blo "-23000,88300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 45
suid 37,0
)
)
)
*40 (CptPort
uid 5464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5465,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,110625,3750,111375"
)
tg (CPTG
uid 5466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5467,0
va (VaSet
)
xt "-3800,110500,2000,111500"
st "sensor_array"
ju 2
blo "2000,111300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 12
suid 44,0
)
)
)
*41 (CptPort
uid 5468,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5469,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,111625,3750,112375"
)
tg (CPTG
uid 5470,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5471,0
va (VaSet
)
xt "-3900,111500,2000,112500"
st "sensor_ready"
ju 2
blo "2000,112300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 13
suid 45,0
)
)
)
*42 (CptPort
uid 6060,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6061,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,99625,3750,100375"
)
tg (CPTG
uid 6062,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6063,0
va (VaSet
)
xt "-2200,99500,2000,100500"
st "dac_array"
ju 2
blo "2000,100300"
)
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
posAdd 0
o 14
suid 53,0
)
)
)
*43 (CptPort
uid 9000,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9001,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,94625,-24000,95375"
)
tg (CPTG
uid 9002,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9003,0
va (VaSet
)
xt "-23000,94500,-17900,95500"
st "adc_clk_en"
blo "-23000,95300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_clk_en"
t "std_logic"
o 47
suid 54,0
i "'0'"
)
)
)
*44 (CptPort
uid 10244,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10245,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,62625,-24000,63375"
)
tg (CPTG
uid 10246,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10247,0
va (VaSet
)
xt "-23000,62500,-13800,63500"
st "drs_srin_data : (7:0)"
blo "-23000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_srin_data"
t "std_logic_vector"
b "(7 downto 0)"
o 56
suid 56,0
i "(others => '0')"
)
)
)
*45 (CptPort
uid 10248,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10249,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,59625,-24000,60375"
)
tg (CPTG
uid 10250,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10251,0
va (VaSet
)
xt "-23000,59500,-14900,60500"
st "drs_srin_write_8b"
blo "-23000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_srin_write_8b"
t "std_logic"
o 54
suid 57,0
i "'0'"
)
)
)
*46 (CptPort
uid 10252,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10253,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,60625,-24000,61375"
)
tg (CPTG
uid 10254,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10255,0
va (VaSet
)
xt "-23000,60500,-14600,61500"
st "drs_srin_write_ack"
blo "-23000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_srin_write_ack"
t "std_logic"
o 55
suid 58,0
)
)
)
*47 (CptPort
uid 10256,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10257,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,61625,-24000,62375"
)
tg (CPTG
uid 10258,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10259,0
va (VaSet
)
xt "-23000,61500,-13300,62500"
st "drs_srin_write_ready"
blo "-23000,62300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_srin_write_ready"
t "std_logic"
o 57
suid 59,0
)
)
)
*48 (CptPort
uid 11385,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11386,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,103625,3750,104375"
)
tg (CPTG
uid 11387,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11388,0
va (VaSet
)
xt "-7000,103500,2000,104500"
st "drs_readout_started"
ju 2
blo "2000,104300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_started"
t "std_logic"
o 60
suid 61,0
i "'0'"
)
)
)
*49 (CptPort
uid 12597,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12598,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,76625,-24000,77375"
)
tg (CPTG
uid 12599,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12600,0
va (VaSet
)
xt "-23000,76500,-14800,77500"
st "drs_readout_ready"
blo "-23000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "--drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 50
suid 62,0
i "'0'"
)
)
)
*50 (CptPort
uid 12601,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12602,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,77625,-24000,78375"
)
tg (CPTG
uid 12603,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12604,0
va (VaSet
)
xt "-23000,77500,-12500,78500"
st "drs_readout_ready_ack"
blo "-23000,78300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
posAdd 0
o 51
suid 63,0
)
)
)
*51 (CptPort
uid 15740,0
ps "OnEdgeStrategy"
shape (Triangle
uid 15741,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,72625,-24000,73375"
)
tg (CPTG
uid 15742,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 15743,0
va (VaSet
)
xt "-23000,72500,-11700,73500"
st "fad_event_counter : (31:0)"
blo "-23000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "fad_event_counter"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 3"
preAdd 0
o 29
suid 65,0
)
)
)
*52 (CptPort
uid 15744,0
ps "OnEdgeStrategy"
shape (Triangle
uid 15745,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,98625,-24000,99375"
)
tg (CPTG
uid 15746,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 15747,0
va (VaSet
)
xt "-23000,98500,-16900,99500"
st "pll_lock : (3:0)"
blo "-23000,99300"
)
)
thePort (LogicalPort
decl (Decl
n "pll_lock"
t "std_logic_vector"
b "( 3 downto 0)"
posAdd 0
o 18
suid 64,0
)
)
)
*53 (CptPort
uid 16320,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16321,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,99625,-24000,100375"
)
tg (CPTG
uid 16322,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16323,0
va (VaSet
)
xt "-23000,99500,-13000,100500"
st "DCM_PS_status : (7:0)"
blo "-23000,100300"
)
)
thePort (LogicalPort
decl (Decl
n "DCM_PS_status"
t "std_logic_vector"
b "(7 downto 0)"
o 35
suid 71,0
)
)
)
*54 (CptPort
uid 16324,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16325,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,100625,-24000,101375"
)
tg (CPTG
uid 16326,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16327,0
va (VaSet
)
xt "-23000,100500,-17900,101500"
st "dna : (63:0)"
blo "-23000,101300"
)
)
thePort (LogicalPort
decl (Decl
n "dna"
t "std_logic_vector"
b "(63 downto 0)"
prec "-- EVT HEADER - part 5"
preAdd 0
posAdd 0
o 40
suid 74,0
)
)
)
*55 (CptPort
uid 16328,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16329,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,101625,-24000,102375"
)
tg (CPTG
uid 16330,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16331,0
va (VaSet
)
xt "-23000,101500,-14700,102500"
st "FTM_RS485_ready"
blo "-23000,102300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_ready"
t "std_logic"
prec "-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
-- during EVT header wrinting, this field is left out ... and only written into event header,
-- when the DRS chip were read out already."
preAdd 0
o 26
suid 69,0
)
)
)
*56 (CptPort
uid 16332,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16333,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,102625,-24000,103375"
)
tg (CPTG
uid 16334,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16335,0
va (VaSet
)
xt "-23000,102500,-12000,103500"
st "FTM_trigger_info : (55:0)"
blo "-23000,103300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_trigger_info"
t "std_logic_vector"
b "(55 downto 0)"
eolc "--7 byte"
posAdd 0
o 27
suid 70,0
)
)
)
*57 (CptPort
uid 16336,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16337,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,105625,-24000,106375"
)
tg (CPTG
uid 16338,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16339,0
va (VaSet
)
xt "-23000,105500,-13300,106500"
st "refclk_counter : (11:0)"
blo "-23000,106300"
)
)
thePort (LogicalPort
decl (Decl
n "refclk_counter"
t "std_logic_vector"
b "(11 downto 0)"
o 30
suid 66,0
)
)
)
*58 (CptPort
uid 16340,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16341,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,106625,-24000,107375"
)
tg (CPTG
uid 16342,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16343,0
va (VaSet
)
xt "-23000,106500,-16000,107500"
st "refclk_too_high"
blo "-23000,107300"
)
)
thePort (LogicalPort
decl (Decl
n "refclk_too_high"
t "std_logic"
o 31
suid 67,0
)
)
)
*59 (CptPort
uid 16344,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16345,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,107625,-24000,108375"
)
tg (CPTG
uid 16346,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16347,0
va (VaSet
)
xt "-23000,107500,-16400,108500"
st "refclk_too_low"
blo "-23000,108300"
)
)
thePort (LogicalPort
decl (Decl
n "refclk_too_low"
t "std_logic"
posAdd 0
o 32
suid 68,0
)
)
)
*60 (CptPort
uid 16348,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16349,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,108625,-24000,109375"
)
tg (CPTG
uid 16350,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16351,0
va (VaSet
)
xt "-23000,108500,-14500,109500"
st "timer_value : (31:0)"
blo "-23000,109300"
)
)
thePort (LogicalPort
decl (Decl
n "timer_value"
t "std_logic_vector"
b "(31 downto 0)"
eolc "-- time in units of 100us"
preAdd 0
posAdd 0
o 42
suid 75,0
)
)
)
*61 (CptPort
uid 16352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16353,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,109625,-24000,110375"
)
tg (CPTG
uid 16354,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16355,0
va (VaSet
)
xt "-23000,109500,-13600,110500"
st "TRG_GEN_div : (15:0)"
blo "-23000,110300"
)
)
thePort (LogicalPort
decl (Decl
n "TRG_GEN_div"
t "std_logic_vector"
b "(15 downto 0)"
posAdd 0
o 39
suid 72,0
)
)
)
*62 (CptPort
uid 17900,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17901,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,93625,-24000,94375"
)
tg (CPTG
uid 17902,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17903,0
va (VaSet
)
xt "-23000,93500,-11000,94500"
st "adc_output_enable_inverted"
blo "-23000,94300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_output_enable_inverted"
t "std_logic"
o 46
suid 76,0
i "'1'"
)
)
)
*63 (CptPort
uid 17908,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17909,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,53625,3750,54375"
)
tg (CPTG
uid 17910,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 17911,0
va (VaSet
)
xt "-10000,53500,2000,54500"
st "dataRAM_write_ea_o : (0:0)"
ju 2
blo "2000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataRAM_write_ea_o"
t "std_logic_vector"
b "(0 downto 0)"
o 6
suid 78,0
i "\"0\""
)
)
)
*64 (CptPort
uid 17916,0
ps "OnEdgeStrategy"
shape (Triangle
uid 17917,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,55625,-24000,56375"
)
tg (CPTG
uid 17918,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 17919,0
va (VaSet
)
xt "-23000,55500,-11800,56500"
st "start_read_drs_stop_cell"
blo "-23000,56300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "start_read_drs_stop_cell"
t "std_logic"
o 53
suid 80,0
i "'0'"
)
)
)
*65 (CptPort
uid 21113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21114,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,86625,3750,87375"
)
tg (CPTG
uid 21115,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21116,0
va (VaSet
)
xt "-3300,86500,2000,87500"
st "config_done"
ju 2
blo "2000,87300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_done"
t "std_logic"
o 16
suid 83,0
i "'0'"
)
)
)
*66 (CptPort
uid 21117,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21118,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,85625,3750,86375"
)
tg (CPTG
uid 21119,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21120,0
va (VaSet
)
xt "-3600,85500,2000,86500"
st "config_start"
ju 2
blo "2000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 15
suid 84,0
)
)
)
*67 (CptPort
uid 23325,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23326,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,110625,-24000,111375"
)
tg (CPTG
uid 23327,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23328,0
va (VaSet
)
xt "-23000,110500,-14500,111500"
st "DCM_locked_status"
blo "-23000,111300"
)
)
thePort (LogicalPort
decl (Decl
n "DCM_locked_status"
t "std_logic"
o 36
suid 85,0
)
)
)
*68 (CptPort
uid 23329,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23330,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,111625,-24000,112375"
)
tg (CPTG
uid 23331,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23332,0
va (VaSet
)
xt "-23000,111500,-14800,112500"
st "DCM_ready_status"
blo "-23000,112300"
)
)
thePort (LogicalPort
decl (Decl
n "DCM_ready_status"
t "std_logic"
o 37
suid 86,0
)
)
)
*69 (CptPort
uid 23333,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23334,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,112625,-24000,113375"
)
tg (CPTG
uid 23335,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23336,0
va (VaSet
)
xt "-23000,112500,-15400,113500"
st "denable_enable_in"
blo "-23000,113300"
)
)
thePort (LogicalPort
decl (Decl
n "denable_enable_in"
t "std_logic"
o 20
suid 87,0
)
)
)
*70 (CptPort
uid 23337,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23338,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,113625,-24000,114375"
)
tg (CPTG
uid 23339,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23340,0
va (VaSet
)
xt "-23000,113500,-15700,114500"
st "dwrite_enable_in"
blo "-23000,114300"
)
)
thePort (LogicalPort
decl (Decl
n "dwrite_enable_in"
t "std_logic"
o 19
suid 88,0
)
)
)
*71 (CptPort
uid 23596,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23597,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,114625,-24000,115375"
)
tg (CPTG
uid 23598,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23599,0
va (VaSet
)
xt "-23000,114500,-12000,115500"
st "SPI_SCLK_enable_status"
blo "-23000,115300"
)
)
thePort (LogicalPort
decl (Decl
n "SPI_SCLK_enable_status"
t "std_logic"
o 38
suid 89,0
)
)
)
*72 (CptPort
uid 24064,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24065,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,106625,3750,107375"
)
tg (CPTG
uid 24066,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24067,0
va (VaSet
)
xt "-3600,106500,2000,107500"
st "trigger_veto"
ju 2
blo "2000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 61
suid 90,0
i "'1'"
)
)
)
*73 (CptPort
uid 24746,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24747,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,103625,-24000,104375"
)
tg (CPTG
uid 24748,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 24749,0
va (VaSet
)
xt "-23000,103500,-14000,104500"
st "FTM_receiver_status"
blo "-23000,104300"
)
)
thePort (LogicalPort
decl (Decl
n "FTM_receiver_status"
t "std_logic"
o 28
suid 91,0
)
)
)
*74 (CptPort
uid 24995,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24996,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,104625,-24000,105375"
)
tg (CPTG
uid 24997,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 24998,0
va (VaSet
)
xt "-23000,104500,-15400,105500"
st "runnumber : (31:0)"
blo "-23000,105300"
)
)
thePort (LogicalPort
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 6"
preAdd 0
posAdd 0
o 41
suid 92,0
)
)
)
*75 (CptPort
uid 25792,0
ps "OnEdgeStrategy"
shape (Triangle
uid 25793,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,74625,-24000,75375"
)
tg (CPTG
uid 25794,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 25795,0
va (VaSet
)
xt "-23000,74500,-14300,75500"
st "hardware_trigger_in"
blo "-23000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "hardware_trigger_in"
t "std_logic"
o 43
suid 96,0
)
)
)
*76 (CptPort
uid 25796,0
ps "OnEdgeStrategy"
shape (Triangle
uid 25797,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,75625,-24000,76375"
)
tg (CPTG
uid 25798,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 25799,0
va (VaSet
)
xt "-23000,75500,-14500,76500"
st "software_trigger_in"
blo "-23000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "software_trigger_in"
t "std_logic"
o 44
suid 97,0
)
)
)
*77 (CptPort
uid 26312,0
ps "OnEdgeStrategy"
shape (Triangle
uid 26313,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,102625,3750,103375"
)
tg (CPTG
uid 26314,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 26315,0
va (VaSet
)
xt "-800,102500,2000,103500"
st "is_idle"
ju 2
blo "2000,103300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "is_idle"
t "std_logic"
o 2
suid 100,0
)
)
)
*78 (CptPort
uid 26316,0
ps "OnEdgeStrategy"
shape (Triangle
uid 26317,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "3000,107625,3750,108375"
)
tg (CPTG
uid 26318,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 26319,0
va (VaSet
)
xt "-3300,107500,2000,108500"
st "state : (7:0)"
ju 2
blo "2000,108300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 1
suid 99,0
)
)
)
*79 (CptPort
uid 31160,0
ps "OnEdgeStrategy"
shape (Triangle
uid 31161,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,115625,-24000,116375"
)
tg (CPTG
uid 31162,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 31163,0
va (VaSet
)
xt "-23000,115500,-16500,116500"
st "busy_enable_in"
blo "-23000,116300"
)
)
thePort (LogicalPort
decl (Decl
n "busy_enable_in"
t "std_logic"
o 21
suid 101,0
)
)
)
*80 (CptPort
uid 31164,0
ps "OnEdgeStrategy"
shape (Triangle
uid 31165,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,116625,-24000,117375"
)
tg (CPTG
uid 31166,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 31167,0
va (VaSet
)
xt "-23000,116500,-15000,117500"
st "cont_trigger_en_in"
blo "-23000,117300"
)
)
thePort (LogicalPort
decl (Decl
n "cont_trigger_en_in"
t "std_logic"
o 23
suid 102,0
)
)
)
*81 (CptPort
uid 31168,0
ps "OnEdgeStrategy"
shape (Triangle
uid 31169,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,117625,-24000,118375"
)
tg (CPTG
uid 31170,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 31171,0
va (VaSet
)
xt "-23000,117500,-13900,118500"
st "socket_send_mode_in"
blo "-23000,118300"
)
)
thePort (LogicalPort
decl (Decl
n "socket_send_mode_in"
t "std_logic"
o 24
suid 103,0
)
)
)
*82 (CptPort
uid 31172,0
ps "OnEdgeStrategy"
shape (Triangle
uid 31173,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,118625,-24000,119375"
)
tg (CPTG
uid 31174,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 31175,0
va (VaSet
)
xt "-23000,118500,-15600,119500"
st "trigger_enable_in"
blo "-23000,119300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger_enable_in"
t "std_logic"
o 22
suid 104,0
)
)
)
*83 (CptPort
uid 32389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 32390,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-24750,119625,-24000,120375"
)
tg (CPTG
uid 32391,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 32392,0
va (VaSet
)
xt "-23000,119500,-16400,120500"
st "busy_manual_in"
blo "-23000,120300"
)
)
thePort (LogicalPort
decl (Decl
n "busy_manual_in"
t "std_logic"
o 25
suid 105,0
)
)
)
]
shape (Rectangle
uid 1400,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-24000,53000,3000,122000"
)
oxt "37000,1000,51000,21000"
ttg (MlTextGroup
uid 1401,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*84 (Text
uid 1402,0
va (VaSet
font "Arial,8,1"
)
xt "-10700,114000,-4500,115000"
st "FACT_FAD_lib"
blo "-10700,114800"
tm "BdLibraryNameMgr"
)
*85 (Text
uid 1403,0
va (VaSet
font "Arial,8,1"
)
xt "-10700,115000,-4300,116000"
st "data_generator"
blo "-10700,115800"
tm "CptNameMgr"
)
*86 (Text
uid 1404,0
va (VaSet
font "Arial,8,1"
)
xt "-10700,116000,-1100,117000"
st "I_main_data_generator"
blo "-10700,116800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1405,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1406,0
text (MLText
uid 1407,0
va (VaSet
font "Courier New,8,0"
)
xt "-24000,52200,2500,53000"
st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b"
)
]
)
viewicon (ZoomableIcon
uid 1408,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-23750,120250,-22250,121750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*87 (Net
uid 1409,0
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 28,0
)
declText (MLText
uid 1410,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,10400,-140500,11200"
st "board_id                     : std_logic_vector(3 DOWNTO 0)"
)
)
*88 (Net
uid 1423,0
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 29,0
)
declText (MLText
uid 1424,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,13600,-150000,14400"
st "trigger                      : std_logic"
)
)
*89 (PortIoIn
uid 1443,0
shape (CompositeShape
uid 1444,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1445,0
sl 0
ro 270
xt "-131000,67625,-129500,68375"
)
(Line
uid 1446,0
sl 0
ro 270
xt "-129500,68000,-129000,68000"
pts [
"-129500,68000"
"-129000,68000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1447,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1448,0
va (VaSet
)
xt "-134800,67500,-132000,68500"
st "trigger"
ju 2
blo "-132000,68300"
tm "WireNameMgr"
)
)
)
*90 (SaComponent
uid 1606,0
optionalChildren [
*91 (CptPort
uid 1542,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1543,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,53625,88000,54375"
)
tg (CPTG
uid 1544,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1545,0
va (VaSet
)
xt "89000,53500,90500,54500"
st "clk"
blo "89000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 1,0
)
)
)
*92 (CptPort
uid 1546,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1547,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,53625,124750,54375"
)
tg (CPTG
uid 1548,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1549,0
va (VaSet
)
xt "118800,53500,123000,54500"
st "wiz_reset"
ju 2
blo "123000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 2,0
i "'1'"
)
)
)
*93 (CptPort
uid 1550,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1551,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,61625,124750,62375"
)
tg (CPTG
uid 1552,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1553,0
va (VaSet
)
xt "117900,61500,123000,62500"
st "addr : (9:0)"
ju 2
blo "123000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 10
suid 3,0
)
)
)
*94 (CptPort
uid 1554,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1555,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,62625,124750,63375"
)
tg (CPTG
uid 1556,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1557,0
va (VaSet
)
xt "117600,62500,123000,63500"
st "data : (15:0)"
ju 2
blo "123000,63300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 11
suid 4,0
)
)
)
*95 (CptPort
uid 1558,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1559,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,54625,124750,55375"
)
tg (CPTG
uid 1560,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1561,0
va (VaSet
)
xt "121800,54500,123000,55500"
st "cs"
ju 2
blo "123000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cs"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 5,0
i "'1'"
)
)
)
*96 (CptPort
uid 1562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1563,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,55625,124750,56375"
)
tg (CPTG
uid 1564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1565,0
va (VaSet
)
xt "121600,55500,123000,56500"
st "wr"
ju 2
blo "123000,56300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 13
suid 6,0
i "'1'"
)
)
)
*97 (CptPort
uid 1570,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1571,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,56625,124750,57375"
)
tg (CPTG
uid 1572,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1573,0
va (VaSet
)
xt "121700,56500,123000,57500"
st "rd"
ju 2
blo "123000,57300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 15
suid 8,0
i "'1'"
)
)
)
*98 (CptPort
uid 1574,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1575,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,57625,124750,58375"
)
tg (CPTG
uid 1576,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1577,0
va (VaSet
)
xt "121600,57500,123000,58500"
st "int"
ju 2
blo "123000,58300"
)
)
thePort (LogicalPort
decl (Decl
n "int"
t "std_logic"
preAdd 0
posAdd 0
o 16
suid 9,0
)
)
)
*99 (CptPort
uid 1578,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1579,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,72625,88000,73375"
)
tg (CPTG
uid 1580,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1581,0
va (VaSet
)
xt "89000,72500,98000,73500"
st "write_length : (16:0)"
blo "89000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 10,0
)
)
)
*100 (CptPort
uid 1582,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1583,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,73625,88000,74375"
)
tg (CPTG
uid 1584,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1585,0
va (VaSet
)
xt "89000,73500,107400,74500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
blo "89000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 18
suid 11,0
)
)
)
*101 (CptPort
uid 1586,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1587,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,56625,88000,57375"
)
tg (CPTG
uid 1588,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1589,0
va (VaSet
)
xt "89000,56500,96300,57500"
st "ram_data : (15:0)"
blo "89000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 19
suid 12,0
)
)
)
*102 (CptPort
uid 1590,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1591,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,55625,88000,56375"
)
tg (CPTG
uid 1592,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1593,0
va (VaSet
)
xt "89000,55500,104900,56500"
st "ram_addr : (RAM_ADDR_WIDTH-1:0)"
blo "89000,56300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 20
suid 13,0
)
)
)
*103 (CptPort
uid 1594,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1595,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,78625,88000,79375"
)
tg (CPTG
uid 1596,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1597,0
va (VaSet
)
xt "89000,78500,93800,79500"
st "data_valid"
blo "89000,79300"
)
)
thePort (LogicalPort
decl (Decl
n "data_valid"
t "std_logic"
preAdd 0
posAdd 0
o 21
suid 14,0
)
)
)
*104 (CptPort
uid 1598,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1599,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,70625,88000,71375"
)
tg (CPTG
uid 1600,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1601,0
va (VaSet
)
xt "89000,70500,91100,71500"
st "busy"
blo "89000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy"
t "std_logic"
preAdd 0
posAdd 0
o 23
suid 15,0
i "'1'"
)
)
)
*105 (CptPort
uid 2218,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2219,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,74625,88000,75375"
)
tg (CPTG
uid 2220,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2221,0
va (VaSet
)
xt "89000,74500,97800,75500"
st "fifo_channels : (3:0)"
blo "89000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 26
suid 20,0
)
)
)
*106 (CptPort
uid 2222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2223,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,75625,88000,76375"
)
tg (CPTG
uid 2224,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2225,0
va (VaSet
)
xt "89000,75500,95600,76500"
st "write_end_flag"
blo "89000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "write_end_flag"
t "std_logic"
o 25
suid 18,0
)
)
)
*107 (CptPort
uid 2226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2227,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,76625,88000,77375"
)
tg (CPTG
uid 2228,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2229,0
va (VaSet
)
xt "89000,76500,96900,77500"
st "write_header_flag"
blo "89000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "write_header_flag"
t "std_logic"
o 24
suid 19,0
)
)
)
*108 (CptPort
uid 5216,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5217,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,72625,124750,73375"
)
tg (CPTG
uid 5218,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5219,0
va (VaSet
)
xt "118600,72500,123000,73500"
st "led : (7:0)"
ju 2
blo "123000,73300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 14
suid 22,0
i "(OTHERS => '0')"
)
)
)
*109 (CptPort
uid 5275,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5276,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,65625,88000,66375"
)
tg (CPTG
uid 5277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5278,0
va (VaSet
)
xt "89000,65500,92900,66500"
st "s_trigger"
blo "89000,66300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "s_trigger"
t "std_logic"
prec "-- softtrigger:"
preAdd 0
o 27
suid 23,0
i "'0'"
)
)
)
*110 (CptPort
uid 6356,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6357,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,76625,124750,77375"
)
tg (CPTG
uid 6358,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6359,0
va (VaSet
)
xt "119800,76500,123000,77500"
st "denable"
ju 2
blo "123000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override."
preAdd 0
posAdd 0
o 43
suid 31,0
i "'0'"
)
)
)
*111 (CptPort
uid 6446,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6447,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,79625,124750,80375"
)
tg (CPTG
uid 6448,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6449,0
va (VaSet
)
xt "116800,79500,123000,80500"
st "dwrite_enable"
ju 2
blo "123000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dwrite_enable"
t "std_logic"
eolc "-- default DWRITE low."
preAdd 0
posAdd 0
o 44
suid 32,0
i "'1'"
)
)
)
*112 (CptPort
uid 8406,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8407,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,79625,88000,80375"
)
tg (CPTG
uid 8408,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8409,0
va (VaSet
)
xt "89000,79500,95600,80500"
st "data_valid_ack"
blo "89000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid_ack"
t "std_logic"
o 22
suid 34,0
i "'0'"
)
)
)
*113 (CptPort
uid 8748,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8749,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,80625,124750,81375"
)
tg (CPTG
uid 8750,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8751,0
va (VaSet
)
xt "117800,80500,123000,81500"
st "sclk_enable"
ju 2
blo "123000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk_enable"
t "std_logic"
eolc "-- default DWRITE HIGH."
posAdd 0
o 45
suid 35,0
i "'1'"
)
)
)
*114 (CptPort
uid 9223,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9224,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,82625,124750,83375"
)
tg (CPTG
uid 9225,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9226,0
va (VaSet
)
xt "117500,82500,123000,83500"
st "ps_direction"
ju 2
blo "123000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_direction"
t "std_logic"
prec "------------------------------------------------------------------------------

-- ADC CLK generator, is able to shift phase with respect to X_50M
-- these signals control the behavior of the digital clock manager (DCM)
------------------------------------------------------------------------------"
eolc "-- default phase shift upwards"
preAdd 0
posAdd 0
o 49
suid 36,0
i "'1'"
)
)
)
*115 (CptPort
uid 9227,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9228,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,83625,124750,84375"
)
tg (CPTG
uid 9229,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9230,0
va (VaSet
)
xt "114900,83500,123000,84500"
st "ps_do_phase_shift"
ju 2
blo "123000,84300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 50
suid 37,0
i "'0'"
)
)
)
*116 (CptPort
uid 9933,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9934,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,84625,124750,85375"
)
tg (CPTG
uid 9935,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9936,0
va (VaSet
)
xt "119300,84500,123000,85500"
st "ps_reset"
ju 2
blo "123000,85300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 51
suid 38,0
i "'0'"
)
)
)
*117 (CptPort
uid 9937,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9938,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,87625,124750,88375"
)
tg (CPTG
uid 9939,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9940,0
va (VaSet
)
xt "117400,87500,123000,88500"
st "srclk_enable"
ju 2
blo "123000,88300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "srclk_enable"
t "std_logic"
eolc "-- default SRCLK on."
posAdd 0
o 46
suid 39,0
i "'1'"
)
)
)
*118 (CptPort
uid 10619,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10620,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,90625,124750,91375"
)
tg (CPTG
uid 10621,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10622,0
va (VaSet
)
xt "115800,90500,123000,91500"
st "socks_connected"
ju 2
blo "123000,91300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socks_connected"
t "std_logic"
posc "------------------------------------------------------------------------------"
posAdd 0
o 54
suid 42,0
)
)
)
*119 (CptPort
uid 10623,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10624,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,91625,124750,92375"
)
tg (CPTG
uid 10625,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10626,0
va (VaSet
)
xt "116900,91500,123000,92500"
st "socks_waiting"
ju 2
blo "123000,92300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socks_waiting"
t "std_logic"
prec "------------------------------------------------------------------------------

-- signals used to control FAD LED bahavior:
-- one of the three LEDs is used for com-status info
------------------------------------------------------------------------------"
preAdd 0
o 53
suid 43,0
)
)
)
*120 (CptPort
uid 11838,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11839,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,92625,124750,93375"
)
tg (CPTG
uid 11840,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11841,0
va (VaSet
)
xt "116700,92500,123000,93500"
st "trigger_enable"
ju 2
blo "123000,93300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_enable"
t "std_logic"
prec "------------------------------------------------------------------------------

-- user controllable enable signals
------------------------------------------------------------------------------"
preAdd 0
posAdd 0
o 42
suid 44,0
)
)
)
*121 (CptPort
uid 13149,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13150,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,66625,88000,67375"
)
tg (CPTG
uid 13151,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13152,0
va (VaSet
)
xt "89000,66500,96200,67500"
st "c_trigger_enable"
blo "89000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 28
suid 45,0
i "'0'"
)
)
)
*122 (CptPort
uid 13153,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13154,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,67625,88000,68375"
)
tg (CPTG
uid 13155,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13156,0
va (VaSet
)
xt "89000,67500,98800,68500"
st "c_trigger_mult : (15:0)"
blo "89000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
eolc "--subject to changes"
posAdd 0
o 29
suid 46,0
i "conv_std_logic_vector(0 ,16)"
)
)
)
*123 (CptPort
uid 13806,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13807,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,94625,88000,95375"
)
tg (CPTG
uid 13808,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13809,0
va (VaSet
)
xt "89000,94500,97000,95500"
st "MAC_jumper : (1:0)"
blo "89000,95300"
)
)
thePort (LogicalPort
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 downto 0)"
prec "------------------------------------------------------------------------------

-- MAC/IP calculation signals:
------------------------------------------------------------------------------"
preAdd 0
o 39
suid 48,0
)
)
)
*124 (CptPort
uid 13911,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13912,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,95625,88000,96375"
)
tg (CPTG
uid 13913,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13914,0
va (VaSet
)
xt "89000,95500,95500,96500"
st "BoardID : (3:0)"
blo "89000,96300"
)
)
thePort (LogicalPort
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 downto 0)"
o 40
suid 49,0
)
)
)
*125 (CptPort
uid 13915,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13916,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,96625,88000,97375"
)
tg (CPTG
uid 13917,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13918,0
va (VaSet
)
xt "89000,96500,95300,97500"
st "CrateID : (1:0)"
blo "89000,97300"
)
)
thePort (LogicalPort
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 downto 0)"
posAdd 0
o 41
suid 50,0
)
)
)
*126 (CptPort
uid 20877,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20878,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,118625,88000,119375"
)
tg (CPTG
uid 20879,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20880,0
va (VaSet
)
xt "89000,118500,94300,119500"
st "dac_setting"
blo "89000,119300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_setting"
t "dac_array_type"
prec "--data_generator_config_start_o	: out std_logic := '0';
--data_generator_config_valid_i	: in std_logic;"
eolc "--<<-- default defined in fad_definitions.vhd"
preAdd 0
posAdd 0
o 34
suid 54,0
i "DEFAULT_DAC"
)
)
)
*127 (CptPort
uid 20897,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20898,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,106625,88000,107375"
)
tg (CPTG
uid 20899,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20900,0
va (VaSet
)
xt "89000,106500,102800,107500"
st "memory_manager_config_start_o"
blo "89000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
prec "-- FAD configuration signals:
------------------------------------------------------------------------------"
preAdd 0
o 30
suid 59,0
i "'0'"
)
)
)
*128 (CptPort
uid 20901,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20902,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,107625,88000,108375"
)
tg (CPTG
uid 20903,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20904,0
va (VaSet
)
xt "89000,107500,102300,108500"
st "memory_manager_config_valid_i"
blo "89000,108300"
)
)
thePort (LogicalPort
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 31
suid 60,0
)
)
)
*129 (CptPort
uid 20905,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20906,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,119625,88000,120375"
)
tg (CPTG
uid 20907,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20908,0
va (VaSet
)
xt "89000,119500,94000,120500"
st "roi_setting"
blo "89000,120300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_setting"
t "roi_array_type"
eolc "--<<-- default defined in fad_definitions.vhd"
preAdd 0
posAdd 0
o 35
suid 61,0
i "DEFAULT_ROI"
)
)
)
*130 (CptPort
uid 20913,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20914,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,110625,88000,111375"
)
tg (CPTG
uid 20915,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20916,0
va (VaSet
)
xt "89000,110500,101400,111500"
st "spi_interface_config_start_o"
blo "89000,111300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 32
suid 63,0
i "'0'"
)
)
)
*131 (CptPort
uid 20917,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20918,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,111625,88000,112375"
)
tg (CPTG
uid 20919,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 20920,0
va (VaSet
)
xt "89000,111500,100900,112500"
st "spi_interface_config_valid_i"
blo "89000,112300"
)
)
thePort (LogicalPort
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
posAdd 0
o 33
suid 64,0
)
)
)
*132 (CptPort
uid 22782,0
ps "OnEdgeStrategy"
shape (Triangle
uid 22783,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,82625,88000,83375"
)
tg (CPTG
uid 22784,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 22785,0
va (VaSet
)
xt "89000,82500,96200,83500"
st "data_ram_empty"
blo "89000,83300"
)
)
thePort (LogicalPort
decl (Decl
n "data_ram_empty"
t "std_logic"
preAdd 0
o 38
suid 65,0
)
)
)
*133 (CptPort
uid 23829,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23830,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,85625,124750,86375"
)
tg (CPTG
uid 23831,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 23832,0
va (VaSet
)
xt "119200,85500,123000,86500"
st "ps_ready"
ju 2
blo "123000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "ps_ready"
t "std_logic"
o 52
suid 66,0
)
)
)
*134 (CptPort
uid 24969,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24970,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,120625,88000,121375"
)
tg (CPTG
uid 24971,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 24972,0
va (VaSet
)
xt "89000,120500,96600,121500"
st "runnumber : (31:0)"
blo "89000,121300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 36
suid 67,0
i "conv_std_logic_vector(0 ,32)"
)
)
)
*135 (CptPort
uid 25009,0
ps "OnEdgeStrategy"
shape (Triangle
uid 25010,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,93625,124750,94375"
)
tg (CPTG
uid 25011,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 25012,0
va (VaSet
)
xt "115800,93500,123000,94500"
st "reset_trigger_id"
ju 2
blo "123000,94300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 37
suid 68,0
i "'0'"
)
)
)
*136 (CptPort
uid 25284,0
ps "OnEdgeStrategy"
shape (Triangle
uid 25285,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,107625,124750,108375"
)
tg (CPTG
uid 25286,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 25287,0
va (VaSet
)
xt "117700,107500,123000,108500"
st "state : (7:0)"
ju 2
blo "123000,108300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 1
suid 69,0
)
)
)
*137 (CptPort
uid 25533,0
ps "OnEdgeStrategy"
shape (Triangle
uid 25534,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,108625,124750,109375"
)
tg (CPTG
uid 25535,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 25536,0
va (VaSet
)
xt "112600,108500,123000,109500"
st "debug_data_ram_empty"
ju 2
blo "123000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 2
suid 70,0
)
)
)
*138 (CptPort
uid 25537,0
ps "OnEdgeStrategy"
shape (Triangle
uid 25538,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,109625,124750,110375"
)
tg (CPTG
uid 25539,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 25540,0
va (VaSet
)
xt "115500,109500,123000,110500"
st "debug_data_valid"
ju 2
blo "123000,110300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 3
suid 71,0
)
)
)
*139 (CptPort
uid 26308,0
ps "OnEdgeStrategy"
shape (Triangle
uid 26309,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,91625,88000,92375"
)
tg (CPTG
uid 26310,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 26311,0
va (VaSet
)
xt "89000,91500,98700,92500"
st "data_generator_idle_i"
blo "89000,92300"
)
)
thePort (LogicalPort
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 4
suid 72,0
)
)
)
*140 (CptPort
uid 28264,0
ps "OnEdgeStrategy"
shape (Triangle
uid 28265,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,113625,124750,114375"
)
tg (CPTG
uid 28266,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 28267,0
va (VaSet
)
xt "111100,113500,123000,114500"
st "socket_tx_free_out : (16:0)"
ju 2
blo "123000,114300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 7
suid 73,0
)
)
)
*141 (CptPort
uid 30666,0
ps "OnEdgeStrategy"
shape (Triangle
uid 30667,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,114625,124750,115375"
)
tg (CPTG
uid 30668,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 30669,0
va (VaSet
)
xt "117600,114500,123000,115500"
st "busy_enable"
ju 2
blo "123000,115300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy_enable"
t "std_logic"
o 47
suid 74,0
i "'1'"
)
)
)
*142 (CptPort
uid 30670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 30671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,115625,124750,116375"
)
tg (CPTG
uid 30672,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 30673,0
va (VaSet
)
xt "112800,115500,123000,116500"
st "socket_send_mode_out"
ju 2
blo "123000,116300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_send_mode_out"
t "std_logic"
o 48
suid 75,0
)
)
)
*143 (CptPort
uid 32339,0
ps "OnEdgeStrategy"
shape (Triangle
uid 32340,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "124000,94625,124750,95375"
)
tg (CPTG
uid 32341,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 32342,0
va (VaSet
)
xt "117500,94500,123000,95500"
st "busy_manual"
ju 2
blo "123000,95300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy_manual"
t "std_logic"
o 6
suid 76,0
)
)
)
*144 (CptPort
uid 32343,0
ps "OnEdgeStrategy"
shape (Triangle
uid 32344,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "87250,100625,88000,101375"
)
tg (CPTG
uid 32345,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 32346,0
va (VaSet
)
xt "89000,100500,96900,101500"
st "data_ram_not_full"
blo "89000,101300"
)
)
thePort (LogicalPort
decl (Decl
n "data_ram_not_full"
t "std_logic"
o 5
suid 77,0
)
)
)
]
shape (Rectangle
uid 1607,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "88000,53000,124000,123000"
)
oxt "43000,2000,56000,22000"
ttg (MlTextGroup
uid 1608,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*145 (Text
uid 1609,0
va (VaSet
font "Arial,8,1"
)
xt "103700,117000,109900,118000"
st "FACT_FAD_lib"
blo "103700,117800"
tm "BdLibraryNameMgr"
)
*146 (Text
uid 1610,0
va (VaSet
font "Arial,8,1"
)
xt "103700,118000,109400,119000"
st "w5300_modul"
blo "103700,118800"
tm "CptNameMgr"
)
*147 (Text
uid 1611,0
va (VaSet
font "Arial,8,1"
)
xt "103700,119000,113300,120000"
st "w5300_modul_instance"
blo "103700,119800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1612,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1613,0
text (MLText
uid 1614,0
va (VaSet
font "Courier New,8,0"
)
xt "88000,52200,115500,53000"
st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
)
viewicon (ZoomableIcon
uid 1615,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "88250,121250,89750,122750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*148 (Net
uid 1680,0
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 30,0
)
declText (MLText
uid 1681,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,11200,-140500,12000"
st "crate_id                     : std_logic_vector(1 DOWNTO 0)"
)
)
*149 (SaComponent
uid 1768,0
optionalChildren [
*150 (CptPort
uid 1760,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1761,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-41000,64625,-40250,65375"
)
tg (CPTG
uid 1762,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1763,0
va (VaSet
)
xt "-48800,64500,-42000,65500"
st "trigger_id : (31:0)"
ju 2
blo "-42000,65300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(31 downto 0)"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*151 (CptPort
uid 1764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-52750,64625,-52000,65375"
)
tg (CPTG
uid 1766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1767,0
va (VaSet
)
xt "-51000,64500,-48200,65500"
st "trigger"
blo "-51000,65300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*152 (CptPort
uid 6207,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6208,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-52750,63625,-52000,64375"
)
tg (CPTG
uid 6209,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6210,0
va (VaSet
)
xt "-51000,63500,-49500,64500"
st "clk"
blo "-51000,64300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "clk"
t "std_logic"
o 4
suid 3,0
)
)
)
*153 (CptPort
uid 23079,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23080,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-52750,65625,-52000,66375"
)
tg (CPTG
uid 23081,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23082,0
va (VaSet
)
xt "-50000,65500,-47600,66500"
st "reset"
blo "-50000,66300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "reset"
t "std_logic"
o 3
suid 4,0
)
)
)
]
shape (Rectangle
uid 1769,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-52000,63000,-41000,67000"
)
oxt "32000,2000,43000,12000"
ttg (MlTextGroup
uid 1770,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*154 (Text
uid 1771,0
va (VaSet
font "Arial,8,1"
)
xt "-50300,67000,-43700,68000"
st "FACT_FAD_LIB"
blo "-50300,67800"
tm "BdLibraryNameMgr"
)
*155 (Text
uid 1772,0
va (VaSet
font "Arial,8,1"
)
xt "-50300,68000,-43700,69000"
st "trigger_counter"
blo "-50300,68800"
tm "CptNameMgr"
)
*156 (Text
uid 1773,0
va (VaSet
font "Arial,8,1"
)
xt "-50300,69000,-39800,70000"
st "trigger_counter_instance"
blo "-50300,69800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1774,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1775,0
text (MLText
uid 1776,0
va (VaSet
font "Courier New,8,0"
)
xt "-52000,62000,-52000,62000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 1777,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-51750,65250,-50250,66750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*157 (Net
uid 2297,0
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 107
suid 36,0
)
declText (MLText
uid 2298,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,102800,-129000,103600"
st "SIGNAL ram_start_addr               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
)
)
*158 (Net
uid 2474,0
lang 2
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 139
suid 39,0
i "'0'"
)
declText (MLText
uid 2475,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,132400,-125500,133200"
st "SIGNAL wiz_write_ea                 : std_logic                                    := '0'"
)
)
*159 (Net
uid 2480,0
lang 2
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 142
suid 40,0
i "(others => '0')"
)
declText (MLText
uid 2481,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,134800,-119500,135600"
st "SIGNAL wiz_write_length             : std_logic_vector(16 downto 0)                := (others => '0')"
)
)
*160 (Net
uid 2486,0
lang 2
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
preAdd 0
o 138
suid 41,0
i "(others => '0')"
)
declText (MLText
uid 2487,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,130800,-119500,131600"
st "SIGNAL wiz_ram_start_addr           : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
)
)
*161 (Net
uid 2492,0
lang 2
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 137
suid 42,0
i "(others => '0')"
)
declText (MLText
uid 2493,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,130000,-119500,130800"
st "SIGNAL wiz_number_of_channels       : std_logic_vector(3 downto 0)                 := (others => '0')"
)
)
*162 (Net
uid 2498,0
lang 2
decl (Decl
n "wiz_write_end"
t "std_logic"
o 140
suid 43,0
i "'0'"
)
declText (MLText
uid 2499,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,133200,-125500,134000"
st "SIGNAL wiz_write_end                : std_logic                                    := '0'"
)
)
*163 (Net
uid 2504,0
lang 2
decl (Decl
n "wiz_write_header"
t "std_logic"
o 141
suid 44,0
i "'0'"
)
declText (MLText
uid 2505,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,134000,-125500,134800"
st "SIGNAL wiz_write_header             : std_logic                                    := '0'"
)
)
*164 (Net
uid 2574,0
decl (Decl
n "ram_write_ea"
t "std_logic"
o 108
suid 48,0
)
declText (MLText
uid 2575,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,103600,-146500,104400"
st "SIGNAL ram_write_ea                 : std_logic"
)
)
*165 (Net
uid 2580,0
decl (Decl
n "ram_write_ready"
t "std_logic"
o 109
suid 49,0
i "'0'"
)
declText (MLText
uid 2581,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,104400,-125500,105200"
st "SIGNAL ram_write_ready              : std_logic                                    := '0'"
)
)
*166 (Net
uid 2598,0
decl (Decl
n "roi_max"
t "roi_max_type"
o 114
suid 52,0
)
declText (MLText
uid 2599,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,108400,-145000,109200"
st "SIGNAL roi_max                      : roi_max_type"
)
)
*167 (Net
uid 2640,0
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 101
suid 54,0
)
declText (MLText
uid 2641,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,98000,-136500,98800"
st "SIGNAL package_length               : std_logic_vector(15 downto 0)"
)
)
*168 (Net
uid 2776,0
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 57,0
i "'1'"
)
declText (MLText
uid 2777,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,24000,-129000,24800"
st "adc_oeb                      : std_logic                                    := '1'"
)
)
*169 (PortIoOut
uid 2798,0
shape (CompositeShape
uid 2799,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2800,0
sl 0
ro 90
xt "-71000,93625,-69500,94375"
)
(Line
uid 2801,0
sl 0
ro 90
xt "-69500,94000,-69000,94000"
pts [
"-69000,94000"
"-69500,94000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2802,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2803,0
va (VaSet
)
xt "-75200,93500,-72000,94500"
st "adc_oeb"
ju 2
blo "-72000,94300"
tm "WireNameMgr"
)
)
)
*170 (PortIoIn
uid 2804,0
shape (CompositeShape
uid 2805,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2806,0
sl 0
ro 270
xt "-68000,85625,-66500,86375"
)
(Line
uid 2807,0
sl 0
ro 270
xt "-66500,86000,-66000,86000"
pts [
"-66500,86000"
"-66000,86000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2808,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2809,0
va (VaSet
)
xt "-74400,85500,-69000,86500"
st "adc_otr_array"
ju 2
blo "-69000,86300"
tm "WireNameMgr"
)
)
)
*171 (PortIoIn
uid 2950,0
shape (CompositeShape
uid 2951,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2952,0
sl 0
ro 270
xt "-71000,96625,-69500,97375"
)
(Line
uid 2953,0
sl 0
ro 270
xt "-69500,97000,-69000,97000"
pts [
"-69500,97000"
"-69000,97000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2954,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2955,0
va (VaSet
)
xt "-75300,96500,-72000,97500"
st "board_id"
ju 2
blo "-72000,97300"
tm "WireNameMgr"
)
)
)
*172 (PortIoIn
uid 2956,0
shape (CompositeShape
uid 2957,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2958,0
sl 0
ro 270
xt "-71000,97625,-69500,98375"
)
(Line
uid 2959,0
sl 0
ro 270
xt "-69500,98000,-69000,98000"
pts [
"-69500,98000"
"-69000,98000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2960,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2961,0
va (VaSet
)
xt "-75100,97500,-72000,98500"
st "crate_id"
ju 2
blo "-72000,98300"
tm "WireNameMgr"
)
)
)
*173 (Grouping
uid 3137,0
optionalChildren [
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uid 3139,0
shape (Rectangle
uid 3140,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "85000,178000,102000,179000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 3141,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "85200,178000,94900,179000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*175 (CommentText
uid 3142,0
shape (Rectangle
uid 3143,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "102000,174000,106000,175000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 3144,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "102200,174000,105200,175000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*176 (CommentText
uid 3145,0
shape (Rectangle
uid 3146,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "85000,176000,102000,177000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 3147,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "85200,176000,95200,177000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*177 (CommentText
uid 3148,0
shape (Rectangle
uid 3149,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "81000,176000,85000,177000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 3150,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "81200,176000,83300,177000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*178 (CommentText
uid 3151,0
shape (Rectangle
uid 3152,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "102000,175000,122000,179000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 3153,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "102200,175200,111400,176200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*179 (CommentText
uid 3154,0
shape (Rectangle
uid 3155,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "106000,174000,122000,175000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 3156,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "106200,174000,110700,175000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*180 (CommentText
uid 3157,0
shape (Rectangle
uid 3158,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "81000,174000,102000,176000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 3159,0
va (VaSet
fg "32768,0,0"
)
xt "88700,174000,94300,176000"
st "
TU Dortmund 
Physik / EE
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*181 (CommentText
uid 3160,0
shape (Rectangle
uid 3161,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "81000,177000,85000,178000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 3162,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "81200,177000,83300,178000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*182 (CommentText
uid 3163,0
shape (Rectangle
uid 3164,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "81000,178000,85000,179000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 3165,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "81200,178000,83900,179000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*183 (CommentText
uid 3166,0
shape (Rectangle
uid 3167,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "85000,177000,102000,178000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 3168,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "85200,177000,97600,178000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 3138,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "81000,174000,122000,179000"
)
oxt "14000,66000,55000,71000"
)
*184 (Net
uid 3894,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 81,0
)
declText (MLText
uid 3895,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,16000,-150000,16800"
st "CLK_25_PS                    : std_logic"
)
)
*185 (PortIoOut
uid 3978,0
shape (CompositeShape
uid 3979,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3980,0
sl 0
ro 270
xt "-36500,23625,-35000,24375"
)
(Line
uid 3981,0
sl 0
ro 270
xt "-37000,24000,-36500,24000"
pts [
"-37000,24000"
"-36500,24000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3982,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3983,0
va (VaSet
)
xt "-35000,23500,-30500,24500"
st "CLK_25_PS"
blo "-35000,24300"
tm "WireNameMgr"
)
)
)
*186 (Net
uid 4068,0
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 90,0
)
declText (MLText
uid 4069,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,16800,-150000,17600"
st "CLK_50                       : std_logic"
)
)
*187 (Net
uid 4204,0
decl (Decl
n "CLK_25"
t "std_logic"
preAdd 0
posAdd 0
o 54
suid 91,0
)
declText (MLText
uid 4205,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,48400,-146500,49200"
st "SIGNAL CLK_25                       : std_logic"
)
)
*188 (PortIoOut
uid 4220,0
shape (CompositeShape
uid 4221,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4222,0
sl 0
ro 270
xt "-36500,21625,-35000,22375"
)
(Line
uid 4223,0
sl 0
ro 270
xt "-37000,22000,-36500,22000"
pts [
"-37000,22000"
"-36500,22000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4224,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4225,0
va (VaSet
)
xt "-35000,21500,-31900,22500"
st "CLK_50"
blo "-35000,22300"
tm "WireNameMgr"
)
)
)
*189 (Net
uid 4232,0
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 92,0
)
declText (MLText
uid 4233,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,3200,-150000,4000"
st "CLK                          : std_logic"
)
)
*190 (Net
uid 4260,0
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 95,0
)
declText (MLText
uid 4261,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,9600,-140500,10400"
st "adc_otr_array                : std_logic_vector(3 DOWNTO 0)"
)
)
*191 (Net
uid 4270,0
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 96,0
)
declText (MLText
uid 4271,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,8800,-145000,9600"
st "adc_data_array               : adc_data_array_type"
)
)
*192 (PortIoIn
uid 4307,0
shape (CompositeShape
uid 4308,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4309,0
sl 0
ro 270
xt "-68000,84625,-66500,85375"
)
(Line
uid 4310,0
sl 0
ro 270
xt "-66500,85000,-66000,85000"
pts [
"-66500,85000"
"-66000,85000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4311,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4312,0
va (VaSet
)
xt "-74900,84500,-69000,85500"
st "adc_data_array"
ju 2
blo "-69000,85300"
tm "WireNameMgr"
)
)
)
*193 (Net
uid 4399,0
decl (Decl
n "drs_clk_en"
t "std_logic"
o 85
suid 97,0
i "'0'"
)
declText (MLText
uid 4400,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,82800,-125500,83600"
st "SIGNAL drs_clk_en                   : std_logic                                    := '0'"
)
)
*194 (Net
uid 4405,0
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 91
suid 98,0
)
declText (MLText
uid 4406,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,89200,-140500,90000"
st "SIGNAL drs_s_cell_array             : drs_s_cell_array_type"
)
)
*195 (Net
uid 4417,0
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 86
suid 100,0
i "'0'"
)
declText (MLText
uid 4418,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,83600,-125500,84400"
st "SIGNAL drs_read_s_cell              : std_logic                                    := '0'"
)
)
*196 (Net
uid 4535,0
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 109,0
i "(others => '0')"
)
declText (MLText
uid 4536,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,31200,-123000,32000"
st "drs_channel_id               : std_logic_vector(3 downto 0)                 := (others => '0')"
)
)
*197 (Net
uid 4543,0
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 110,0
i "'1'"
)
declText (MLText
uid 4544,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,32000,-129000,32800"
st "drs_dwrite                   : std_logic                                    := '1'"
)
)
*198 (PortIoOut
uid 4551,0
shape (CompositeShape
uid 4552,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4553,0
sl 0
ro 90
xt "-31000,69625,-29500,70375"
)
(Line
uid 4554,0
sl 0
ro 90
xt "-29500,70000,-29000,70000"
pts [
"-29000,70000"
"-29500,70000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4555,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4556,0
va (VaSet
)
xt "-37900,69500,-32000,70500"
st "drs_channel_id"
ju 2
blo "-32000,70300"
tm "WireNameMgr"
)
)
)
*199 (PortIoOut
uid 4557,0
shape (CompositeShape
uid 4558,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4559,0
sl 0
ro 90
xt "-100000,76625,-98500,77375"
)
(Line
uid 4560,0
sl 0
ro 90
xt "-98500,77000,-98000,77000"
pts [
"-98000,77000"
"-98500,77000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4561,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4562,0
va (VaSet
)
xt "-105300,76500,-101000,77500"
st "drs_dwrite"
ju 2
blo "-101000,77300"
tm "WireNameMgr"
)
)
)
*200 (Net
uid 4669,0
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 112,0
)
declText (MLText
uid 4670,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,5600,-150000,6400"
st "SROUT_in_0                   : std_logic"
)
)
*201 (Net
uid 4677,0
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 113,0
)
declText (MLText
uid 4678,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,6400,-150000,7200"
st "SROUT_in_1                   : std_logic"
)
)
*202 (Net
uid 4685,0
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 114,0
)
declText (MLText
uid 4686,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,7200,-150000,8000"
st "SROUT_in_2                   : std_logic"
)
)
*203 (Net
uid 4693,0
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 115,0
)
declText (MLText
uid 4694,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,8000,-150000,8800"
st "SROUT_in_3                   : std_logic"
)
)
*204 (PortIoIn
uid 4701,0
shape (CompositeShape
uid 4702,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4703,0
sl 0
ro 270
xt "-68000,49625,-66500,50375"
)
(Line
uid 4704,0
sl 0
ro 270
xt "-66500,50000,-66000,50000"
pts [
"-66500,50000"
"-66000,50000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4705,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4706,0
va (VaSet
)
xt "-74400,49500,-69000,50500"
st "SROUT_in_0"
ju 2
blo "-69000,50300"
tm "WireNameMgr"
)
)
)
*205 (PortIoIn
uid 4707,0
shape (CompositeShape
uid 4708,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4709,0
sl 0
ro 270
xt "-68000,50625,-66500,51375"
)
(Line
uid 4710,0
sl 0
ro 270
xt "-66500,51000,-66000,51000"
pts [
"-66500,51000"
"-66000,51000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4711,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4712,0
va (VaSet
)
xt "-74400,50500,-69000,51500"
st "SROUT_in_1"
ju 2
blo "-69000,51300"
tm "WireNameMgr"
)
)
)
*206 (PortIoIn
uid 4713,0
shape (CompositeShape
uid 4714,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4715,0
sl 0
ro 270
xt "-68000,51625,-66500,52375"
)
(Line
uid 4716,0
sl 0
ro 270
xt "-66500,52000,-66000,52000"
pts [
"-66500,52000"
"-66000,52000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4717,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4718,0
va (VaSet
)
xt "-74400,51500,-69000,52500"
st "SROUT_in_2"
ju 2
blo "-69000,52300"
tm "WireNameMgr"
)
)
)
*207 (PortIoIn
uid 4719,0
shape (CompositeShape
uid 4720,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4721,0
sl 0
ro 270
xt "-68000,52625,-66500,53375"
)
(Line
uid 4722,0
sl 0
ro 270
xt "-66500,53000,-66000,53000"
pts [
"-66500,53000"
"-66000,53000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4723,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4724,0
va (VaSet
)
xt "-74400,52500,-69000,53500"
st "SROUT_in_3"
ju 2
blo "-69000,53300"
tm "WireNameMgr"
)
)
)
*208 (Net
uid 4741,0
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 87
suid 116,0
)
declText (MLText
uid 4742,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,84400,-146500,85200"
st "SIGNAL drs_read_s_cell_ready        : std_logic"
)
)
*209 (SaComponent
uid 4903,0
optionalChildren [
*210 (CptPort
uid 4867,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4868,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,47625,-58000,48375"
)
tg (CPTG
uid 4869,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4870,0
va (VaSet
)
xt "-57000,47500,-55100,48500"
st "CLK"
blo "-57000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
)
)
)
*211 (CptPort
uid 4871,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4872,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,51625,-38250,52375"
)
tg (CPTG
uid 4873,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4874,0
va (VaSet
)
xt "-47500,51500,-40000,52500"
st "start_endless_mode"
ju 2
blo "-40000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "start_endless_mode"
t "std_logic"
o 2
)
)
)
*212 (CptPort
uid 4875,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4876,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,48625,-38250,49375"
)
tg (CPTG
uid 4877,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4878,0
va (VaSet
)
xt "-50200,48500,-40000,49500"
st "start_read_stop_pos_mode"
ju 2
blo "-40000,49300"
)
)
thePort (LogicalPort
decl (Decl
n "start_read_stop_pos_mode"
t "std_logic"
o 3
)
)
)
*213 (CptPort
uid 4879,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4880,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,49625,-58000,50375"
)
tg (CPTG
uid 4881,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4882,0
va (VaSet
)
xt "-57000,49500,-51600,50500"
st "SROUT_in_0"
blo "-57000,50300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
)
)
)
*214 (CptPort
uid 4883,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4884,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,50625,-58000,51375"
)
tg (CPTG
uid 4885,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4886,0
va (VaSet
)
xt "-57000,50500,-51600,51500"
st "SROUT_in_1"
blo "-57000,51300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
)
)
)
*215 (CptPort
uid 4887,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4888,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,51625,-58000,52375"
)
tg (CPTG
uid 4889,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4890,0
va (VaSet
)
xt "-57000,51500,-51600,52500"
st "SROUT_in_2"
blo "-57000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
)
)
)
*216 (CptPort
uid 4891,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4892,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,52625,-58000,53375"
)
tg (CPTG
uid 4893,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4894,0
va (VaSet
)
xt "-57000,52500,-51600,53500"
st "SROUT_in_3"
blo "-57000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
)
)
)
*217 (CptPort
uid 4895,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4896,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,50625,-38250,51375"
)
tg (CPTG
uid 4897,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4898,0
va (VaSet
)
xt "-43400,50500,-40000,51500"
st "stop_pos"
ju 2
blo "-40000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "stop_pos"
t "drs_s_cell_array_type"
o 8
)
)
)
*218 (CptPort
uid 4899,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4900,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,49625,-38250,50375"
)
tg (CPTG
uid 4901,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4902,0
va (VaSet
)
xt "-45700,49500,-40000,50500"
st "stop_pos_valid"
ju 2
blo "-40000,50300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "stop_pos_valid"
t "std_logic"
o 9
i "'0'"
)
)
)
*219 (CptPort
uid 4938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4939,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,53625,-58000,54375"
)
tg (CPTG
uid 4940,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4941,0
va (VaSet
)
xt "-57000,53500,-52800,54500"
st "RSRLOAD"
blo "-57000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 15
i "'0'"
)
)
)
*220 (CptPort
uid 4942,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4943,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,54625,-58000,55375"
)
tg (CPTG
uid 4944,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4945,0
va (VaSet
)
xt "-57000,54500,-54000,55500"
st "SRCLK"
blo "-57000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 16
i "'0'"
)
)
)
*221 (CptPort
uid 10272,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10273,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,59625,-38250,60375"
)
tg (CPTG
uid 10274,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10275,0
va (VaSet
)
xt "-46100,59500,-40000,60500"
st "srin_data : (7:0)"
ju 2
blo "-40000,60300"
)
)
thePort (LogicalPort
decl (Decl
n "srin_data"
t "std_logic_vector"
b "(7 downto 0)"
o 13
)
)
)
*222 (CptPort
uid 10276,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10277,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,59625,-58000,60375"
)
tg (CPTG
uid 10278,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10279,0
va (VaSet
)
xt "-57000,59500,-53300,60500"
st "SRIN_out"
blo "-57000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 14
i "'0'"
)
)
)
*223 (CptPort
uid 10280,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10281,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,57625,-38250,58375"
)
tg (CPTG
uid 10282,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10283,0
va (VaSet
)
xt "-45600,57500,-40000,58500"
st "srin_write_ack"
ju 2
blo "-40000,58300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "srin_write_ack"
t "std_logic"
o 12
i "'0'"
)
)
)
*224 (CptPort
uid 10284,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10285,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,58625,-38250,59375"
)
tg (CPTG
uid 10286,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10287,0
va (VaSet
)
xt "-46300,58500,-40000,59500"
st "srin_write_ready"
ju 2
blo "-40000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "srin_write_ready"
t "std_logic"
o 11
i "'0'"
)
)
)
*225 (CptPort
uid 10288,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10289,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-39000,56625,-38250,57375"
)
tg (CPTG
uid 10290,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10291,0
va (VaSet
)
xt "-47200,56500,-40000,57500"
st "start_srin_write_8b"
ju 2
blo "-40000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "start_srin_write_8b"
t "std_logic"
o 10
)
)
)
]
shape (Rectangle
uid 4904,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-58000,47000,-39000,62000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4905,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*226 (Text
uid 4906,0
va (VaSet
font "Arial,8,1"
)
xt "-52400,44000,-45800,45000"
st "FACT_FAD_LIB"
blo "-52400,44800"
tm "BdLibraryNameMgr"
)
*227 (Text
uid 4907,0
va (VaSet
font "Arial,8,1"
)
xt "-52400,45000,-47700,46000"
st "drs_pulser"
blo "-52400,45800"
tm "CptNameMgr"
)
*228 (Text
uid 4908,0
va (VaSet
font "Arial,8,1"
)
xt "-52400,46000,-44900,47000"
st "I_main_drs_pulser"
blo "-52400,46800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4909,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4910,0
text (MLText
uid 4911,0
va (VaSet
font "Courier New,8,0"
)
xt "-48500,49000,-48500,49000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 4912,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-57750,60250,-56250,61750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*229 (Net
uid 4946,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 117,0
i "'0'"
)
declText (MLText
uid 4947,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,21600,-129000,22400"
st "RSRLOAD                      : std_logic                                    := '0'"
)
)
*230 (PortIoOut
uid 4954,0
shape (CompositeShape
uid 4955,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4956,0
sl 0
ro 90
xt "-68000,53625,-66500,54375"
)
(Line
uid 4957,0
sl 0
ro 90
xt "-66500,54000,-66000,54000"
pts [
"-66000,54000"
"-66500,54000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4958,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4959,0
va (VaSet
)
xt "-73200,53500,-69000,54500"
st "RSRLOAD"
ju 2
blo "-69000,54300"
tm "WireNameMgr"
)
)
)
*231 (Net
uid 4960,0
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 118,0
i "'0'"
)
declText (MLText
uid 4961,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,22400,-129000,23200"
st "SRCLK                        : std_logic                                    := '0'"
)
)
*232 (PortIoOut
uid 4968,0
shape (CompositeShape
uid 4969,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4970,0
sl 0
ro 90
xt "-75000,56625,-73500,57375"
)
(Line
uid 4971,0
sl 0
ro 90
xt "-73500,57000,-73000,57000"
pts [
"-73000,57000"
"-73500,57000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4972,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4973,0
va (VaSet
)
xt "-79000,56500,-76000,57500"
st "SRCLK"
ju 2
blo "-76000,57300"
tm "WireNameMgr"
)
)
)
*233 (Net
uid 5220,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 133,0
i "(OTHERS => '0')"
)
declText (MLText
uid 5221,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,33600,-123000,34400"
st "led                          : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
)
)
*234 (Net
uid 5472,0
decl (Decl
n "sensor_ready"
t "std_logic"
o 122
suid 140,0
)
declText (MLText
uid 5473,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,114800,-146500,115600"
st "SIGNAL sensor_ready                 : std_logic"
)
)
*235 (Net
uid 5478,0
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 121
suid 141,0
)
declText (MLText
uid 5479,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,114000,-142500,114800"
st "SIGNAL sensor_array                 : sensor_array_type"
)
)
*236 (Net
uid 5632,0
lang 10
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 63
suid 146,0
)
declText (MLText
uid 5633,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,59600,-137000,60400"
st "SIGNAL adc_otr                      : std_logic_vector(3 DOWNTO 0)"
)
)
*237 (Net
uid 5640,0
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 62
suid 147,0
)
declText (MLText
uid 5641,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,58800,-141500,59600"
st "SIGNAL adc_data_array_int           : adc_data_array_type"
)
)
*238 (SaComponent
uid 5678,0
optionalChildren [
*239 (CptPort
uid 5658,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5659,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,84625,-58000,85375"
)
tg (CPTG
uid 5660,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5661,0
va (VaSet
font "arial,8,0"
)
xt "-57000,84500,-51100,85500"
st "adc_data_array"
blo "-57000,85300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 2
suid 5,0
)
)
)
*240 (CptPort
uid 5662,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5663,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-40000,84625,-39250,85375"
)
tg (CPTG
uid 5664,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5665,0
va (VaSet
font "arial,8,0"
)
xt "-48100,84500,-41000,85500"
st "adc_data_array_int"
ju 2
blo "-41000,85300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 4
suid 6,0
)
)
)
*241 (CptPort
uid 5666,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5667,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-40000,85625,-39250,86375"
)
tg (CPTG
uid 5668,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5669,0
va (VaSet
font "arial,8,0"
)
xt "-43900,85500,-41000,86500"
st "adc_otr"
ju 2
blo "-41000,86300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 7,0
)
)
)
*242 (CptPort
uid 5670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,85625,-58000,86375"
)
tg (CPTG
uid 5672,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5673,0
va (VaSet
font "arial,8,0"
)
xt "-57000,85500,-51600,86500"
st "adc_otr_array"
blo "-57000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 3
suid 8,0
)
)
)
*243 (CptPort
uid 5674,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5675,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-58750,82625,-58000,83375"
)
tg (CPTG
uid 5676,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5677,0
va (VaSet
font "arial,8,0"
)
xt "-57000,82500,-54500,83500"
st "clk_ps"
blo "-57000,83300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "clk_ps"
t "std_logic"
o 1
suid 9,0
)
)
)
]
shape (Rectangle
uid 5679,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-58000,82000,-40000,90000"
)
oxt "15000,6000,23000,11000"
ttg (MlTextGroup
uid 5680,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*244 (Text
uid 5681,0
va (VaSet
font "arial,8,1"
)
xt "-51100,86500,-44900,87500"
st "FACT_FAD_lib"
blo "-51100,87300"
tm "BdLibraryNameMgr"
)
*245 (Text
uid 5682,0
va (VaSet
font "arial,8,1"
)
xt "-51100,87500,-46300,88500"
st "adc_buffer"
blo "-51100,88300"
tm "CptNameMgr"
)
*246 (Text
uid 5683,0
va (VaSet
font "arial,8,1"
)
xt "-51100,88500,-43500,89500"
st "I_main_adc_buffer"
blo "-51100,89300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5684,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5685,0
text (MLText
uid 5686,0
va (VaSet
font "Courier New,8,0"
)
xt "-78000,82300,-78000,82300"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5687,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-57750,88250,-56250,89750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*247 (SaComponent
uid 5793,0
optionalChildren [
*248 (CptPort
uid 5753,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5754,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,128625,-19000,129375"
)
tg (CPTG
uid 5755,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5756,0
va (VaSet
)
xt "-18000,128500,-16100,129500"
st "sclk"
blo "-18000,129300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 9
suid 1,0
)
)
)
*249 (CptPort
uid 5761,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5762,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-3000,128625,-2250,129375"
)
tg (CPTG
uid 5763,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5764,0
va (VaSet
)
xt "-7700,128500,-4000,129500"
st "dac_array"
ju 2
blo "-4000,129300"
)
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 3
suid 10,0
)
)
)
*250 (CptPort
uid 5765,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5766,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-3000,125625,-2250,126375"
)
tg (CPTG
uid 5767,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5768,0
va (VaSet
)
xt "-9100,125500,-4000,126500"
st "config_ready"
ju 2
blo "-4000,126300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 5
suid 11,0
)
)
)
*251 (CptPort
uid 5769,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5770,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-3000,124625,-2250,125375"
)
tg (CPTG
uid 5771,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5772,0
va (VaSet
)
xt "-8800,124500,-4000,125500"
st "config_start"
ju 2
blo "-4000,125300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 2
suid 12,0
)
)
)
*252 (CptPort
uid 5773,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5774,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-3000,121625,-2250,122375"
)
tg (CPTG
uid 5775,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5776,0
va (VaSet
)
xt "-9800,121500,-4000,122500"
st "sensor_array"
ju 2
blo "-4000,122300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 10
suid 13,0
)
)
)
*253 (CptPort
uid 5777,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5778,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-3000,120625,-2250,121375"
)
tg (CPTG
uid 5779,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5780,0
va (VaSet
)
xt "-9900,120500,-4000,121500"
st "sensor_ready"
ju 2
blo "-4000,121300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_ready"
t "std_logic"
o 12
suid 14,0
)
)
)
*254 (CptPort
uid 5781,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5782,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,124625,-19000,125375"
)
tg (CPTG
uid 5783,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5784,0
va (VaSet
)
xt "-18000,124500,-15200,125500"
st "dac_cs"
blo "-18000,125300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 7
suid 15,0
)
)
)
*255 (CptPort
uid 5785,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5786,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,123625,-19000,124375"
)
tg (CPTG
uid 5787,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5788,0
va (VaSet
)
xt "-18000,123500,-11000,124500"
st "sensor_cs : (3:0)"
blo "-18000,124300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 11
suid 16,0
)
)
)
*256 (CptPort
uid 5789,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5790,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,120625,-19000,121375"
)
tg (CPTG
uid 5791,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5792,0
va (VaSet
)
xt "-18000,120500,-13800,121500"
st "clk_50MHz"
blo "-18000,121300"
)
)
thePort (LogicalPort
decl (Decl
n "clk_50MHz"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 17,0
)
)
)
*257 (CptPort
uid 6154,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6155,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,126625,-19000,127375"
)
tg (CPTG
uid 6156,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6157,0
va (VaSet
)
xt "-18000,126500,-16000,127500"
st "mosi"
blo "-18000,127300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 8
suid 19,0
i "'0'"
)
)
)
*258 (CptPort
uid 6317,0
ps "OnEdgeStrategy"
shape (Diamond
uid 6318,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,127625,-19000,128375"
)
tg (CPTG
uid 6319,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6320,0
va (VaSet
)
xt "-18000,127500,-16000,128500"
st "miso"
blo "-18000,128300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "miso"
t "std_logic"
preAdd 0
posAdd 0
o 13
suid 20,0
)
)
)
*259 (CptPort
uid 20147,0
ps "OnEdgeStrategy"
shape (Triangle
uid 20148,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-3000,129625,-2250,130375"
)
tg (CPTG
uid 20149,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 20150,0
va (VaSet
)
xt "-10900,129500,-4000,130500"
st "current_dac_array"
ju 2
blo "-4000,130300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "current_dac_array"
t "dac_array_type"
o 6
suid 21,0
i "( others => 0)"
)
)
)
*260 (CptPort
uid 21545,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21546,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-19750,129625,-19000,130375"
)
tg (CPTG
uid 21547,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21548,0
va (VaSet
)
xt "-18000,129500,-12700,130500"
st "sclk_enable_i"
blo "-18000,130300"
)
)
thePort (LogicalPort
decl (Decl
n "sclk_enable_i"
t "std_logic"
o 4
suid 22,0
)
)
)
]
shape (Rectangle
uid 5794,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-19000,120000,-3000,133000"
)
oxt "15000,12000,30000,26000"
ttg (MlTextGroup
uid 5795,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*261 (Text
uid 5796,0
va (VaSet
font "Arial,8,1"
)
xt "-18800,137000,-12600,138000"
st "FACT_FAD_lib"
blo "-18800,137800"
tm "BdLibraryNameMgr"
)
*262 (Text
uid 5797,0
va (VaSet
font "Arial,8,1"
)
xt "-18800,138000,-13300,139000"
st "spi_interface"
blo "-18800,138800"
tm "CptNameMgr"
)
*263 (Text
uid 5798,0
va (VaSet
font "Arial,8,1"
)
xt "-18800,139000,-10000,140000"
st "I_main_SPI_interface"
blo "-18800,139800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5799,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5800,0
text (MLText
uid 5801,0
va (VaSet
font "Courier New,8,0"
)
xt "-34000,120000,-34000,120000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5802,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-18750,131250,-17250,132750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*264 (Net
uid 5811,0
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 151,0
)
declText (MLText
uid 5812,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,36800,-150000,37600"
st "sclk                         : std_logic"
)
)
*265 (Net
uid 5819,0
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 152,0
)
declText (MLText
uid 5820,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,44800,-150000,45600"
st "sio                          : std_logic"
)
)
*266 (Net
uid 5827,0
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 153,0
)
declText (MLText
uid 5828,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,28000,-150000,28800"
st "dac_cs                       : std_logic"
)
)
*267 (Net
uid 5835,0
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 154,0
)
declText (MLText
uid 5836,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,37600,-140500,38400"
st "sensor_cs                    : std_logic_vector(3 DOWNTO 0)"
)
)
*268 (PortIoOut
uid 5843,0
shape (CompositeShape
uid 5844,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5845,0
sl 0
ro 90
xt "-30000,128625,-28500,129375"
)
(Line
uid 5846,0
sl 0
ro 90
xt "-28500,129000,-28000,129000"
pts [
"-28000,129000"
"-28500,129000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5847,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5848,0
va (VaSet
)
xt "-32700,128500,-31000,129500"
st "sclk"
ju 2
blo "-31000,129300"
tm "WireNameMgr"
)
)
)
*269 (PortIoInOut
uid 5849,0
shape (CompositeShape
uid 5850,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
uid 5851,0
sl 0
ro 180
xt "-30000,127625,-28500,128375"
)
(Line
uid 5852,0
sl 0
ro 180
xt "-28500,128000,-28000,128000"
pts [
"-28000,128000"
"-28500,128000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5853,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5854,0
va (VaSet
)
xt "-32400,127500,-31000,128500"
st "sio"
ju 2
blo "-31000,128300"
tm "WireNameMgr"
)
)
)
*270 (PortIoOut
uid 5855,0
shape (CompositeShape
uid 5856,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5857,0
sl 0
ro 90
xt "-30000,124625,-28500,125375"
)
(Line
uid 5858,0
sl 0
ro 90
xt "-28500,125000,-28000,125000"
pts [
"-28000,125000"
"-28500,125000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5859,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5860,0
va (VaSet
)
xt "-33800,124500,-31000,125500"
st "dac_cs"
ju 2
blo "-31000,125300"
tm "WireNameMgr"
)
)
)
*271 (PortIoOut
uid 5861,0
shape (CompositeShape
uid 5862,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5863,0
sl 0
ro 90
xt "-30000,123625,-28500,124375"
)
(Line
uid 5864,0
sl 0
ro 90
xt "-28500,124000,-28000,124000"
pts [
"-28000,124000"
"-28500,124000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5865,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5866,0
va (VaSet
)
xt "-34900,123500,-31000,124500"
st "sensor_cs"
ju 2
blo "-31000,124300"
tm "WireNameMgr"
)
)
)
*272 (Net
uid 6158,0
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 162,0
i "'0'"
)
declText (MLText
uid 6159,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,35200,-129000,36000"
st "mosi                         : std_logic                                    := '0'"
)
)
*273 (PortIoOut
uid 6166,0
shape (CompositeShape
uid 6167,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6168,0
sl 0
ro 90
xt "-30000,126625,-28500,127375"
)
(Line
uid 6169,0
sl 0
ro 90
xt "-28500,127000,-28000,127000"
pts [
"-28000,127000"
"-28500,127000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6170,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6171,0
va (VaSet
)
xt "-33000,126500,-31000,127500"
st "mosi"
ju 2
blo "-31000,127300"
tm "WireNameMgr"
)
)
)
*274 (Net
uid 6360,0
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 166,0
i "'0'"
)
declText (MLText
uid 6361,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,30400,-115500,31200"
st "denable                      : std_logic                                    := '0' -- default domino wave off"
)
)
*275 (PortIoOut
uid 6368,0
shape (CompositeShape
uid 6369,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6370,0
sl 0
ro 270
xt "179500,87625,181000,88375"
)
(Line
uid 6371,0
sl 0
ro 270
xt "179000,88000,179500,88000"
pts [
"179000,88000"
"179500,88000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6372,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6373,0
va (VaSet
)
xt "182000,87500,185000,88500"
st "denable"
blo "182000,88300"
tm "WireNameMgr"
)
)
)
*276 (MWC
uid 6529,0
optionalChildren [
*277 (CptPort
uid 6501,0
optionalChildren [
*278 (Line
uid 6505,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-94000,77000,-93000,77000"
pts [
"-94000,77000"
"-93000,77000"
]
)
*279 (Property
uid 6506,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6502,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-94750,76625,-94000,77375"
)
tg (CPTG
uid 6503,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6504,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-73331,316342,-71531,317342"
st "dout"
blo "-73331,317142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 36
suid 1,0
i "'1'"
)
)
)
*280 (CptPort
uid 6507,0
optionalChildren [
*281 (Line
uid 6511,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-88999,76000,-88000,76000"
pts [
"-88000,76000"
"-88999,76000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6508,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-88000,75625,-87250,76375"
)
tg (CPTG
uid 6509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6510,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-70365,315294,-68565,316294"
st "din0"
ju 2
blo "-68565,316094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 95
suid 2,0
i "'1'"
)
)
)
*282 (CptPort
uid 6512,0
optionalChildren [
*283 (Line
uid 6516,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-88999,78000,-88000,78000"
pts [
"-88000,78000"
"-88999,78000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6513,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-88000,77625,-87250,78375"
)
tg (CPTG
uid 6514,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6515,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-70250,317700,-68450,318700"
st "din1"
ju 2
blo "-68450,318500"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
o 94
suid 3,0
i "'1'"
)
)
)
*284 (CommentGraphic
uid 6517,0
optionalChildren [
*285 (Property
uid 6519,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-89000,79000"
"-89000,79000"
]
uid 6518,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-89000,79000,-89000,79000"
)
oxt "11000,10000,11000,10000"
)
*286 (CommentGraphic
uid 6520,0
optionalChildren [
*287 (Property
uid 6522,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-89000,75000"
"-89000,75000"
]
uid 6521,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-89000,75000,-89000,75000"
)
oxt "11000,6000,11000,6000"
)
*288 (Grouping
uid 6523,0
optionalChildren [
*289 (CommentGraphic
uid 6525,0
shape (PolyLine2D
pts [
"-91000,75000"
"-89000,75000"
"-89000,79000"
"-91000,79000"
]
uid 6526,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-91000,75000,-89000,79000"
)
oxt "9000,6000,11000,10000"
)
*290 (CommentGraphic
uid 6527,0
shape (Arc2D
pts [
"-91000,79000"
"-93000,77000"
"-91000,75000"
]
uid 6528,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-93000,75000,-91000,79000"
)
oxt "7000,6000,9000,10000"
)
]
shape (GroupingShape
uid 6524,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "-93000,75000,-89000,79000"
)
oxt "7000,6000,11000,10000"
)
]
shape (Rectangle
uid 6530,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
lineWidth -1
)
xt "-94000,75000,-88000,79000"
fos 1
)
showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 6531,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*291 (Text
uid 6532,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-91500,75500,-86700,76500"
st "moduleware"
blo "-91500,76300"
)
*292 (Text
uid 6533,0
va (VaSet
font "arial,8,0"
)
xt "-91500,76500,-89900,77500"
st "and"
blo "-91500,77300"
)
*293 (Text
uid 6534,0
va (VaSet
font "arial,8,0"
)
xt "-91500,77500,-89100,78500"
st "and_5"
blo "-91500,78300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 6535,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 6536,0
text (MLText
uid 6537,0
va (VaSet
font "arial,8,0"
)
xt "-109000,66000,-109000,66000"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
de 1
visOptions (mwParamsVisibilityOptions
)
)
*294 (Net
uid 8746,0
decl (Decl
n "sclk_enable"
t "std_logic"
o 120
suid 194,0
)
declText (MLText
uid 8747,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,113200,-146500,114000"
st "SIGNAL sclk_enable                  : std_logic"
)
)
*295 (Net
uid 9004,0
lang 2
decl (Decl
n "adc_clk_en"
t "std_logic"
o 61
suid 195,0
)
declText (MLText
uid 9005,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,58000,-146500,58800"
st "SIGNAL adc_clk_en                   : std_logic"
)
)
*296 (SaComponent
uid 9175,0
optionalChildren [
*297 (CptPort
uid 9120,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9121,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-42000,21625,-41250,22375"
)
tg (CPTG
uid 9122,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9123,0
va (VaSet
font "arial,8,0"
)
xt "-46100,21500,-43000,22500"
st "CLK_50"
ju 2
blo "-43000,22300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 7
suid 2,0
)
)
)
*298 (CptPort
uid 9124,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9125,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-42000,22625,-41250,23375"
)
tg (CPTG
uid 9126,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9127,0
va (VaSet
font "arial,8,0"
)
xt "-46100,22500,-43000,23500"
st "CLK_25"
ju 2
blo "-43000,23300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25"
t "std_logic"
o 5
suid 3,0
)
)
)
*299 (CptPort
uid 9128,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9129,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-60750,21625,-60000,22375"
)
tg (CPTG
uid 9130,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9131,0
va (VaSet
font "arial,8,0"
)
xt "-59000,21500,-57100,22500"
st "CLK"
blo "-59000,22300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 6,0
)
)
)
*300 (CptPort
uid 9211,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9212,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-42000,23625,-41250,24375"
)
tg (CPTG
uid 9213,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9214,0
va (VaSet
font "arial,8,0"
)
xt "-47500,23500,-43000,24500"
st "CLK_25_PS"
ju 2
blo "-43000,24300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 6
suid 24,0
)
)
)
*301 (CptPort
uid 9215,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9216,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-60750,14625,-60000,15375"
)
tg (CPTG
uid 9217,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9218,0
va (VaSet
font "arial,8,0"
)
xt "-59000,14500,-55700,15500"
st "direction"
blo "-59000,15300"
)
)
thePort (LogicalPort
decl (Decl
n "direction"
t "std_logic"
o 3
suid 26,0
)
)
)
*302 (CptPort
uid 9219,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9220,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-60750,15625,-60000,16375"
)
tg (CPTG
uid 9221,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9222,0
va (VaSet
font "arial,8,0"
)
xt "-59000,15500,-56000,16500"
st "do_shift"
blo "-59000,16300"
)
)
thePort (LogicalPort
decl (Decl
n "do_shift"
t "std_logic"
o 4
suid 25,0
)
)
)
*303 (CptPort
uid 10030,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10031,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-60750,23625,-60000,24375"
)
tg (CPTG
uid 10032,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10033,0
va (VaSet
font "arial,8,0"
)
xt "-59000,23500,-55800,24500"
st "RST_IN"
blo "-59000,24300"
)
)
thePort (LogicalPort
decl (Decl
n "RST_IN"
t "std_logic"
o 2
suid 27,0
)
)
)
*304 (CptPort
uid 15170,0
ps "OnEdgeStrategy"
shape (Triangle
uid 15171,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-42000,14625,-41250,15375"
)
tg (CPTG
uid 15172,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 15173,0
va (VaSet
font "arial,8,0"
)
xt "-47800,14500,-43000,15500"
st "offset : (7:0)"
ju 2
blo "-43000,15300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 9
suid 28,0
i "(OTHERS => '0')"
)
)
)
*305 (CptPort
uid 23071,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23072,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-42000,15625,-41250,16375"
)
tg (CPTG
uid 23073,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 23074,0
va (VaSet
font "arial,8,0"
)
xt "-49100,15500,-43000,16500"
st "locked_status_o"
ju 2
blo "-43000,16300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "locked_status_o"
t "std_logic"
o 8
suid 29,0
)
)
)
*306 (CptPort
uid 23075,0
ps "OnEdgeStrategy"
shape (Triangle
uid 23076,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-42000,16625,-41250,17375"
)
tg (CPTG
uid 23077,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 23078,0
va (VaSet
font "arial,8,0"
)
xt "-48800,16500,-43000,17500"
st "ready_status_o"
ju 2
blo "-43000,17300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready_status_o"
t "std_logic"
o 10
suid 30,0
)
)
)
]
shape (Rectangle
uid 9176,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-60000,13000,-42000,27000"
)
oxt "28000,10000,46000,33000"
ttg (MlTextGroup
uid 9177,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*307 (Text
uid 9178,0
va (VaSet
font "arial,8,1"
)
xt "-55800,18000,-49600,19000"
st "FACT_FAD_lib"
blo "-55800,18800"
tm "BdLibraryNameMgr"
)
*308 (Text
uid 9179,0
va (VaSet
font "arial,8,1"
)
xt "-55800,19000,-45800,20000"
st "clock_generator_var_ps"
blo "-55800,19800"
tm "CptNameMgr"
)
*309 (Text
uid 9180,0
va (VaSet
font "arial,8,1"
)
xt "-55800,20000,-45200,21000"
st "clock_generator_instance"
blo "-55800,20800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9181,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9182,0
text (MLText
uid 9183,0
va (VaSet
font "Courier New,8,0"
)
xt "-75000,6000,-75000,6000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 9184,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-59750,25250,-58250,26750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*310 (Net
uid 9231,0
decl (Decl
n "ps_direction"
t "std_logic"
eolc "-- default phase shift upwards"
posAdd 0
o 102
suid 196,0
i "'1'"
)
declText (MLText
uid 9232,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,98800,-110000,99600"
st "SIGNAL ps_direction                 : std_logic                                    := '1' -- default phase shift upwards"
)
)
*311 (Net
uid 9239,0
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 103
suid 197,0
i "'0'"
)
declText (MLText
uid 9240,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,99600,-109000,100400"
st "SIGNAL ps_do_phase_shift            : std_logic                                    := '0' --pulse this to phase shift once"
)
)
*312 (Net
uid 9941,0
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 104
suid 221,0
i "'0'"
)
declText (MLText
uid 9942,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,100400,-101500,101200"
st "SIGNAL ps_reset                     : std_logic                                    := '0' -- pulse this to reset the variable phase shift"
)
)
*313 (Net
uid 9949,0
decl (Decl
n "srclk_enable"
t "std_logic"
o 128
suid 222,0
i "'0'"
)
declText (MLText
uid 9950,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,120400,-125500,121200"
st "SIGNAL srclk_enable                 : std_logic                                    := '0'"
)
)
*314 (MWC
uid 9957,0
optionalChildren [
*315 (CptPort
uid 9966,0
optionalChildren [
*316 (Line
uid 9970,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-72000,57000,-71000,57000"
pts [
"-72000,57000"
"-71000,57000"
]
)
*317 (Property
uid 9971,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9967,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-72750,56625,-72000,57375"
)
tg (CPTG
uid 9968,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9969,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-51331,296342,-49531,297342"
st "dout"
blo "-51331,297142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 24
i "'0'"
)
)
)
*318 (CptPort
uid 9972,0
optionalChildren [
*319 (Line
uid 9976,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-66999,56000,-66000,56000"
pts [
"-66000,56000"
"-66999,56000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9973,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-66000,55625,-65250,56375"
)
tg (CPTG
uid 9974,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9975,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-48365,295294,-46565,296294"
st "din0"
ju 2
blo "-46565,296094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 60
i "'0'"
)
)
)
*320 (CptPort
uid 9977,0
optionalChildren [
*321 (Line
uid 9981,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-67000,58000,-66000,58000"
pts [
"-66000,58000"
"-67000,58000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 9978,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-66000,57625,-65250,58375"
)
tg (CPTG
uid 9979,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9980,0
sl 0
va (VaSet
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ga (GenericAssociation
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prms (Property
pclass "params"
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va (VaSet
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decl (Decl
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t "std_logic_vector"
b "(7 downto 0)"
o 92
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i "(others => '0')"
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tg (WTG
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stg "STSignalDisplayStrategy"
f (Text
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ps "OnEdgeStrategy"
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ro 90
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xt "-125750,67625,-125000,68375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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xt "-128000,67700,-126200,68700"
st "din1"
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t "std_logic"
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o 14
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ps "OnEdgeStrategy"
shape (Triangle
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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tg (CPTG
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stg "VerticalLayoutStrategy"
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xt "-128115,65294,-126315,66294"
st "din0"
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uid 10361,0
layer 8
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shape (Arc2D
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shape (GroupingShape
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va (VaSet
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shape (PolyLine2D
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uid 10375,0
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uid 10378,0
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shape (Rectangle
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ttg (MlTextGroup
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va (VaSet
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va (VaSet
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ga (GenericAssociation
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matrix (Matrix
uid 10387,0
text (MLText
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va (VaSet
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xt "-140000,56000,-140000,56000"
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header ""
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elements [
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sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
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prms (Property
pclass "params"
pname "params"
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de 2
visOptions (mwParamsVisibilityOptions
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*363 (Net
uid 10627,0
decl (Decl
n "socks_connected"
t "std_logic"
o 123
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declText (MLText
uid 10628,0
va (VaSet
font "Courier New,8,0"
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xt "-172000,116400,-146500,117200"
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uid 10635,0
decl (Decl
n "socks_waiting"
t "std_logic"
o 124
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declText (MLText
uid 10636,0
va (VaSet
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xt "-172000,117200,-146500,118000"
st "SIGNAL socks_waiting                : std_logic"
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)
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uid 10721,0
decl (Decl
n "green"
t "std_logic"
o 37
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declText (MLText
uid 10722,0
va (VaSet
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xt "-172000,32800,-150000,33600"
st "green                        : std_logic"
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*366 (PortIoOut
uid 10729,0
shape (CompositeShape
uid 10730,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 10731,0
sl 0
ro 270
xt "113500,128625,115000,129375"
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(Line
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sl 0
ro 270
xt "113000,129000,113500,129000"
pts [
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stc 0
sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "116000,128500,118400,129500"
st "green"
blo "116000,129300"
tm "WireNameMgr"
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)
*367 (Net
uid 10735,0
decl (Decl
n "amber"
t "std_logic"
o 29
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declText (MLText
uid 10736,0
va (VaSet
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xt "-172000,26400,-150000,27200"
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uid 10743,0
shape (CompositeShape
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va (VaSet
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fg "0,0,32768"
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sl 0
ro 270
xt "113500,129625,115000,130375"
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sl 0
ro 270
xt "113000,130000,113500,130000"
pts [
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tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "116000,129500,118500,130500"
st "amber"
blo "116000,130300"
tm "WireNameMgr"
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decl (Decl
n "red"
t "std_logic"
o 41
suid 250,0
)
declText (MLText
uid 10750,0
va (VaSet
font "Courier New,8,0"
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xt "-172000,36000,-150000,36800"
st "red                          : std_logic"
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)
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shape (CompositeShape
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va (VaSet
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fg "0,0,32768"
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sl 0
ro 270
xt "113500,130625,115000,131375"
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ro 270
xt "113000,131000,113500,131000"
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)
stc 0
sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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xt "116000,130500,117500,131500"
st "red"
blo "116000,131300"
tm "WireNameMgr"
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*371 (SaComponent
uid 11209,0
optionalChildren [
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uid 11181,0
ps "OnEdgeStrategy"
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ro 90
va (VaSet
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xt "88250,128625,89000,129375"
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tg (CPTG
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va (VaSet
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xt "90000,128500,91900,129500"
st "CLK"
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)
thePort (LogicalPort
decl (Decl
n "CLK"
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ps "OnEdgeStrategy"
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ro 90
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xt "107000,128625,107750,129375"
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tg (CPTG
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va (VaSet
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xt "103600,128500,106000,129500"
st "green"
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blo "106000,129300"
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m 1
decl (Decl
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o 2
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ps "OnEdgeStrategy"
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ro 90
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xt "107000,129625,107750,130375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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xt "103500,129500,106000,130500"
st "amber"
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decl (Decl
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o 3
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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xt "107000,130625,107750,131375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "104500,130500,106000,131500"
st "red"
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blo "106000,131300"
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m 1
decl (Decl
n "red"
t "std_logic"
o 4
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uid 11197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11198,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,129625,89000,130375"
)
tg (CPTG
uid 11199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11200,0
va (VaSet
)
xt "90000,129500,92800,130500"
st "trigger"
blo "90000,130300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
o 6
)
)
)
*377 (CptPort
uid 11201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,130625,89000,131375"
)
tg (CPTG
uid 11203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11204,0
va (VaSet
)
xt "90000,130500,96100,131500"
st "socks_waiting"
blo "90000,131300"
)
)
thePort (LogicalPort
decl (Decl
n "socks_waiting"
t "std_logic"
o 11
)
)
)
*378 (CptPort
uid 11205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11206,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,131625,89000,132375"
)
tg (CPTG
uid 11207,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11208,0
va (VaSet
)
xt "90000,131500,97200,132500"
st "socks_connected"
blo "90000,132300"
)
)
thePort (LogicalPort
decl (Decl
n "socks_connected"
t "std_logic"
o 12
)
)
)
*379 (CptPort
uid 12693,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12694,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "107000,132625,107750,133375"
)
tg (CPTG
uid 12695,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 12696,0
va (VaSet
)
xt "97500,132500,106000,133500"
st "additional_flasher_out"
ju 2
blo "106000,133300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "additional_flasher_out"
t "std_logic"
o 5
)
)
)
*380 (CptPort
uid 22344,0
ps "OnEdgeStrategy"
shape (Triangle
uid 22345,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,132625,89000,133375"
)
tg (CPTG
uid 22346,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 22347,0
va (VaSet
)
xt "90000,132500,97000,133500"
st "refclk_too_high"
blo "90000,133300"
)
)
thePort (LogicalPort
decl (Decl
n "refclk_too_high"
t "std_logic"
o 9
)
)
)
*381 (CptPort
uid 22348,0
ps "OnEdgeStrategy"
shape (Triangle
uid 22349,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,133625,89000,134375"
)
tg (CPTG
uid 22350,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 22351,0
va (VaSet
)
xt "90000,133500,96600,134500"
st "refclk_too_low"
blo "90000,134300"
)
)
thePort (LogicalPort
decl (Decl
n "refclk_too_low"
t "std_logic"
o 10
)
)
)
*382 (CptPort
uid 30445,0
ps "OnEdgeStrategy"
shape (Triangle
uid 30446,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,134625,89000,135375"
)
tg (CPTG
uid 30447,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 30448,0
va (VaSet
)
xt "90000,134500,95600,135500"
st "trigger_veto"
blo "90000,135300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger_veto"
t "std_logic"
o 8
)
)
)
*383 (CptPort
uid 30449,0
ps "OnEdgeStrategy"
shape (Triangle
uid 30450,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88250,135625,89000,136375"
)
tg (CPTG
uid 30451,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 30452,0
va (VaSet
)
xt "90000,135500,96000,136500"
st "w5300_reset"
blo "90000,136300"
)
)
thePort (LogicalPort
decl (Decl
n "w5300_reset"
t "std_logic"
o 7
)
)
)
]
shape (Rectangle
uid 11210,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "89000,128000,107000,138000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11211,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*384 (Text
uid 11212,0
va (VaSet
font "Arial,8,1"
)
xt "90900,139000,97100,140000"
st "FACT_FAD_lib"
blo "90900,139800"
tm "BdLibraryNameMgr"
)
*385 (Text
uid 11213,0
va (VaSet
font "Arial,8,1"
)
xt "90900,140000,96800,141000"
st "led_controller"
blo "90900,140800"
tm "CptNameMgr"
)
*386 (Text
uid 11214,0
va (VaSet
font "Arial,8,1"
)
xt "90900,141000,100700,142000"
st "led_controller_instance"
blo "90900,141800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11215,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11216,0
text (MLText
uid 11217,0
va (VaSet
font "Courier New,8,0"
)
xt "89000,125600,115500,127200"
st "HEARTBEAT_PWM_DIVIDER = 50000       ( integer )  
WAITING_DIVIDER       = 50000000    ( integer )  "
)
header ""
)
elements [
(GiElement
name "HEARTBEAT_PWM_DIVIDER"
type "integer"
value "50000"
)
(GiElement
name "WAITING_DIVIDER"
type "integer"
value "50000000"
)
]
)
viewicon (ZoomableIcon
uid 11218,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "89250,136250,90750,137750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*387 (Net
uid 11403,0
decl (Decl
n "drs_readout_started"
t "std_logic"
o 90
suid 252,0
)
declText (MLText
uid 11404,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,88400,-146500,89200"
st "SIGNAL drs_readout_started          : std_logic"
)
)
*388 (Net
uid 11856,0
decl (Decl
n "trigger_enable"
t "std_logic"
o 133
suid 254,0
)
declText (MLText
uid 11857,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,126000,-146500,126800"
st "SIGNAL trigger_enable               : std_logic"
)
)
*389 (MWC
uid 12295,0
optionalChildren [
*390 (CptPort
uid 12267,0
optionalChildren [
*391 (Line
uid 12271,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-114000,70000,-113000,70000"
pts [
"-113000,70000"
"-114000,70000"
]
)
*392 (Property
uid 12272,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 12268,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-113000,69625,-112250,70375"
)
tg (CPTG
uid 12269,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 12270,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-111581,69342,-109781,70342"
st "dout"
ju 2
blo "-109781,70142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
preAdd 0
posAdd 0
o 145
suid 1,0
)
)
)
*393 (CptPort
uid 12273,0
optionalChildren [
*394 (Line
uid 12277,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-119000,69000,-117999,69000"
pts [
"-119000,69000"
"-117999,69000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 12274,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-119750,68625,-119000,69375"
)
tg (CPTG
uid 12275,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12276,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-122115,68294,-120315,69294"
st "din0"
blo "-122115,69094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
preAdd 0
posAdd 0
o 135
suid 2,0
)
)
)
*395 (CptPort
uid 12278,0
optionalChildren [
*396 (Line
uid 12282,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-119000,71000,-117999,71000"
pts [
"-119000,71000"
"-117999,71000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 12279,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-119750,70625,-119000,71375"
)
tg (CPTG
uid 12280,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12281,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-122000,70700,-120200,71700"
st "din1"
blo "-122000,71500"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
o 133
suid 3,0
)
)
)
*397 (CommentGraphic
uid 12283,0
optionalChildren [
*398 (Property
uid 12285,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-118000,72000"
"-118000,72000"
]
uid 12284,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-118000,72000,-118000,72000"
)
oxt "7000,10000,7000,10000"
)
*399 (CommentGraphic
uid 12286,0
optionalChildren [
*400 (Property
uid 12288,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"-118000,68000"
"-118000,68000"
]
uid 12287,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-118000,68000,-118000,68000"
)
oxt "7000,6000,7000,6000"
)
*401 (Grouping
uid 12289,0
optionalChildren [
*402 (CommentGraphic
uid 12291,0
shape (PolyLine2D
pts [
"-116000,72000"
"-118000,72000"
"-118000,68000"
"-116000,68000"
]
uid 12292,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-118000,68000,-116000,72000"
)
oxt "7000,6000,9000,10000"
)
*403 (CommentGraphic
uid 12293,0
shape (Arc2D
pts [
"-116000,68000"
"-114000,70000"
"-116000,72000"
]
uid 12294,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "-116000,68000,-114000,72000"
)
oxt "9000,6000,11000,10000"
)
]
shape (GroupingShape
uid 12290,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "-118000,68000,-114000,72000"
)
oxt "7000,6000,11000,10000"
)
]
shape (Rectangle
uid 12296,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
lineWidth -1
)
xt "-119000,68000,-113000,72000"
fos 1
)
showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 12297,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*404 (Text
uid 12298,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-117500,68500,-112700,69500"
st "moduleware"
blo "-117500,69300"
)
*405 (Text
uid 12299,0
va (VaSet
font "arial,8,0"
)
xt "-117500,69500,-115900,70500"
st "and"
blo "-117500,70300"
)
*406 (Text
uid 12300,0
va (VaSet
font "arial,8,0"
)
xt "-117500,70500,-115100,71500"
st "and_4"
blo "-117500,71300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 12301,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 12302,0
text (MLText
uid 12303,0
va (VaSet
font "arial,8,0"
)
xt "-134000,59000,-134000,59000"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
de 2
visOptions (mwParamsVisibilityOptions
)
)
*407 (SaComponent
uid 12625,0
optionalChildren [
*408 (CptPort
uid 12605,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12606,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-72750,73625,-72000,74375"
)
tg (CPTG
uid 12607,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12608,0
va (VaSet
)
xt "-71000,73500,-66800,74500"
st "trigger_in"
blo "-71000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger_in"
t "std_logic"
o 2
)
)
)
*409 (CptPort
uid 12609,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12610,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-56000,71625,-55250,72375"
)
tg (CPTG
uid 12611,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 12612,0
va (VaSet
)
xt "-61600,71500,-57000,72500"
st "trigger_out"
ju 2
blo "-57000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_out"
t "std_logic"
o 3
i "'0'"
)
)
)
*410 (CptPort
uid 12613,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12614,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-72750,75625,-72000,76375"
)
tg (CPTG
uid 12615,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12616,0
va (VaSet
)
xt "-71000,75500,-67500,76500"
st "drs_write"
blo "-71000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_write"
t "std_logic"
o 4
i "'1'"
)
)
)
*411 (CptPort
uid 12617,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12618,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-56000,73625,-55250,74375"
)
tg (CPTG
uid 12619,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 12620,0
va (VaSet
)
xt "-64000,73500,-57000,74500"
st "drs_readout_ready"
ju 2
blo "-57000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_readout_ready"
t "std_logic"
o 5
)
)
)
*412 (CptPort
uid 12621,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12622,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-56000,74625,-55250,75375"
)
tg (CPTG
uid 12623,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 12624,0
va (VaSet
)
xt "-65900,74500,-57000,75500"
st "drs_readout_ready_ack"
ju 2
blo "-57000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
o 6
i "'0'"
)
)
)
*413 (CptPort
uid 12673,0
ps "OnEdgeStrategy"
shape (Triangle
uid 12674,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-72750,71625,-72000,72375"
)
tg (CPTG
uid 12675,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 12676,0
va (VaSet
)
xt "-71000,71500,-69700,72500"
st "clk"
blo "-71000,72300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 1
)
)
)
]
shape (Rectangle
uid 12626,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-72000,71000,-56000,78000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 12627,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*414 (Text
uid 12628,0
va (VaSet
font "Arial,8,1"
)
xt "-71950,78000,-65750,79000"
st "FACT_FAD_lib"
blo "-71950,78800"
tm "BdLibraryNameMgr"
)
*415 (Text
uid 12629,0
va (VaSet
font "Arial,8,1"
)
xt "-71950,79000,-65050,80000"
st "trigger_manager"
blo "-71950,79800"
tm "CptNameMgr"
)
*416 (Text
uid 12630,0
va (VaSet
font "Arial,8,1"
)
xt "-71950,80000,-61150,81000"
st "trigger_manager_instance"
blo "-71950,80800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 12631,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 12632,0
text (MLText
uid 12633,0
va (VaSet
font "Courier New,8,0"
)
xt "-62500,71000,-62500,71000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 12634,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-71750,76250,-70250,77750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*417 (Net
uid 12647,0
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "-- --
--      drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 88
suid 266,0
i "'0'"
)
declText (MLText
uid 12648,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,85200,-125500,87600"
st "-- --
--      drs_dwrite : out std_logic := '1';
SIGNAL drs_readout_ready            : std_logic                                    := '0'"
)
)
*418 (Net
uid 12653,0
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
o 89
suid 267,0
)
declText (MLText
uid 12654,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,87600,-146500,88400"
st "SIGNAL drs_readout_ready_ack        : std_logic"
)
)
*419 (SaComponent
uid 13117,0
optionalChildren [
*420 (CptPort
uid 13101,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13102,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "72000,61625,72750,62375"
)
tg (CPTG
uid 13103,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13104,0
va (VaSet
)
xt "69200,61500,71000,62500"
st "CLK"
ju 2
blo "71000,62300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
)
)
)
*421 (CptPort
uid 13105,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13106,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "72000,62625,72750,63375"
)
tg (CPTG
uid 13107,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13108,0
va (VaSet
)
xt "68300,62500,71000,63500"
st "enable"
ju 2
blo "71000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "enable"
t "std_logic"
o 2
)
)
)
*422 (CptPort
uid 13109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13110,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "72000,63625,72750,64375"
)
tg (CPTG
uid 13111,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13112,0
va (VaSet
)
xt "63900,63500,71000,64500"
st "multiplier : (15:0)"
ju 2
blo "71000,64300"
)
)
thePort (LogicalPort
decl (Decl
n "multiplier"
t "std_logic_vector"
b "(15 downto 0)"
o 3
)
)
)
*423 (CptPort
uid 13113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13114,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59250,61625,60000,62375"
)
tg (CPTG
uid 13115,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13116,0
va (VaSet
)
xt "61000,61500,64000,62500"
st "trigger"
blo "61000,62300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger"
t "std_logic"
o 4
)
)
)
]
shape (Rectangle
uid 13118,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "60000,61000,72000,65000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 13119,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*424 (Text
uid 13120,0
va (VaSet
font "Arial,8,1"
)
xt "62350,65000,68550,66000"
st "FACT_FAD_lib"
blo "62350,65800"
tm "BdLibraryNameMgr"
)
*425 (Text
uid 13121,0
va (VaSet
font "Arial,8,1"
)
xt "62350,66000,69650,67000"
st "continous_pulser"
blo "62350,66800"
tm "CptNameMgr"
)
*426 (Text
uid 13122,0
va (VaSet
font "Arial,8,1"
)
xt "62350,67000,73550,68000"
st "continous_pulser_instance"
blo "62350,67800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 13123,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 13124,0
text (MLText
uid 13125,0
va (VaSet
font "Courier New,8,0"
)
xt "58000,59400,85000,61000"
st "MINIMAL_TRIGGER_WAIT_TIME = 25000    ( integer )  
TRIGGER_WIDTH             = 5        ( integer )  "
)
header ""
)
elements [
(GiElement
name "MINIMAL_TRIGGER_WAIT_TIME"
type "integer"
value "25000"
)
(GiElement
name "TRIGGER_WIDTH"
type "integer"
value "5"
)
]
)
viewicon (ZoomableIcon
uid 13126,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "60250,63250,61750,64750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*427 (Net
uid 13157,0
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 65
suid 275,0
i "'0'"
)
declText (MLText
uid 13158,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,63600,-125500,64400"
st "SIGNAL c_trigger_enable             : std_logic                                    := '0'"
)
)
*428 (PortIoIn
uid 13689,0
shape (CompositeShape
uid 13690,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 13691,0
sl 0
ro 270
xt "78000,94625,79500,95375"
)
(Line
uid 13692,0
sl 0
ro 270
xt "79500,95000,80000,95000"
pts [
"79500,95000"
"80000,95000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 13693,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13694,0
va (VaSet
)
xt "80100,93500,83000,94500"
st "D_T_in"
ju 2
blo "83000,94300"
tm "WireNameMgr"
)
)
)
*429 (Net
uid 13701,0
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 281,0
)
declText (MLText
uid 13702,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,4000,-140500,4800"
st "D_T_in                       : std_logic_vector(1 DOWNTO 0)"
)
)
*430 (PortIoIn
uid 14042,0
shape (CompositeShape
uid 14043,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14044,0
sl 0
ro 270
xt "-74000,134625,-72500,135375"
)
(Line
uid 14045,0
sl 0
ro 270
xt "-72500,135000,-72000,135000"
pts [
"-72500,135000"
"-72000,135000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 14046,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14047,0
va (VaSet
)
xt "-80100,134500,-75000,135500"
st "drs_refclk_in"
ju 2
blo "-75000,135300"
tm "WireNameMgr"
)
)
)
*431 (Net
uid 14054,0
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 284,0
)
declText (MLText
uid 14055,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,12000,-118500,12800"
st "drs_refclk_in                : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
)
)
*432 (PortIoIn
uid 14165,0
shape (CompositeShape
uid 14166,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14167,0
sl 0
ro 270
xt "-92000,122625,-90500,123375"
)
(Line
uid 14168,0
sl 0
ro 270
xt "-90500,123000,-90000,123000"
pts [
"-90500,123000"
"-90000,123000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 14169,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14170,0
va (VaSet
)
xt "-96900,122500,-93000,123500"
st "plllock_in"
ju 2
blo "-93000,123300"
tm "WireNameMgr"
)
)
)
*433 (Net
uid 14177,0
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 285,0
)
declText (MLText
uid 14178,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,12800,-111000,13600"
st "plllock_in                   : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
)
)
*434 (SaComponent
uid 14417,0
optionalChildren [
*435 (CptPort
uid 14397,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14398,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-69750,133625,-69000,134375"
)
tg (CPTG
uid 14399,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14400,0
va (VaSet
)
xt "-68000,133500,-66700,134500"
st "clk"
blo "-68000,134300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 1
)
)
)
*436 (CptPort
uid 14401,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14402,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-69750,134625,-69000,135375"
)
tg (CPTG
uid 14403,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14404,0
va (VaSet
)
xt "-68000,134500,-64800,135500"
st "refclk_in"
blo "-68000,135300"
)
)
thePort (LogicalPort
decl (Decl
n "refclk_in"
t "std_logic"
o 2
)
)
)
*437 (CptPort
uid 14405,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14406,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-54000,133625,-53250,134375"
)
tg (CPTG
uid 14407,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14408,0
va (VaSet
)
xt "-63600,133500,-55000,134500"
st "counter_result : (11:0)"
ju 2
blo "-55000,134300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 downto 0)"
o 3
i "(others => '0')"
)
)
)
*438 (CptPort
uid 14409,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14410,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-54000,134625,-53250,135375"
)
tg (CPTG
uid 14411,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14412,0
va (VaSet
)
xt "-63600,134500,-55000,135500"
st "alarm_refclk_too_high"
ju 2
blo "-55000,135300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 4
i "'0'"
)
)
)
*439 (CptPort
uid 14413,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14414,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-54000,135625,-53250,136375"
)
tg (CPTG
uid 14415,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14416,0
va (VaSet
)
xt "-63200,135500,-55000,136500"
st "alarm_refclk_too_low"
ju 2
blo "-55000,136300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
o 5
i "'0'"
)
)
)
]
shape (Rectangle
uid 14418,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-69000,133000,-54000,138000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 14419,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*440 (Text
uid 14420,0
va (VaSet
font "Arial,8,1"
)
xt "-68200,138000,-62000,139000"
st "FACT_FAD_lib"
blo "-68200,138800"
tm "BdLibraryNameMgr"
)
*441 (Text
uid 14421,0
va (VaSet
font "Arial,8,1"
)
xt "-68200,139000,-60800,140000"
st "REFCLK_counter"
blo "-68200,139800"
tm "CptNameMgr"
)
*442 (Text
uid 14422,0
va (VaSet
font "Arial,8,1"
)
xt "-68200,140000,-58600,141000"
st "REFCLK_counter_main"
blo "-68200,140800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 14423,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 14424,0
text (MLText
uid 14425,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "-69000,131400,-47000,133000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 14426,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-68750,136250,-67250,137750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*443 (Net
uid 14477,0
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 290,0
)
declText (MLText
uid 14478,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,24800,-150000,25600"
st "alarm_refclk_too_high        : std_logic"
)
)
*444 (PortIoOut
uid 14485,0
shape (CompositeShape
uid 14486,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14487,0
sl 0
ro 270
xt "-50500,134625,-49000,135375"
)
(Line
uid 14488,0
sl 0
ro 270
xt "-51000,135000,-50500,135000"
pts [
"-51000,135000"
"-50500,135000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 14489,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14490,0
va (VaSet
)
xt "-48000,134500,-39400,135500"
st "alarm_refclk_too_high"
blo "-48000,135300"
tm "WireNameMgr"
)
)
)
*445 (Net
uid 14491,0
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 291,0
)
declText (MLText
uid 14492,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,25600,-150000,26400"
st "alarm_refclk_too_low         : std_logic"
)
)
*446 (PortIoOut
uid 14499,0
shape (CompositeShape
uid 14500,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14501,0
sl 0
ro 270
xt "-50500,135625,-49000,136375"
)
(Line
uid 14502,0
sl 0
ro 270
xt "-51000,136000,-50500,136000"
pts [
"-51000,136000"
"-50500,136000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 14503,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14504,0
va (VaSet
)
xt "-48000,135500,-39800,136500"
st "alarm_refclk_too_low"
blo "-48000,136300"
tm "WireNameMgr"
)
)
)
*447 (Net
uid 14620,0
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 292,0
)
declText (MLText
uid 14621,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,27200,-140000,28000"
st "counter_result               : std_logic_vector(11 DOWNTO 0)"
)
)
*448 (PortIoOut
uid 14628,0
shape (CompositeShape
uid 14629,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14630,0
sl 0
ro 270
xt "-41500,133625,-40000,134375"
)
(Line
uid 14631,0
sl 0
ro 270
xt "-42000,134000,-41500,134000"
pts [
"-42000,134000"
"-41500,134000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 14632,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14633,0
va (VaSet
)
xt "-39000,133500,-33400,134500"
st "counter_result"
blo "-39000,134300"
tm "WireNameMgr"
)
)
)
*449 (MWC
uid 14991,0
optionalChildren [
*450 (CptPort
uid 14963,0
optionalChildren [
*451 (Line
uid 14967,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "165000,78000,166000,78000"
pts [
"166000,78000"
"165000,78000"
]
)
*452 (Property
uid 14968,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 14964,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "166000,77625,166750,78375"
)
tg (CPTG
uid 14965,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14966,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "167419,77342,169219,78342"
st "dout"
ju 2
blo "169219,78142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 74
suid 1,0
i "'0'"
)
)
)
*453 (CptPort
uid 14969,0
optionalChildren [
*454 (Line
uid 14973,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "160000,77000,161000,77000"
pts [
"160000,77000"
"161000,77000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 14970,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "159250,76625,160000,77375"
)
tg (CPTG
uid 14971,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14972,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "156885,76294,158685,77294"
st "din0"
blo "156885,77094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 73
suid 2,0
i "'0'"
)
)
)
*455 (CptPort
uid 14974,0
optionalChildren [
*456 (Line
uid 14978,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "160000,79000,161000,79000"
pts [
"160000,79000"
"161000,79000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 14975,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "159250,78625,160000,79375"
)
tg (CPTG
uid 14976,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14977,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "157000,78700,158800,79700"
st "din1"
blo "157000,79500"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 77
suid 3,0
i "'0'"
)
)
)
*457 (CommentGraphic
uid 14979,0
optionalChildren [
*458 (Property
uid 14981,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"161000,80000"
"161000,80000"
]
uid 14980,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "161000,80000,161000,80000"
)
oxt "7000,10000,7000,10000"
)
*459 (CommentGraphic
uid 14982,0
optionalChildren [
*460 (Property
uid 14984,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"161000,76000"
"161000,76000"
]
uid 14983,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "161000,76000,161000,76000"
)
oxt "7000,6000,7000,6000"
)
*461 (Grouping
uid 14985,0
optionalChildren [
*462 (CommentGraphic
uid 14987,0
shape (PolyLine2D
pts [
"163000,80000"
"161000,80000"
"161000,76000"
"163000,76000"
]
uid 14988,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "161000,76000,163000,80000"
)
oxt "7000,6000,9000,10000"
)
*463 (CommentGraphic
uid 14989,0
shape (Arc2D
pts [
"163000,76000"
"165000,78000"
"163000,80000"
]
uid 14990,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "163000,76000,165000,80000"
)
oxt "9000,6000,11000,10000"
)
]
shape (GroupingShape
uid 14986,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "161000,76000,165000,80000"
)
oxt "7000,6000,11000,10000"
)
]
shape (Rectangle
uid 14992,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
lineWidth -1
)
xt "160000,76000,166000,80000"
fos 1
)
showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 14993,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*464 (Text
uid 14994,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "162500,75500,167300,76500"
st "moduleware"
blo "162500,76300"
)
*465 (Text
uid 14995,0
va (VaSet
font "arial,8,0"
)
xt "162500,76500,164100,77500"
st "and"
blo "162500,77300"
)
*466 (Text
uid 14996,0
va (VaSet
font "arial,8,0"
)
xt "162500,77500,164900,78500"
st "and_2"
blo "162500,78300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 14997,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 14998,0
text (MLText
uid 14999,0
va (VaSet
font "arial,8,0"
)
xt "145000,67000,145000,67000"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
de 2
visOptions (mwParamsVisibilityOptions
)
)
*467 (MWC
uid 15058,0
optionalChildren [
*468 (CptPort
uid 15045,0
optionalChildren [
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uid 15049,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "153000,79000,154000,79000"
pts [
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"154000,79000"
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)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 15046,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "152250,78625,153000,79375"
)
tg (CPTG
uid 15047,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 15048,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "150000,78500,151400,79500"
st "din"
blo "150000,79300"
)
s (Text
uid 15067,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "150000,79500,150000,79500"
blo "150000,79500"
)
)
thePort (LogicalPort
decl (Decl
n "din"
t "std_logic"
posAdd 0
o 28
suid 1,0
)
)
)
*470 (CptPort
uid 15050,0
optionalChildren [
*471 (Line
uid 15054,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "157750,79000,158000,79000"
pts [
"158000,79000"
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)
*472 (Circle
uid 15055,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
)
xt "157000,78625,157750,79375"
radius 375
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 15051,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "158000,78625,158750,79375"
)
tg (CPTG
uid 15052,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 15053,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "159950,78500,161750,79500"
st "dout"
ju 2
blo "161750,79300"
)
s (Text
uid 15068,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "161750,79500,161750,79500"
ju 2
blo "161750,79500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 77
suid 2,0
i "'0'"
)
)
)
*473 (CommentGraphic
uid 15056,0
shape (CustomPolygon
pts [
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"154000,77000"
]
uid 15057,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
bg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "154000,77000,157000,81000"
)
oxt "7000,6000,10000,10000"
)
]
shape (Rectangle
uid 15059,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "153000,77000,158000,81000"
fos 1
)
showPorts 0
oxt "6000,6000,11000,10000"
ttg (MlTextGroup
uid 15060,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 15061,0
va (VaSet
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font "arial,8,0"
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xt "155350,77100,160150,78100"
st "moduleware"
blo "155350,77900"
)
*475 (Text
uid 15062,0
va (VaSet
font "arial,8,0"
)
xt "155350,78100,156650,79100"
st "inv"
blo "155350,78900"
)
*476 (Text
uid 15063,0
va (VaSet
font "arial,8,0"
)
xt "155350,79100,159450,80100"
st "inverter_1"
blo "155350,79900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 15064,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 15065,0
text (MLText
uid 15066,0
va (VaSet
font "arial,8,0"
)
xt "150000,58400,150000,58400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*477 (Net
uid 15077,0
decl (Decl
n "denable_prim"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 73
suid 294,0
i "'0'"
)
declText (MLText
uid 15078,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,70000,-112000,70800"
st "SIGNAL denable_prim                 : std_logic                                    := '0' -- default domino wave off"
)
)
*478 (Net
uid 15079,0
decl (Decl
n "din1"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 77
suid 295,0
i "'0'"
)
declText (MLText
uid 15080,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,73200,-112000,74000"
st "SIGNAL din1                         : std_logic                                    := '0' -- default domino wave off"
)
)
*479 (Net
uid 15492,0
decl (Decl
n "trigger_out"
t "std_logic"
o 136
suid 301,0
)
declText (MLText
uid 15493,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,128400,-146500,129200"
st "SIGNAL trigger_out                  : std_logic"
)
)
*480 (Net
uid 15748,0
lang 2
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(31 downto 0)"
preAdd 0
posAdd 0
o 134
suid 302,0
)
declText (MLText
uid 15749,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,126800,-136500,127600"
st "SIGNAL trigger_id                   : std_logic_vector(31 downto 0)"
)
)
*481 (Net
uid 16369,0
decl (Decl
n "DCM_PS_status"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 55
suid 304,0
i "(OTHERS => '0')"
)
declText (MLText
uid 16370,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,49200,-119500,50000"
st "SIGNAL DCM_PS_status                : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
)
)
*482 (SaComponent
uid 16404,0
optionalChildren [
*483 (CptPort
uid 16388,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16389,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-67750,97625,-67000,98375"
)
tg (CPTG
uid 16390,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16391,0
va (VaSet
)
xt "-66000,97500,-64500,98500"
st "clk"
blo "-66000,98300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*484 (CptPort
uid 16396,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16397,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-57000,97625,-56250,98375"
)
tg (CPTG
uid 16398,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16399,0
va (VaSet
)
xt "-63100,97500,-58000,98500"
st "dna : (63:0)"
ju 2
blo "-58000,98300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dna"
t "STD_LOGIC_VECTOR"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 2
suid 3,0
i "(others => '0')"
)
)
)
*485 (CptPort
uid 16400,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16401,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-57000,99625,-56250,100375"
)
tg (CPTG
uid 16402,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16403,0
va (VaSet
)
xt "-60500,99500,-58000,100500"
st "ready"
ju 2
blo "-58000,100300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ready"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 3
suid 4,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 16405,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-67000,96000,-57000,106000"
)
oxt "39000,2000,49000,12000"
ttg (MlTextGroup
uid 16406,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*486 (Text
uid 16407,0
va (VaSet
font "Arial,8,1"
)
xt "-64800,103000,-58600,104000"
st "FACT_FAD_lib"
blo "-64800,103800"
tm "BdLibraryNameMgr"
)
*487 (Text
uid 16408,0
va (VaSet
font "Arial,8,1"
)
xt "-64800,104000,-61200,105000"
st "dna_gen"
blo "-64800,104800"
tm "CptNameMgr"
)
*488 (Text
uid 16409,0
va (VaSet
font "Arial,8,1"
)
xt "-64800,105000,-57300,106000"
st "dna_gen_instance"
blo "-64800,105800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16410,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16411,0
text (MLText
uid 16412,0
va (VaSet
font "Courier New,8,0"
)
xt "-67000,95000,-67000,95000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 16413,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-66750,104250,-65250,105750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*489 (Net
uid 16545,0
decl (Decl
n "dna"
t "STD_LOGIC_VECTOR"
b "(63 DOWNTO 0)"
preAdd 0
posAdd 0
o 78
suid 309,0
i "(others => '0')"
)
declText (MLText
uid 16546,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,74000,-119500,74800"
st "SIGNAL dna                          : STD_LOGIC_VECTOR(63 DOWNTO 0)                := (others => '0')"
)
)
*490 (Net
uid 16562,0
decl (Decl
n "ready"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 110
suid 311,0
i "'0'"
)
declText (MLText
uid 16563,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,105200,-125500,106000"
st "SIGNAL ready                        : STD_LOGIC                                    := '0'"
)
)
*491 (SaComponent
uid 16865,0
optionalChildren [
*492 (CptPort
uid 16841,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16842,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-69750,144625,-69000,145375"
)
tg (CPTG
uid 16843,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16844,0
va (VaSet
)
xt "-68000,144500,-66700,145500"
st "clk"
blo "-68000,145300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 1
)
)
)
*493 (CptPort
uid 16845,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16846,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-49000,144625,-48250,145375"
)
tg (CPTG
uid 16847,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16848,0
va (VaSet
)
xt "-61400,144500,-50000,145500"
st "time_o : (TIMER_WIDTH-1:0)"
ju 2
blo "-50000,145300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "time_o"
t "std_logic_vector"
b "( TIMER_WIDTH-1 downto 0)"
o 2
)
)
)
*494 (CptPort
uid 16849,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16850,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-69750,145625,-69000,146375"
)
tg (CPTG
uid 16851,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16852,0
va (VaSet
)
xt "-68000,145500,-65100,146500"
st "synch_i"
blo "-68000,146300"
)
)
thePort (LogicalPort
decl (Decl
n "synch_i"
t "std_logic"
o 3
)
)
)
*495 (CptPort
uid 16853,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16854,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-49000,145625,-48250,146375"
)
tg (CPTG
uid 16855,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 16856,0
va (VaSet
)
xt "-53900,145500,-50000,146500"
st "synched_o"
ju 2
blo "-50000,146300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "synched_o"
t "std_logic"
o 4
i "'0'"
)
)
)
*496 (CptPort
uid 16857,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16858,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-69750,147625,-69000,148375"
)
tg (CPTG
uid 16859,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16860,0
va (VaSet
)
xt "-68000,147500,-62600,148500"
st "reset_synch_i"
blo "-68000,148300"
)
)
thePort (LogicalPort
decl (Decl
n "reset_synch_i"
t "std_logic"
o 5
)
)
)
*497 (CptPort
uid 16861,0
ps "OnEdgeStrategy"
shape (Triangle
uid 16862,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-69750,146625,-69000,147375"
)
tg (CPTG
uid 16863,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16864,0
va (VaSet
)
xt "-68000,146500,-64800,147500"
st "enable_i"
blo "-68000,147300"
)
)
thePort (LogicalPort
decl (Decl
n "enable_i"
t "std_logic"
o 6
)
)
)
]
shape (Rectangle
uid 16866,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-69000,144000,-49000,149000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 16867,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*498 (Text
uid 16868,0
va (VaSet
font "Arial,8,1"
)
xt "-68100,149000,-61900,150000"
st "FACT_FAD_lib"
blo "-68100,149800"
tm "BdLibraryNameMgr"
)
*499 (Text
uid 16869,0
va (VaSet
font "Arial,8,1"
)
xt "-68100,150000,-65800,151000"
st "timer"
blo "-68100,150800"
tm "CptNameMgr"
)
*500 (Text
uid 16870,0
va (VaSet
font "Arial,8,1"
)
xt "-68100,151000,-61900,152000"
st "timer_instance"
blo "-68100,151800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16871,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16872,0
text (MLText
uid 16873,0
va (VaSet
font "Courier New,8,0"
)
xt "-68500,142400,-49500,144000"
st "TIMER_WIDTH = 32      ( integer )  
PRESCALER   = 5000    ( integer )  "
)
header ""
)
elements [
(GiElement
name "TIMER_WIDTH"
type "integer"
value "32"
)
(GiElement
name "PRESCALER"
type "integer"
value "5000"
)
]
)
viewicon (ZoomableIcon
uid 16874,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-68750,147250,-67250,148750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*501 (MWC
uid 16902,0
optionalChildren [
*502 (CptPort
uid 16891,0
optionalChildren [
*503 (Line
uid 16895,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-84000,147000,-84000,147000"
pts [
"-84000,147000"
"-84000,147000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 16892,0
ro 180
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-84375,147000,-83625,147750"
)
tg (CPTG
uid 16893,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 16894,0
sl 0
ro 270
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-84422,148110,-83422,149910"
st "dout"
blo "-83622,149910"
)
s (Text
uid 16911,0
sl 0
ro 270
va (VaSet
font "arial,8,0"
)
xt "-83422,149910,-83422,149910"
blo "-83422,149910"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 96
suid 1,0
)
)
)
*504 (Grouping
uid 16896,0
optionalChildren [
*505 (CommentGraphic
uid 16898,0
shape (PolyLine2D
pts [
"-84000,147000"
"-84000,145000"
]
uid 16899,0
layer 0
sl 0
ro 90
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-84000,145000,-84000,147000"
)
oxt "7000,6000,7000,8000"
)
*506 (CommentGraphic
uid 16900,0
shape (PolyLine2D
pts [
"-85000,145000"
"-83000,145000"
]
uid 16901,0
layer 0
sl 0
ro 90
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "-85000,145000,-83000,145000"
)
oxt "6000,6000,8000,6000"
)
]
shape (GroupingShape
uid 16897,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "-85000,145000,-83000,147000"
)
oxt "6000,6000,8000,8000"
)
]
shape (Rectangle
uid 16903,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "-85000,145000,-83000,147000"
fos 1
)
showPorts 0
oxt "6000,6000,8000,8000"
ttg (MlTextGroup
uid 16904,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*507 (Text
uid 16905,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-84650,142100,-79850,143100"
st "moduleware"
blo "-84650,142900"
)
*508 (Text
uid 16906,0
va (VaSet
font "arial,8,0"
)
xt "-84650,143100,-83150,144100"
st "vdd"
blo "-84650,143900"
)
*509 (Text
uid 16907,0
va (VaSet
font "arial,8,0"
)
xt "-84650,144100,-82450,145100"
st "U_14"
blo "-84650,144900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 16908,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 16909,0
text (MLText
uid 16910,0
va (VaSet
font "arial,8,0"
)
xt "-93000,125400,-93000,125400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*510 (Net
uid 16912,0
decl (Decl
n "enable_i"
t "std_logic"
o 96
suid 314,0
)
declText (MLText
uid 16913,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,93200,-146500,94000"
st "SIGNAL enable_i                     : std_logic"
)
)
*511 (MWC
uid 16927,0
optionalChildren [
*512 (CptPort
uid 16918,0
optionalChildren [
*513 (Line
uid 16922,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-80999,148000,-79000,148000"
pts [
"-79000,148000"
"-80999,148000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 16919,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-79000,147625,-78250,148375"
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prms (Property
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decl (Decl
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-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
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prms (Property
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declText (MLText
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decl (Decl
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posAdd 0
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decl (Decl
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declText (MLText
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va (VaSet
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*549 (Net
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decl (Decl
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t "dac_array_type"
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suid 342,0
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declText (MLText
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va (VaSet
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declText (MLText
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decl (Decl
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va (VaSet
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xt "-172000,56400,-146500,57200"
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decl (Decl
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i "'1'"
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va (VaSet
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decl (Decl
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t "std_logic"
o 94
suid 376,0
i "'1'"
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declText (MLText
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va (VaSet
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xt "-172000,91600,-125500,92400"
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)
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xt "-52000,123000,-51000,123000"
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pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
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ps "OnEdgeStrategy"
shape (Triangle
uid 22089,0
ro 90
va (VaSet
vasetType 1
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fg "0,65535,65535"
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xt "-51000,122625,-50250,123375"
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tg (CPTG
uid 22090,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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sl 0
va (VaSet
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font "arial,8,0"
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xt "-49581,122342,-47781,123342"
st "dout"
ju 2
blo "-47781,123142"
)
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thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 94
suid 1,0
i "'1'"
)
)
)
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uid 22094,0
optionalChildren [
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layer 5
sl 0
va (VaSet
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xt "-57000,122000,-55999,122000"
pts [
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ps "OnEdgeStrategy"
shape (Triangle
uid 22095,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
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xt "-57750,121625,-57000,122375"
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tg (CPTG
uid 22096,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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sl 0
va (VaSet
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font "arial,8,0"
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xt "-60115,121294,-58315,122294"
st "din0"
blo "-60115,122094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 93
suid 2,0
i "'1'"
)
)
)
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uid 22099,0
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layer 5
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va (VaSet
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pts [
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]
ps "OnEdgeStrategy"
shape (Triangle
uid 22100,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
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xt "-57750,123625,-57000,124375"
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tg (CPTG
uid 22101,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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sl 0
va (VaSet
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font "arial,8,0"
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xt "-60000,123700,-58200,124700"
st "din1"
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thePort (LogicalPort
decl (Decl
n "din1"
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o 84
suid 3,0
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pclass "_MW_GEOM_"
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uid 22105,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
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oxt "7000,10000,7000,10000"
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*637 (CommentGraphic
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uid 22109,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
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shape (PolyLine2D
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uid 22108,0
layer 0
sl 0
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xt "-56000,121000,-56000,121000"
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oxt "7000,6000,7000,6000"
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shape (PolyLine2D
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uid 22113,0
layer 0
sl 0
va (VaSet
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fg "0,65535,65535"
lineColor "26368,26368,26368"
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xt "-56000,121000,-54000,125000"
)
oxt "7000,6000,9000,10000"
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shape (Arc2D
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uid 22115,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
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xt "-54000,121000,-52000,125000"
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oxt "9000,6000,11000,10000"
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shape (GroupingShape
uid 22111,0
sl 0
va (VaSet
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lineWidth 2
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xt "-56000,121000,-52000,125000"
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oxt "7000,6000,11000,10000"
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shape (Rectangle
uid 22117,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
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xt "-57000,121000,-51000,125000"
fos 1
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showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 22118,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 22119,0
va (VaSet
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xt "-55500,123500,-50700,124500"
st "moduleware"
blo "-55500,124300"
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va (VaSet
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xt "-55500,124500,-53900,125500"
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va (VaSet
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xt "-55500,125500,-53700,126500"
st "U_4"
blo "-55500,126300"
tm "InstanceNameMgr"
)
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ga (GenericAssociation
uid 22122,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 22123,0
text (MLText
uid 22124,0
va (VaSet
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)
xt "-72000,112000,-72000,112000"
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header ""
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elements [
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sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
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prms (Property
pclass "params"
pname "params"
ptn "String"
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de 2
visOptions (mwParamsVisibilityOptions
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*645 (Net
uid 22125,0
decl (Decl
n "dout4"
t "STD_LOGIC"
o 84
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declText (MLText
uid 22126,0
va (VaSet
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xt "-172000,78800,-146500,79600"
st "SIGNAL dout4                        : STD_LOGIC"
)
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*646 (Net
uid 22131,0
decl (Decl
n "dwrite_trigger_manager"
t "std_logic"
o 95
suid 378,0
i "'1'"
)
declText (MLText
uid 22132,0
va (VaSet
font "Courier New,8,0"
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xt "-172000,92400,-125500,93200"
st "SIGNAL dwrite_trigger_manager       : std_logic                                    := '1'"
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)
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uid 23004,0
optionalChildren [
*648 (CptPort
uid 22993,0
optionalChildren [
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layer 5
sl 0
va (VaSet
vasetType 3
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xt "-94000,128000,-94000,128000"
pts [
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)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 22994,0
ro 180
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
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xt "-94375,128000,-93625,128750"
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tg (CPTG
uid 22995,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 22996,0
sl 0
ro 270
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-94422,129110,-93422,130910"
st "dout"
blo "-93622,130910"
)
s (Text
uid 23013,0
sl 0
ro 270
va (VaSet
font "arial,8,0"
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xt "-93422,130910,-93422,130910"
blo "-93422,130910"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "STD_LOGIC"
o 59
suid 1,0
)
)
)
*650 (Grouping
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shape (PolyLine2D
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uid 23001,0
layer 0
sl 0
ro 90
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
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xt "-94000,126000,-94000,128000"
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oxt "7000,6000,7000,8000"
)
*652 (CommentGraphic
uid 23002,0
shape (PolyLine2D
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uid 23003,0
layer 0
sl 0
ro 90
va (VaSet
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lineColor "26368,26368,26368"
lineWidth 2
)
xt "-95000,126000,-93000,126000"
)
oxt "6000,6000,8000,6000"
)
]
shape (GroupingShape
uid 22999,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
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xt "-95000,126000,-93000,128000"
)
oxt "6000,6000,8000,8000"
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shape (Rectangle
uid 23005,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
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xt "-95000,126000,-93000,128000"
fos 1
)
showPorts 0
oxt "6000,6000,8000,8000"
ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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uid 23007,0
va (VaSet
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blo "-93650,125900"
)
*654 (Text
uid 23008,0
va (VaSet
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xt "-93650,126100,-92150,127100"
st "vdd"
blo "-93650,126900"
)
*655 (Text
uid 23009,0
va (VaSet
font "arial,8,0"
)
xt "-93650,127100,-91850,128100"
st "U_3"
blo "-93650,127900"
tm "InstanceNameMgr"
)
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)
ga (GenericAssociation
uid 23010,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 23011,0
text (MLText
uid 23012,0
va (VaSet
font "arial,8,0"
)
xt "-103000,106400,-103000,106400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
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visOptions (mwParamsVisibilityOptions
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)
*656 (MWC
uid 23034,0
optionalChildren [
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uid 23014,0
optionalChildren [
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uid 23018,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "169000,81000,169000,81000"
pts [
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"169000,81000"
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)
]
ps "OnEdgeStrategy"
shape (Triangle
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ro 180
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "168625,80250,169375,81000"
)
tg (CPTG
uid 23016,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 23017,0
sl 0
ro 270
va (VaSet
isHidden 1
font "arial,8,0"
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xt "260100,351600,261100,352400"
st "s"
ju 2
blo "260900,351600"
)
s (Text
uid 23043,0
sl 0
ro 270
va (VaSet
font "arial,8,0"
)
xt "261100,351600,261100,351600"
ju 2
blo "261100,351600"
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thePort (LogicalPort
decl (Decl
n "s"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 74
suid 1,0
i "'0'"
)
)
)
*659 (CptPort
uid 23019,0
optionalChildren [
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uid 23023,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "169000,83000,169000,83000"
pts [
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]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 23020,0
ro 180
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
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xt "168625,83000,169375,83750"
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tg (CPTG
uid 23021,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 23022,0
sl 0
ro 270
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "252800,352700,253800,353300"
st "t"
blo "253600,353300"
)
s (Text
uid 23044,0
sl 0
ro 270
va (VaSet
font "arial,8,0"
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xt "253800,353300,253800,353300"
blo "253800,353300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "t"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 2,0
i "'0'"
)
)
)
*661 (CommentGraphic
uid 23024,0
shape (PolyLine2D
pts [
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]
uid 23025,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "168000,81000,169000,82000"
)
oxt "6000,6000,7000,7000"
)
*662 (CommentGraphic
uid 23026,0
shape (PolyLine2D
pts [
"168000,82000"
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]
uid 23027,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "168000,82000,169000,83000"
)
oxt "6000,7000,7000,8000"
)
*663 (CommentGraphic
uid 23028,0
shape (PolyLine2D
pts [
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]
uid 23029,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "168988,82329,169988,82329"
)
oxt "6988,7329,7988,7329"
)
*664 (CommentGraphic
uid 23030,0
shape (PolyLine2D
pts [
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uid 23031,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "170000,82000,171000,82000"
)
oxt "8000,7000,9000,7000"
)
*665 (CommentGraphic
uid 23032,0
shape (PolyLine2D
pts [
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]
uid 23033,0
layer 8
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
lineColor "26368,26368,26368"
lineWidth 2
)
xt "168976,81730,169976,81730"
)
oxt "6976,6730,7976,6730"
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]
shape (Rectangle
uid 23035,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "168000,81000,171000,83000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,8000"
ttg (MlTextGroup
uid 23036,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 23037,0
va (VaSet
isHidden 1
font "arial,8,0"
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xt "173350,80100,178150,81100"
st "moduleware"
blo "173350,80900"
)
*667 (Text
uid 23038,0
va (VaSet
font "arial,8,0"
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xt "173350,81100,178050,82100"
st "assignment"
blo "173350,81900"
)
*668 (Text
uid 23039,0
va (VaSet
font "arial,8,0"
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xt "173350,82100,175150,83100"
st "U_5"
blo "173350,82900"
tm "InstanceNameMgr"
)
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)
ga (GenericAssociation
uid 23040,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 23041,0
text (MLText
uid 23042,0
va (VaSet
font "arial,8,0"
)
xt "163000,61400,163000,61400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*669 (Net
uid 23051,0
decl (Decl
n "denable_sig"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 74
suid 380,0
i "'0'"
)
declText (MLText
uid 23052,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,70800,-112000,71600"
st "SIGNAL denable_sig                  : std_logic                                    := '0' -- default domino wave off"
)
)
*670 (Net
uid 23341,0
decl (Decl
n "DCM_locked_status"
t "std_logic"
o 56
suid 382,0
)
declText (MLText
uid 23342,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,50000,-146500,50800"
st "SIGNAL DCM_locked_status            : std_logic"
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uid 23349,0
decl (Decl
n "DCM_ready_status"
t "std_logic"
o 57
suid 383,0
)
declText (MLText
uid 23350,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,50800,-146500,51600"
st "SIGNAL DCM_ready_status             : std_logic"
)
)
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uid 24076,0
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 385,0
i "'1'"
)
declText (MLText
uid 24077,0
va (VaSet
font "Courier New,8,0"
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xt "-172000,39200,-129000,40000"
st "trigger_veto                 : std_logic                                    := '1'"
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*673 (PortIoOut
uid 24084,0
shape (CompositeShape
uid 24085,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 24086,0
sl 0
ro 270
xt "65500,98625,67000,99375"
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(Line
uid 24087,0
sl 0
ro 270
xt "65000,99000,65500,99000"
pts [
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)
]
)
stc 0
sf 1
tg (WTG
uid 24088,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24089,0
va (VaSet
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xt "68000,98500,72900,99500"
st "trigger_veto"
blo "68000,99300"
tm "WireNameMgr"
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)
*674 (SaComponent
uid 24570,0
optionalChildren [
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uid 24538,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24539,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-21750,148625,-21000,149375"
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tg (CPTG
uid 24540,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 24541,0
va (VaSet
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xt "-20000,148500,-16800,149500"
st "rec_clk"
blo "-20000,149300"
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)
thePort (LogicalPort
decl (Decl
n "rec_clk"
t "std_logic"
o 1
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*676 (CptPort
uid 24542,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24543,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "-1000,157625,-250,158375"
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tg (CPTG
uid 24544,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24545,0
va (VaSet
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xt "-4300,157500,-2000,158500"
st "rx_d"
ju 2
blo "-2000,158300"
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)
thePort (LogicalPort
decl (Decl
n "rx_d"
t "std_logic"
o 2
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*677 (CptPort
uid 24546,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24547,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "-1000,158625,-250,159375"
)
tg (CPTG
uid 24548,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24549,0
va (VaSet
)
xt "-4600,158500,-2000,159500"
st "rx_en"
ju 2
blo "-2000,159300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rx_en"
t "std_logic"
o 3
)
)
)
*678 (CptPort
uid 24550,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24551,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1000,156625,-250,157375"
)
tg (CPTG
uid 24552,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24553,0
va (VaSet
)
xt "-4300,156500,-2000,157500"
st "tx_d"
ju 2
blo "-2000,157300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "tx_d"
t "std_logic"
o 4
)
)
)
*679 (CptPort
uid 24554,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24555,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1000,159625,-250,160375"
)
tg (CPTG
uid 24556,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24557,0
va (VaSet
)
xt "-4600,159500,-2000,160500"
st "tx_en"
ju 2
blo "-2000,160300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "tx_en"
t "std_logic"
o 5
)
)
)
*680 (CptPort
uid 24558,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24559,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1000,149625,-250,150375"
)
tg (CPTG
uid 24560,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24561,0
va (VaSet
)
xt "-6100,149500,-2000,150500"
st "rec_start"
ju 2
blo "-2000,150300"
)
)
thePort (LogicalPort
decl (Decl
n "rec_start"
t "std_logic"
o 6
)
)
)
*681 (CptPort
uid 24562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24563,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1000,150625,-250,151375"
)
tg (CPTG
uid 24564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24565,0
va (VaSet
)
xt "-14500,150500,-2000,151500"
st "rec_dout : (RX_WIDTH - 1:0)"
ju 2
blo "-2000,151300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rec_dout"
t "std_logic_vector"
b "(RX_WIDTH - 1 downto 0)"
o 8
i "(others => '0')"
)
)
)
*682 (CptPort
uid 24566,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24567,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1000,151625,-250,152375"
)
tg (CPTG
uid 24568,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24569,0
va (VaSet
)
xt "-5800,151500,-2000,152500"
st "rec_valid"
ju 2
blo "-2000,152300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rec_valid"
t "std_logic"
o 9
i "'0'"
)
)
)
*683 (CptPort
uid 24732,0
ps "OnEdgeStrategy"
shape (Triangle
uid 24733,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-1000,152625,-250,153375"
)
tg (CPTG
uid 24734,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 24735,0
va (VaSet
)
xt "-10800,152500,-2000,153500"
st "rec_timeout_occured"
ju 2
blo "-2000,153300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rec_timeout_occured"
t "std_logic"
o 7
i "'0'"
)
)
)
]
shape (Rectangle
uid 24571,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-21000,148000,-1000,162000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 24572,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*684 (Text
uid 24573,0
va (VaSet
font "Arial,8,1"
)
xt "-15000,157000,-8800,158000"
st "FACT_FAD_lib"
blo "-15000,157800"
tm "BdLibraryNameMgr"
)
*685 (Text
uid 24574,0
va (VaSet
font "Arial,8,1"
)
xt "-15000,158000,-7000,159000"
st "FAD_rs485_receiver"
blo "-15000,158800"
tm "CptNameMgr"
)
*686 (Text
uid 24575,0
va (VaSet
font "Arial,8,1"
)
xt "-15000,159000,-7200,160000"
st "Inst_rs485_receiver"
blo "-15000,159800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 24576,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 24577,0
text (MLText
uid 24578,0
va (VaSet
font "Courier New,8,0"
)
xt "-24000,146400,18500,148000"
st "RX_BYTES = RS485_MESSAGE_LEN_BYTES        ( integer ) -- no. of bytes to receive 
RX_WIDTH = RS485_MESSAGE_LEN_BYTES * 8    ( integer ) -- no. of bits to receive  "
)
header ""
)
elements [
(GiElement
name "RX_BYTES"
type "integer"
value "RS485_MESSAGE_LEN_BYTES"
e "-- no. of bytes to receive"
)
(GiElement
name "RX_WIDTH"
type "integer"
value "RS485_MESSAGE_LEN_BYTES * 8"
e "-- no. of bits to receive"
)
]
)
viewicon (ZoomableIcon
uid 24579,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-20750,160250,-19250,161750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*687 (PortIoOut
uid 24652,0
shape (CompositeShape
uid 24653,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 24654,0
sl 0
ro 270
xt "4500,156625,6000,157375"
)
(Line
uid 24655,0
sl 0
ro 270
xt "4000,157000,4500,157000"
pts [
"4000,157000"
"4500,157000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 24656,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24657,0
va (VaSet
)
xt "7000,156500,13900,157500"
st "FTM_RS485_tx_d"
blo "7000,157300"
tm "WireNameMgr"
)
)
)
*688 (PortIoIn
uid 24666,0
shape (CompositeShape
uid 24667,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 24668,0
sl 0
ro 90
xt "4500,157625,6000,158375"
)
(Line
uid 24669,0
sl 0
ro 90
xt "4000,158000,4500,158000"
pts [
"4500,158000"
"4000,158000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 24670,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24671,0
va (VaSet
)
xt "7000,157500,14000,158500"
st "FTM_RS485_rx_d"
blo "7000,158300"
tm "WireNameMgr"
)
)
)
*689 (PortIoOut
uid 24680,0
shape (CompositeShape
uid 24681,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 24682,0
sl 0
ro 270
xt "5500,158625,7000,159375"
)
(Line
uid 24683,0
sl 0
ro 270
xt "5000,159000,5500,159000"
pts [
"5000,159000"
"5500,159000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 24684,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24685,0
va (VaSet
)
xt "8000,158500,15400,159500"
st "FTM_RS485_rx_en"
blo "8000,159300"
tm "WireNameMgr"
)
)
)
*690 (PortIoOut
uid 24694,0
shape (CompositeShape
uid 24695,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 24696,0
sl 0
ro 270
xt "5500,159625,7000,160375"
)
(Line
uid 24697,0
sl 0
ro 270
xt "5000,160000,5500,160000"
pts [
"5000,160000"
"5500,160000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 24698,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24699,0
va (VaSet
)
xt "8000,159500,15300,160500"
st "FTM_RS485_tx_en"
blo "8000,160300"
tm "WireNameMgr"
)
)
)
*691 (Net
uid 24700,0
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 395,0
)
declText (MLText
uid 24701,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,4800,-150000,5600"
st "FTM_RS485_rx_d               : std_logic"
)
)
*692 (Net
uid 24702,0
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 396,0
)
declText (MLText
uid 24703,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,20000,-150000,20800"
st "FTM_RS485_tx_d               : std_logic"
)
)
*693 (Net
uid 24704,0
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 397,0
)
declText (MLText
uid 24705,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,19200,-150000,20000"
st "FTM_RS485_rx_en              : std_logic"
)
)
*694 (Net
uid 24706,0
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 398,0
)
declText (MLText
uid 24707,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,20800,-150000,21600"
st "FTM_RS485_tx_en              : std_logic"
)
)
*695 (Net
uid 24736,0
decl (Decl
n "rec_timeout_occured"
t "std_logic"
o 111
suid 399,0
i "'0'"
)
declText (MLText
uid 24737,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,106000,-125500,106800"
st "SIGNAL rec_timeout_occured          : std_logic                                    := '0'"
)
)
*696 (Net
uid 25027,0
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 113
suid 403,0
i "'0'"
)
declText (MLText
uid 25028,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,107600,-125500,108400"
st "SIGNAL reset_trigger_id             : std_logic                                    := '0'"
)
)
*697 (PortIoOut
uid 25304,0
shape (CompositeShape
uid 25305,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 25306,0
sl 0
ro 270
xt "132500,107625,134000,108375"
)
(Line
uid 25307,0
sl 0
ro 270
xt "132000,108000,132500,108000"
pts [
"132000,108000"
"132500,108000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 25308,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25309,0
va (VaSet
)
xt "134000,107500,138900,108500"
st "w5300_state"
blo "134000,108300"
tm "WireNameMgr"
)
)
)
*698 (Net
uid 25310,0
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 406,0
)
declText (MLText
uid 25311,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,40000,-115000,40800"
st "w5300_state                  : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
)
)
*699 (Net
uid 25541,0
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 407,0
)
declText (MLText
uid 25542,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,28800,-150000,29600"
st "debug_data_ram_empty         : std_logic"
)
)
*700 (PortIoOut
uid 25549,0
shape (CompositeShape
uid 25550,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 25551,0
sl 0
ro 270
xt "137500,108625,139000,109375"
)
(Line
uid 25552,0
sl 0
ro 270
xt "137000,109000,137500,109000"
pts [
"137000,109000"
"137500,109000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 25553,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25554,0
va (VaSet
)
xt "140000,108500,149100,109500"
st "debug_data_ram_empty"
blo "140000,109300"
tm "WireNameMgr"
)
)
)
*701 (Net
uid 25555,0
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 408,0
)
declText (MLText
uid 25556,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,29600,-150000,30400"
st "debug_data_valid             : std_logic"
)
)
*702 (PortIoOut
uid 25563,0
shape (CompositeShape
uid 25564,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 25565,0
sl 0
ro 270
xt "135500,109625,137000,110375"
)
(Line
uid 25566,0
sl 0
ro 270
xt "135000,110000,135500,110000"
pts [
"135000,110000"
"135500,110000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 25567,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25568,0
va (VaSet
)
xt "138000,109500,144600,110500"
st "debug_data_valid"
blo "138000,110300"
tm "WireNameMgr"
)
)
)
*703 (MWC
uid 25830,0
optionalChildren [
*704 (CptPort
uid 25821,0
optionalChildren [
*705 (Line
uid 25825,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "-41999,78000,-40000,78000"
pts [
"-40000,78000"
"-41999,78000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 25822,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "-40000,77625,-39250,78375"
)
tg (CPTG
uid 25823,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 25824,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-38836,77595,-37036,78595"
st "dout"
ju 2
blo "-37036,78395"
)
s (Text
uid 25839,0
sl 0
va (VaSet
font "arial,8,0"
)
xt "-37036,78595,-37036,78595"
ju 2
blo "-37036,78595"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 125
suid 1,0
)
)
)
*706 (CommentGraphic
uid 25826,0
shape (PolyLine2D
pts [
"-42000,78000"
"-42000,79000"
]
uid 25827,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "-42000,78000,-42000,79000"
)
oxt "7000,7000,7000,8000"
)
*707 (CommentGraphic
uid 25828,0
shape (CustomPolygon
pts [
"-43000,79000"
"-41000,79000"
"-42000,80000"
"-43000,79000"
]
uid 25829,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "32768,32768,32768"
bg "0,0,0"
lineWidth -1
)
xt "-43000,79000,-41000,80000"
)
oxt "6000,8000,8000,9000"
)
]
shape (Rectangle
uid 25831,0
va (VaSet
vasetType 1
transparent 1
fg "0,65535,0"
lineColor "65535,65535,65535"
lineWidth -1
)
xt "-43000,77000,-40000,80000"
fos 1
)
showPorts 0
oxt "6000,6000,9000,9000"
ttg (MlTextGroup
uid 25832,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*708 (Text
uid 25833,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-40550,77695,-35750,78695"
st "moduleware"
blo "-40550,78495"
)
*709 (Text
uid 25834,0
va (VaSet
font "arial,8,0"
)
xt "-40550,78695,-38850,79695"
st "gnd"
blo "-40550,79495"
)
*710 (Text
uid 25835,0
va (VaSet
font "arial,8,0"
)
xt "-40550,79695,-38750,80695"
st "U_6"
blo "-40550,80495"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 25836,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 25837,0
text (MLText
uid 25838,0
va (VaSet
font "arial,8,0"
)
xt "-48000,57400,-48000,57400"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
*711 (Net
uid 25840,0
decl (Decl
n "software_trigger_in"
t "std_logic"
o 125
suid 409,0
)
declText (MLText
uid 25841,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,118000,-146500,118800"
st "SIGNAL software_trigger_in          : std_logic"
)
)
*712 (PortIoOut
uid 26079,0
shape (CompositeShape
uid 26080,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 26081,0
sl 0
ro 270
xt "67500,85625,69000,86375"
)
(Line
uid 26082,0
sl 0
ro 270
xt "67000,86000,67500,86000"
pts [
"67000,86000"
"67500,86000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 26083,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 26084,0
va (VaSet
)
xt "70000,85500,77800,86500"
st "mem_manager_state"
blo "70000,86300"
tm "WireNameMgr"
)
)
)
*713 (Net
uid 26085,0
lang 2
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 411,0
)
declText (MLText
uid 26086,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,34400,-115000,35200"
st "mem_manager_state            : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
)
)
*714 (Net
uid 26334,0
decl (Decl
n "is_idle"
t "std_logic"
o 98
suid 413,0
)
declText (MLText
uid 26335,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,94800,-146500,95600"
st "SIGNAL is_idle                      : std_logic"
)
)
*715 (PortIoOut
uid 26350,0
shape (CompositeShape
uid 26351,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 26352,0
sl 0
ro 270
xt "7500,107625,9000,108375"
)
(Line
uid 26353,0
sl 0
ro 270
xt "7000,108000,7500,108000"
pts [
"7000,108000"
"7500,108000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 26354,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 26355,0
va (VaSet
)
xt "10000,107500,13600,108500"
st "DG_state"
blo "10000,108300"
tm "WireNameMgr"
)
)
)
*716 (Net
uid 26591,0
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 415,0
)
declText (MLText
uid 26592,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,17600,-140500,19200"
st "-- for debugging
DG_state                     : std_logic_vector(7 downto 0)"
)
)
*717 (SaComponent
uid 27117,0
optionalChildren [
*718 (CptPort
uid 27041,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27042,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,85625,59750,86375"
)
tg (CPTG
uid 27043,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27044,0
va (VaSet
)
xt "52700,85500,58000,86500"
st "state : (3:0)"
ju 2
blo "58000,86300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 1
)
)
)
*719 (CptPort
uid 27045,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27046,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28625,67250,29375,68000"
)
tg (CPTG
uid 27047,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27048,0
ro 270
va (VaSet
)
xt "28500,69000,29500,70500"
st "clk"
ju 2
blo "29300,69000"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
o 2
)
)
)
*720 (CptPort
uid 27049,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27050,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,75625,28000,76375"
)
tg (CPTG
uid 27051,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27052,0
va (VaSet
)
xt "29000,75500,34600,76500"
st "config_start"
blo "29000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 3
)
)
)
*721 (CptPort
uid 27053,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27054,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,72625,28000,73375"
)
tg (CPTG
uid 27055,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27056,0
va (VaSet
)
xt "29000,72500,36400,73500"
st "ram_write_ready"
blo "29000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_write_ready"
t "std_logic"
o 11
)
)
)
*722 (CptPort
uid 27057,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27058,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,85625,28000,86375"
)
tg (CPTG
uid 27059,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27060,0
va (VaSet
)
xt "29000,85500,32900,86500"
st "roi_array"
blo "29000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 5
)
)
)
*723 (CptPort
uid 27061,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27062,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,71625,28000,72375"
)
tg (CPTG
uid 27063,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27064,0
va (VaSet
)
xt "29000,71500,35100,72500"
st "ram_write_ea"
blo "29000,72300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ea"
t "std_logic"
o 12
i "'0'"
)
)
)
*724 (CptPort
uid 27065,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27066,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,76625,28000,77375"
)
tg (CPTG
uid 27067,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27068,0
va (VaSet
)
xt "29000,76500,34700,77500"
st "config_ready"
blo "29000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 4
i "'1'"
)
)
)
*725 (CptPort
uid 27069,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27070,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,78625,28000,79375"
)
tg (CPTG
uid 27071,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27072,0
va (VaSet
)
xt "29000,78500,32400,79500"
st "roi_max"
blo "29000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_max"
t "roi_max_type"
o 6
i "(others => conv_std_logic_vector (0, 11))"
)
)
)
*726 (CptPort
uid 27073,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27074,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,79625,28000,80375"
)
tg (CPTG
uid 27075,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27076,0
va (VaSet
)
xt "29000,79500,38900,80500"
st "package_length : (15:0)"
blo "29000,80300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 7
i "(others => '0')"
)
)
)
*727 (CptPort
uid 27077,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27078,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,73625,59750,74375"
)
tg (CPTG
uid 27079,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27080,0
va (VaSet
)
xt "35400,73500,58000,74500"
st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
ju 2
blo "58000,74300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
o 17
i "(others => '0')"
)
)
)
*728 (CptPort
uid 27081,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27082,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,72625,59750,73375"
)
tg (CPTG
uid 27083,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27084,0
va (VaSet
)
xt "47200,72500,58000,73500"
st "wiz_write_length : (16:0)"
ju 2
blo "58000,73300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 16
i "(others => '0')"
)
)
)
*729 (CptPort
uid 27085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27086,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,74625,59750,75375"
)
tg (CPTG
uid 27087,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27088,0
va (VaSet
)
xt "44800,74500,58000,75500"
st "wiz_number_of_channels : (3:0)"
ju 2
blo "58000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 8
i "(others => '0')"
)
)
)
*730 (CptPort
uid 27089,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27090,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,78625,59750,79375"
)
tg (CPTG
uid 27091,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27092,0
va (VaSet
)
xt "52000,78500,58000,79500"
st "wiz_write_ea"
ju 2
blo "58000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 15
i "'0'"
)
)
)
*731 (CptPort
uid 27093,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27094,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,76625,59750,77375"
)
tg (CPTG
uid 27095,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27096,0
va (VaSet
)
xt "50200,76500,58000,77500"
st "wiz_write_header"
ju 2
blo "58000,77300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_write_header"
t "std_logic"
o 18
i "'0'"
)
)
)
*732 (CptPort
uid 27097,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27098,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,75625,59750,76375"
)
tg (CPTG
uid 27099,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27100,0
va (VaSet
)
xt "51500,75500,58000,76500"
st "wiz_write_end"
ju 2
blo "58000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_write_end"
t "std_logic"
o 19
i "'0'"
)
)
)
*733 (CptPort
uid 27109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27110,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,70625,28000,71375"
)
tg (CPTG
uid 27111,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27112,0
va (VaSet
)
xt "29000,70500,49900,71500"
st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
blo "29000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)"
o 13
i "(others => '0')"
)
)
)
*734 (CptPort
uid 27113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27114,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,82625,59750,83375"
)
tg (CPTG
uid 27115,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27116,0
va (VaSet
)
xt "50800,82500,58000,83500"
st "data_ram_empty"
ju 2
blo "58000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_ram_empty"
t "std_logic"
o 20
)
)
)
*735 (CptPort
uid 27127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27128,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "59000,79625,59750,80375"
)
tg (CPTG
uid 27129,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 27130,0
va (VaSet
)
xt "51400,79500,58000,80500"
st "wiz_read_done"
ju 2
blo "58000,80300"
)
)
thePort (LogicalPort
decl (Decl
n "wiz_read_done"
t "std_logic"
o 14
)
)
)
*736 (CptPort
uid 27139,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27140,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,83625,28000,84375"
)
tg (CPTG
uid 27141,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27142,0
va (VaSet
)
xt "29000,83500,35700,84500"
st "dg_config_done"
blo "29000,84300"
)
)
thePort (LogicalPort
decl (Decl
n "dg_config_done"
t "std_logic"
o 10
)
)
)
*737 (CptPort
uid 27143,0
ps "OnEdgeStrategy"
shape (Triangle
uid 27144,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27250,82625,28000,83375"
)
tg (CPTG
uid 27145,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 27146,0
va (VaSet
)
xt "29000,82500,36000,83500"
st "dg_start_config"
blo "29000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dg_start_config"
t "std_logic"
o 9
i "'0'"
)
)
)
]
shape (Rectangle
uid 27118,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "28000,68000,59000,88000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 27119,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*738 (Text
uid 27120,0
va (VaSet
font "Arial,8,1"
)
xt "28450,88000,34650,89000"
st "FACT_FAD_lib"
blo "28450,88800"
tm "BdLibraryNameMgr"
)
*739 (Text
uid 27121,0
va (VaSet
font "Arial,8,1"
)
xt "28450,89000,36550,90000"
st "memory_manager_2"
blo "28450,89800"
tm "CptNameMgr"
)
*740 (Text
uid 27122,0
va (VaSet
font "Arial,8,1"
)
xt "28450,90000,38750,91000"
st "Inst_memory_manager_2"
blo "28450,90800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 27123,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 27124,0
text (MLText
uid 27125,0
va (VaSet
font "Courier New,8,0"
)
xt "34000,66400,63500,68000"
st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer )  
RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH_64B"
type "integer"
value "RAMADDRWIDTH64b"
)
(GiElement
name "RAM_ADDR_WIDTH_16B"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
)
viewicon (ZoomableIcon
uid 27126,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "28250,86250,29750,87750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*741 (Net
uid 27131,0
decl (Decl
n "data_valid_ack"
t "std_logic"
o 72
suid 416,0
i "'0'"
)
declText (MLText
uid 27132,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,69200,-125500,70000"
st "SIGNAL data_valid_ack               : std_logic                                    := '0'"
)
)
*742 (Net
uid 27147,0
decl (Decl
n "dg_start_config"
t "std_logic"
o 76
suid 417,0
i "'0'"
)
declText (MLText
uid 27148,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,72400,-125500,73200"
st "SIGNAL dg_start_config              : std_logic                                    := '0'"
)
)
*743 (Net
uid 27153,0
decl (Decl
n "dg_config_done"
t "std_logic"
o 75
suid 418,0
)
declText (MLText
uid 27154,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,71600,-146500,72400"
st "SIGNAL dg_config_done               : std_logic"
)
)
*744 (Net
uid 27603,0
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 6"
preAdd 0
posAdd 0
o 117
suid 419,0
)
declText (MLText
uid 27604,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,110800,-136500,112400"
st "-- EVT HEADER - part 6
SIGNAL runnumber                    : std_logic_vector(31 downto 0)"
)
)
*745 (Net
uid 28276,0
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 421,0
)
declText (MLText
uid 28277,0
va (VaSet
font "Courier New,8,0"
)
xt "-172000,38400,-125000,39200"
st "socket_tx_free_out           : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
)
)
*746 (PortIoOut
uid 28284,0
shape (CompositeShape
uid 28285,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 28286,0
sl 0
ro 270
xt "139500,113625,141000,114375"
)
(Line
uid 28287,0
sl 0
ro 270
xt "139000,114000,139500,114000"
pts [
"139000,114000"
"139500,114000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 28288,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 28289,0
va (VaSet
)
xt "142000,113500,148900,114500"
st "socket_tx_free_out"
blo "142000,114300"
tm "WireNameMgr"
)
)
)
*747 (MWC
uid 29010,0
optionalChildren [
*748 (CptPort
uid 29019,0
optionalChildren [
*749 (Line
uid 29023,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "24000,94000,25589,94000"
pts [
"24000,94000"
"25589,94000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 29020,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "23250,93625,24000,94375"
)
tg (CPTG
uid 29021,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 29022,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-141550,93300,-139750,94300"
st "din1"
blo "-141550,94100"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
o 144
)
)
)
*750 (CptPort
uid 29024,0
optionalChildren [
*751 (Property
uid 29028,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
*752 (Line
uid 29029,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "29000,95000,30000,95000"
pts [
"30000,95000"
"29000,95000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 29025,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "30000,94625,30750,95375"
)
tg (CPTG
uid 29026,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 29027,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-138300,94468,-136500,95468"
st "dout"
ju 2
blo "-136500,95268"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 146
)
)
)
*753 (CptPort
uid 29030,0
optionalChildren [
*754 (Line
uid 29034,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "24000,96000,25589,96000"
pts [
"24000,96000"
"25589,96000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 29031,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "23250,95625,24000,96375"
)
tg (CPTG
uid 29032,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 29033,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "-141435,95706,-139635,96706"
st "din0"
blo "-141435,96506"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 145
i "'1'"
)
)
)
*755 (CommentGraphic
uid 29035,0
shape (Arc2D
pts [
"29000,95000"
"27263,96479"
"25000,96996"
]
uid 29036,0
layer 8
sl 0
ro 180
va (VaSet
vasetType 1
fg "0,65535,65535"
bg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "25000,95000,29000,96997"
)
oxt "43000,182000,47000,183997"
)
*756 (CommentGraphic
uid 29037,0
shape (Arc2D
pts [
"24996,93002"
"27449,93606"
"29000,94995"
]
uid 29038,0
layer 0
sl 0
ro 180
va (VaSet
vasetType 1
fg "0,65535,65535"
bg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "24996,93000,29000,94995"
)
oxt "42996,180000,47000,181995"
)
*757 (Grouping
uid 29039,0
optionalChildren [
*758 (CommentGraphic
uid 29041,0
optionalChildren [
*759 (Property
uid 29043,0
pclass "_MW_GEOM_"
pname "arc"
ptn "String"
)
]
shape (CustomPolygon
pts [
"25000,93002"
"27048,93868"
"29000,95000"
"27952,95844"
"26183,96789"
"25000,97000"
"25000,93002"
]
uid 29042,0
layer 0
sl 0
ro 180
va (VaSet
vasetType 1
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prms (Property
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uid 33507,0
ps "OnEdgeStrategy"
shape (Triangle
uid 33508,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51000,46625,51750,47375"
)
tg (CPTG
uid 33509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 33510,0
va (VaSet
font "arial,8,0"
)
xt "48300,46500,50000,47500"
st "clkb"
ju 2
blo "50000,47300"
)
)
thePort (LogicalPort
decl (Decl
n "clkb"
t "std_logic"
preAdd 0
posAdd 0
o 5
suid 5,0
)
)
)
*927 (CptPort
uid 33511,0
ps "OnEdgeStrategy"
shape (Triangle
uid 33512,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51000,51625,51750,52375"
)
tg (CPTG
uid 33513,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 33514,0
va (VaSet
font "arial,8,0"
)
xt "44700,51500,50000,52500"
st "addrb : (16:0)"
ju 2
blo "50000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "addrb"
t "std_logic_VECTOR"
b "(16 downto 0)"
preAdd 0
posAdd 0
o 6
suid 6,0
)
)
)
*928 (CptPort
uid 33515,0
ps "OnEdgeStrategy"
shape (Triangle
uid 33516,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "51000,52625,51750,53375"
)
tg (CPTG
uid 33517,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 33518,0
va (VaSet
font "arial,8,0"
)
xt "44800,52500,50000,53500"
st "doutb : (15:0)"
ju 2
blo "50000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "doutb"
t "std_logic_VECTOR"
b "(15 downto 0)"
preAdd 0
posAdd 0
o 7
suid 7,0
)
)
)
]
shape (Rectangle
uid 33523,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "37000,45000,51000,55000"
)
oxt "30000,11000,44000,21000"
ttg (MlTextGroup
uid 33524,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*929 (Text
uid 33525,0
va (VaSet
font "arial,8,1"
)
xt "37200,55000,43400,56000"
st "FACT_FAD_lib"
blo "37200,55800"
tm "BdLibraryNameMgr"
)
*930 (Text
uid 33526,0
va (VaSet
font "arial,8,1"
)
xt "37200,56000,49200,57000"
st "dataRAM_64b_16b_width14_5"
blo "37200,56800"
tm "CptNameMgr"
)
*931 (Text
uid 33527,0
va (VaSet
font "arial,8,1"
)
xt "37200,57000,43600,58000"
st "data_RAM_inst"
blo "37200,57800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 33528,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 33529,0
text (MLText
uid 33530,0
va (VaSet
font "Courier New,8,0"
)
xt "36500,40000,36500,40000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 33531,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "37250,53250,38750,54750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*932 (Wire
uid 322,0
shape (OrthoPolyLine
uid 323,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3750,51000,36250,54000"
pts [
"3750,54000"
"4000,54000"
"4000,51000"
"36250,51000"
]
)
start &63
end &925
ss 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 324,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 325,0
va (VaSet
)
xt "5000,53000,11600,54000"
st "write_ea : (0:0)"
blo "5000,53800"
tm "WireNameMgr"
)
)
on &2
)
*933 (Wire
uid 328,0
shape (OrthoPolyLine
uid 329,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3750,52000,36250,55000"
pts [
"3750,55000"
"5000,55000"
"5000,52000"
"36250,52000"
]
)
start &25
end &924
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 330,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 331,0
va (VaSet
)
xt "5000,54000,21200,55000"
st "addr_out : (RAMADDRWIDTH64b-1:0)"
blo "5000,54800"
tm "WireNameMgr"
)
)
on &3
)
*934 (Wire
uid 334,0
shape (OrthoPolyLine
uid 335,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3750,53000,36250,56000"
pts [
"3750,56000"
"7000,56000"
"7000,53000"
"36250,53000"
]
)
start &24
end &923
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 337,0
va (VaSet
)
xt "5000,55000,12200,56000"
st "data_out : (63:0)"
blo "5000,55800"
tm "WireNameMgr"
)
)
on &4
)
*935 (Wire
uid 364,0
shape (OrthoPolyLine
uid 365,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51750,52000,87250,56000"
pts [
"87250,56000"
"83000,56000"
"83000,52000"
"51750,52000"
]
)
start &102
end &927
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 367,0
va (VaSet
)
xt "54000,51000,70400,52000"
st "ram_addr : (RAMADDRWIDTH64b+1:0)"
blo "54000,51800"
tm "WireNameMgr"
)
)
on &5
)
*936 (Wire
uid 370,0
shape (OrthoPolyLine
uid 371,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51750,53000,87250,57000"
pts [
"87250,57000"
"82000,57000"
"82000,53000"
"51750,53000"
]
)
start &101
end &928
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 373,0
va (VaSet
)
xt "55000,53000,62300,54000"
st "ram_data : (15:0)"
blo "55000,53800"
tm "WireNameMgr"
)
)
on &6
)
*937 (Wire
uid 376,0
shape (OrthoPolyLine
uid 377,0
va (VaSet
vasetType 3
)
xt "137000,54000,147000,55000"
pts [
"137000,55000"
"147000,54000"
]
)
start &842
end &14
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 381,0
va (VaSet
isHidden 1
)
xt "155000,54000,159200,55000"
st "wiz_reset"
blo "155000,54800"
tm "WireNameMgr"
)
)
on &7
)
*938 (Wire
uid 384,0
shape (OrthoPolyLine
uid 385,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "124750,62000,128000,62000"
pts [
"124750,62000"
"128000,62000"
]
)
start &93
end &15
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
isHidden 1
)
xt "142000,61000,146000,62000"
st "wiz_addr"
blo "142000,61800"
tm "WireNameMgr"
)
)
on &8
)
*939 (Wire
uid 392,0
shape (OrthoPolyLine
uid 393,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "124750,63000,128000,63000"
pts [
"124750,63000"
"128000,63000"
]
)
start &94
end &16
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 396,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 397,0
va (VaSet
isHidden 1
)
xt "141000,62000,144900,63000"
st "wiz_data"
blo "141000,62800"
tm "WireNameMgr"
)
)
on &9
)
*940 (Wire
uid 400,0
shape (OrthoPolyLine
uid 401,0
va (VaSet
vasetType 3
)
xt "124750,55000,128000,55000"
pts [
"124750,55000"
"128000,55000"
]
)
start &95
end &17
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 404,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 405,0
va (VaSet
isHidden 1
)
xt "142000,54000,145000,55000"
st "wiz_cs"
blo "142000,54800"
tm "WireNameMgr"
)
)
on &10
)
*941 (Wire
uid 408,0
shape (OrthoPolyLine
uid 409,0
va (VaSet
vasetType 3
)
xt "124750,56000,128000,56000"
pts [
"124750,56000"
"128000,56000"
]
)
start &96
end &18
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 412,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 413,0
va (VaSet
isHidden 1
)
xt "142000,55000,145200,56000"
st "wiz_wr"
blo "142000,55800"
tm "WireNameMgr"
)
)
on &11
)
*942 (Wire
uid 424,0
shape (OrthoPolyLine
uid 425,0
va (VaSet
vasetType 3
)
xt "124750,57000,128000,57000"
pts [
"124750,57000"
"128000,57000"
]
)
start &97
end &20
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
isHidden 1
)
xt "142000,56000,145100,57000"
st "wiz_rd"
blo "142000,56800"
tm "WireNameMgr"
)
)
on &12
)
*943 (Wire
uid 432,0
shape (OrthoPolyLine
uid 433,0
va (VaSet
vasetType 3
)
xt "124750,58000,128000,58000"
pts [
"128000,58000"
"124750,58000"
]
)
start &21
end &98
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 436,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 437,0
va (VaSet
isHidden 1
)
xt "141000,57000,144200,58000"
st "wiz_int"
blo "141000,57800"
tm "WireNameMgr"
)
)
on &13
)
*944 (Wire
uid 1411,0
shape (OrthoPolyLine
uid 1412,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-69000,97000,-24750,97000"
pts [
"-69000,97000"
"-24750,97000"
]
)
start &171
end &27
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1415,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1416,0
va (VaSet
)
xt "-67000,96000,-63200,97000"
st "board_id"
blo "-67000,96800"
tm "WireNameMgr"
)
)
on &87
)
*945 (Wire
uid 1425,0
shape (OrthoPolyLine
uid 1426,0
va (VaSet
vasetType 3
)
xt "-129000,68000,-125000,68000"
pts [
"-129000,68000"
"-125000,68000"
]
)
start &89
end &341
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1429,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1430,0
va (VaSet
isHidden 1
)
xt "-134000,66000,-131000,67000"
st "trigger"
blo "-134000,66800"
tm "WireNameMgr"
)
)
on &88
)
*946 (Wire
uid 1682,0
shape (OrthoPolyLine
uid 1683,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-69000,98000,-24750,98000"
pts [
"-69000,98000"
"-24750,98000"
]
)
start &172
end &28
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1686,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1687,0
va (VaSet
)
xt "-67000,97000,-63400,98000"
st "crate_id"
blo "-67000,97800"
tm "WireNameMgr"
)
)
on &148
)
*947 (Wire
uid 2299,0
shape (OrthoPolyLine
uid 2300,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3750,71000,27250,74000"
pts [
"27250,71000"
"7000,71000"
"7000,74000"
"3750,74000"
]
)
start &733
end &26
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2303,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2304,0
va (VaSet
)
xt "4000,73000,22900,74000"
st "ram_start_addr : (RAMADDRWIDTH64b-1:0)"
blo "4000,73800"
tm "WireNameMgr"
)
)
on &157
)
*948 (Wire
uid 2476,0
shape (OrthoPolyLine
uid 2477,0
va (VaSet
vasetType 3
)
xt "59750,79000,87250,79000"
pts [
"59750,79000"
"87250,79000"
]
)
start &730
end &103
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2478,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2479,0
va (VaSet
)
xt "60000,78000,66000,79000"
st "wiz_write_ea"
blo "60000,78800"
tm "WireNameMgr"
)
)
on &158
)
*949 (Wire
uid 2482,0
shape (OrthoPolyLine
uid 2483,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59750,73000,87250,73000"
pts [
"59750,73000"
"87250,73000"
]
)
start &728
end &99
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2485,0
va (VaSet
)
xt "60000,72000,70800,73000"
st "wiz_write_length : (16:0)"
blo "60000,72800"
tm "WireNameMgr"
)
)
on &159
)
*950 (Wire
uid 2488,0
shape (OrthoPolyLine
uid 2489,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59750,74000,87250,74000"
pts [
"59750,74000"
"87250,74000"
]
)
start &727
end &100
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2490,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2491,0
va (VaSet
)
xt "60000,73000,81200,74000"
st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
blo "60000,73800"
tm "WireNameMgr"
)
)
on &160
)
*951 (Wire
uid 2494,0
shape (OrthoPolyLine
uid 2495,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59750,75000,87250,75000"
pts [
"59750,75000"
"87250,75000"
]
)
start &729
end &105
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2496,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2497,0
va (VaSet
)
xt "60000,74000,73200,75000"
st "wiz_number_of_channels : (3:0)"
blo "60000,74800"
tm "WireNameMgr"
)
)
on &161
)
*952 (Wire
uid 2500,0
shape (OrthoPolyLine
uid 2501,0
va (VaSet
vasetType 3
)
xt "59750,76000,87250,76000"
pts [
"59750,76000"
"87250,76000"
]
)
start &732
end &106
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2502,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2503,0
va (VaSet
)
xt "60000,75000,66500,76000"
st "wiz_write_end"
blo "60000,75800"
tm "WireNameMgr"
)
)
on &162
)
*953 (Wire
uid 2506,0
shape (OrthoPolyLine
uid 2507,0
va (VaSet
vasetType 3
)
xt "59750,77000,87250,77000"
pts [
"59750,77000"
"87250,77000"
]
)
start &731
end &107
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2508,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2509,0
va (VaSet
)
xt "60000,76000,67800,77000"
st "wiz_write_header"
blo "60000,76800"
tm "WireNameMgr"
)
)
on &163
)
*954 (Wire
uid 2576,0
optionalChildren [
*955 (BdJunction
uid 29083,0
ps "OnConnectorStrategy"
shape (Circle
uid 29084,0
va (VaSet
vasetType 1
)
xt "11600,71600,12400,72400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 2577,0
va (VaSet
vasetType 3
)
xt "3750,72000,27250,75000"
pts [
"3750,75000"
"8000,75000"
"8000,72000"
"27250,72000"
]
)
start &29
end &723
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2578,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2579,0
va (VaSet
)
xt "4000,74000,10100,75000"
st "ram_write_ea"
blo "4000,74800"
tm "WireNameMgr"
)
)
on &164
)
*956 (Wire
uid 2582,0
shape (OrthoPolyLine
uid 2583,0
va (VaSet
vasetType 3
)
xt "3750,73000,27250,76000"
pts [
"3750,76000"
"10000,76000"
"10000,73000"
"27250,73000"
]
)
start &30
end &721
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2584,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2585,0
va (VaSet
)
xt "4000,75000,11400,76000"
st "ram_write_ready"
blo "4000,75800"
tm "WireNameMgr"
)
)
on &165
)
*957 (Wire
uid 2600,0
shape (OrthoPolyLine
uid 2601,0
va (VaSet
vasetType 3
)
xt "3750,79000,27250,82000"
pts [
"3750,82000"
"10000,82000"
"10000,79000"
"27250,79000"
]
)
start &31
end &725
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2602,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2603,0
va (VaSet
)
xt "4000,81000,7400,82000"
st "roi_max"
blo "4000,81800"
tm "WireNameMgr"
)
)
on &166
)
*958 (Wire
uid 2642,0
shape (OrthoPolyLine
uid 2643,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3750,80000,27250,83000"
pts [
"3750,83000"
"7000,83000"
"7000,80000"
"27250,80000"
]
)
start &33
end &726
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2644,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2645,0
va (VaSet
)
xt "4000,82000,13900,83000"
st "package_length : (15:0)"
blo "4000,82800"
tm "WireNameMgr"
)
)
on &167
)
*959 (Wire
uid 2778,0
shape (OrthoPolyLine
uid 2779,0
va (VaSet
vasetType 3
)
xt "-69000,94000,-24750,94000"
pts [
"-24750,94000"
"-69000,94000"
]
)
start &62
end &169
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2782,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2783,0
va (VaSet
isHidden 1
)
xt "-63000,88000,-59500,89000"
st "adc_oeb"
blo "-63000,88800"
tm "WireNameMgr"
)
)
on &168
)
*960 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-66000,86000,-58750,86000"
pts [
"-66000,86000"
"-58750,86000"
]
)
start &170
end &242
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2790,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2791,0
va (VaSet
isHidden 1
)
xt "-97000,79000,-90600,80000"
st "adc_otr_array"
blo "-97000,79800"
tm "WireNameMgr"
)
)
on &190
)
*961 (Wire
uid 3984,0
optionalChildren [
*962 (BdJunction
uid 19235,0
ps "OnConnectorStrategy"
shape (Circle
uid 19236,0
va (VaSet
vasetType 1
)
xt "-39400,23600,-38600,24400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 3985,0
va (VaSet
vasetType 3
lineColor "49152,0,0"
)
xt "-41250,24000,-37000,24000"
pts [
"-37000,24000"
"-41250,24000"
]
)
start &185
end &300
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3986,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3987,0
va (VaSet
isHidden 1
)
xt "-69000,30000,-64200,31000"
st "CLK_25_PS"
blo "-69000,30800"
tm "WireNameMgr"
)
)
on &184
)
*963 (Wire
uid 4042,0
shape (OrthoPolyLine
uid 4043,0
va (VaSet
vasetType 3
)
xt "-66000,22000,-60750,22000"
pts [
"-66000,22000"
"-60750,22000"
]
)
start &1
end &299
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4044,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4045,0
va (VaSet
isHidden 1
)
xt "-65000,35000,-63100,36000"
st "CLK"
blo "-65000,35800"
tm "WireNameMgr"
)
)
on &189
)
*964 (Wire
uid 4226,0
shape (OrthoPolyLine
uid 4227,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "-41250,22000,-37000,22000"
pts [
"-37000,22000"
"-41250,22000"
]
)
start &188
end &297
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4228,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4229,0
va (VaSet
isHidden 1
)
xt "-75000,26000,-71700,27000"
st "CLK_50"
blo "-75000,26800"
tm "WireNameMgr"
)
)
on &186
)
*965 (Wire
uid 4240,0
shape (OrthoPolyLine
uid 4241,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "86000,49000,91000,54000"
pts [
"87250,54000"
"86000,54000"
"86000,49000"
"91000,49000"
]
)
start &91
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4242,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4243,0
va (VaSet
)
xt "87000,48000,90300,49000"
st "CLK_50"
blo "87000,48800"
tm "WireNameMgr"
)
)
on &186
)
*966 (Wire
uid 4272,0
shape (OrthoPolyLine
uid 4273,0
va (VaSet
vasetType 3
)
xt "-66000,85000,-58750,85000"
pts [
"-66000,85000"
"-58750,85000"
]
)
start &192
end &239
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4274,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4275,0
va (VaSet
isHidden 1
)
xt "-96000,79000,-89100,80000"
st "adc_data_array"
blo "-96000,79800"
tm "WireNameMgr"
)
)
on &191
)
*967 (Wire
uid 4401,0
shape (OrthoPolyLine
uid 4402,0
va (VaSet
vasetType 3
)
xt "-38250,52000,-24750,59000"
pts [
"-24750,59000"
"-35000,59000"
"-35000,52000"
"-38250,52000"
]
)
start &36
end &211
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4404,0
va (VaSet
)
xt "-29750,58000,-24650,59000"
st "drs_clk_en"
blo "-29750,58800"
tm "WireNameMgr"
)
)
on &193
)
*968 (Wire
uid 4407,0
shape (OrthoPolyLine
uid 4408,0
va (VaSet
vasetType 3
)
xt "-38250,51000,-24750,58000"
pts [
"-24750,58000"
"-34000,58000"
"-34000,51000"
"-38250,51000"
]
)
start &38
end &217
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4409,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4410,0
va (VaSet
)
xt "-31750,57000,-24450,58000"
st "drs_s_cell_array"
blo "-31750,57800"
tm "WireNameMgr"
)
)
on &194
)
*969 (Wire
uid 4419,0
shape (OrthoPolyLine
uid 4420,0
va (VaSet
vasetType 3
)
xt "-38250,49000,-24750,56000"
pts [
"-24750,56000"
"-32000,56000"
"-32000,49000"
"-38250,49000"
]
)
start &64
end &212
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4421,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4422,0
va (VaSet
)
xt "-31750,55000,-24750,56000"
st "drs_read_s_cell"
blo "-31750,55800"
tm "WireNameMgr"
)
)
on &195
)
*970 (Wire
uid 4537,0
shape (OrthoPolyLine
uid 4538,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-29000,70000,-24750,70000"
pts [
"-24750,70000"
"-29000,70000"
]
)
start &35
end &198
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4541,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4542,0
va (VaSet
isHidden 1
)
xt "-64000,68000,-57400,69000"
st "drs_channel_id"
blo "-64000,68800"
tm "WireNameMgr"
)
)
on &196
)
*971 (Wire
uid 4545,0
shape (OrthoPolyLine
uid 4546,0
va (VaSet
vasetType 3
)
xt "-98000,77000,-94000,77000"
pts [
"-94000,77000"
"-98000,77000"
]
)
start &277
end &199
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4549,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4550,0
va (VaSet
)
xt "-98000,76000,-92800,77000"
st "drs_dwrite"
blo "-98000,76800"
tm "WireNameMgr"
)
)
on &197
)
*972 (Wire
uid 4671,0
shape (OrthoPolyLine
uid 4672,0
va (VaSet
vasetType 3
)
xt "-66000,50000,-58750,50000"
pts [
"-66000,50000"
"-58750,50000"
]
)
start &204
end &213
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4675,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4676,0
va (VaSet
isHidden 1
)
xt "-65000,49000,-59200,50000"
st "SROUT_in_0"
blo "-65000,49800"
tm "WireNameMgr"
)
)
on &200
)
*973 (Wire
uid 4679,0
shape (OrthoPolyLine
uid 4680,0
va (VaSet
vasetType 3
)
xt "-66000,51000,-58750,51000"
pts [
"-66000,51000"
"-58750,51000"
]
)
start &205
end &214
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4683,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4684,0
va (VaSet
isHidden 1
)
xt "-65000,50000,-59300,51000"
st "SROUT_in_1"
blo "-65000,50800"
tm "WireNameMgr"
)
)
on &201
)
*974 (Wire
uid 4687,0
shape (OrthoPolyLine
uid 4688,0
va (VaSet
vasetType 3
)
xt "-66000,52000,-58750,52000"
pts [
"-66000,52000"
"-58750,52000"
]
)
start &206
end &215
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4691,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4692,0
va (VaSet
isHidden 1
)
xt "-65000,51000,-59200,52000"
st "SROUT_in_2"
blo "-65000,51800"
tm "WireNameMgr"
)
)
on &202
)
*975 (Wire
uid 4695,0
shape (OrthoPolyLine
uid 4696,0
va (VaSet
vasetType 3
)
xt "-66000,53000,-58750,53000"
pts [
"-66000,53000"
"-58750,53000"
]
)
start &207
end &216
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4699,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4700,0
va (VaSet
isHidden 1
)
xt "-65000,52000,-59200,53000"
st "SROUT_in_3"
blo "-65000,52800"
tm "WireNameMgr"
)
)
on &203
)
*976 (Wire
uid 4743,0
shape (OrthoPolyLine
uid 4744,0
va (VaSet
vasetType 3
)
xt "-38250,50000,-24750,57000"
pts [
"-38250,50000"
"-33000,50000"
"-33000,57000"
"-24750,57000"
]
)
start &218
end &37
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4747,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4748,0
va (VaSet
)
xt "-36250,53000,-26150,54000"
st "drs_read_s_cell_ready"
blo "-36250,53800"
tm "WireNameMgr"
)
)
on &208
)
*977 (Wire
uid 4948,0
shape (OrthoPolyLine
uid 4949,0
va (VaSet
vasetType 3
)
xt "-66000,54000,-58750,54000"
pts [
"-58750,54000"
"-66000,54000"
]
)
start &219
end &230
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4953,0
va (VaSet
isHidden 1
)
xt "-64000,53000,-59800,54000"
st "RSRLOAD"
blo "-64000,53800"
tm "WireNameMgr"
)
)
on &229
)
*978 (Wire
uid 4962,0
shape (OrthoPolyLine
uid 4963,0
va (VaSet
vasetType 3
)
xt "-73000,57000,-72000,57000"
pts [
"-72000,57000"
"-73000,57000"
]
)
start &315
end &232
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4966,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4967,0
va (VaSet
isHidden 1
)
xt "-73000,56000,-70100,57000"
st "SRCLK"
blo "-73000,56800"
tm "WireNameMgr"
)
)
on &231
)
*979 (Wire
uid 5222,0
shape (OrthoPolyLine
uid 5223,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "124750,73000,130000,73000"
pts [
"124750,73000"
"130000,73000"
]
)
start &108
end &19
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5224,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5225,0
va (VaSet
isHidden 1
)
xt "142750,72000,144250,73000"
st "led"
blo "142750,72800"
tm "WireNameMgr"
)
)
on &233
)
*980 (Wire
uid 5474,0
shape (OrthoPolyLine
uid 5475,0
va (VaSet
vasetType 3
)
xt "-2250,112000,3750,121000"
pts [
"-2250,121000"
"1000,121000"
"1000,112000"
"3750,112000"
]
)
start &253
end &41
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5477,0
va (VaSet
)
xt "-250,120000,5650,121000"
st "sensor_ready"
blo "-250,120800"
tm "WireNameMgr"
)
)
on &234
)
*981 (Wire
uid 5480,0
shape (OrthoPolyLine
uid 5481,0
va (VaSet
vasetType 3
)
xt "-2250,111000,3750,122000"
pts [
"-2250,122000"
"2000,122000"
"2000,111000"
"3750,111000"
]
)
start &252
end &40
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5482,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5483,0
va (VaSet
)
xt "-250,121000,5550,122000"
st "sensor_array"
blo "-250,121800"
tm "WireNameMgr"
)
)
on &235
)
*982 (Wire
uid 5602,0
shape (OrthoPolyLine
uid 5603,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-30000,54000,-24750,54000"
pts [
"-24750,54000"
"-30000,54000"
]
)
start &23
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5604,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5605,0
va (VaSet
)
xt "-29000,53000,-25700,54000"
st "CLK_25"
blo "-29000,53800"
tm "WireNameMgr"
)
)
on &187
)
*983 (Wire
uid 5626,0
shape (OrthoPolyLine
uid 5627,0
va (VaSet
vasetType 3
)
xt "-39250,85000,-24750,88000"
pts [
"-24750,88000"
"-28000,88000"
"-28000,85000"
"-39250,85000"
]
)
start &39
end &240
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5630,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5631,0
va (VaSet
)
xt "-31750,87000,-23350,88000"
st "adc_data_array_int"
blo "-31750,87800"
tm "WireNameMgr"
)
)
on &237
)
*984 (Wire
uid 5634,0
shape (OrthoPolyLine
uid 5635,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-39250,86000,-24750,89000"
pts [
"-24750,89000"
"-29000,89000"
"-29000,86000"
"-39250,86000"
]
)
start &34
end &241
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 5638,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5639,0
va (VaSet
)
xt "-31750,88000,-25450,89000"
st "adc_otr : (3:0)"
blo "-31750,88800"
tm "WireNameMgr"
)
)
on &236
)
*985 (Wire
uid 5646,0
shape (OrthoPolyLine
uid 5647,0
va (VaSet
vasetType 3
lineColor "49152,0,0"
)
xt "-66000,83000,-58750,83000"
pts [
"-66000,83000"
"-58750,83000"
]
)
end &243
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5652,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5653,0
va (VaSet
)
xt "-65000,82000,-60200,83000"
st "CLK_25_PS"
blo "-65000,82800"
tm "WireNameMgr"
)
)
on &184
)
*986 (Wire
uid 5805,0
shape (OrthoPolyLine
uid 5806,0
va (VaSet
vasetType 3
)
xt "-24000,121000,-19750,121000"
pts [
"-24000,121000"
"-19750,121000"
]
)
end &256
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 5809,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5810,0
va (VaSet
)
xt "-23000,120000,-19700,121000"
st "CLK_50"
blo "-23000,120800"
tm "WireNameMgr"
)
)
on &186
)
*987 (Wire
uid 5813,0
shape (OrthoPolyLine
uid 5814,0
va (VaSet
vasetType 3
)
xt "-28000,129000,-19750,129000"
pts [
"-19750,129000"
"-28000,129000"
]
)
start &248
end &268
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5817,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5818,0
va (VaSet
isHidden 1
)
xt "-24000,128000,-22100,129000"
st "sclk"
blo "-24000,128800"
tm "WireNameMgr"
)
)
on &264
)
*988 (Wire
uid 5821,0
shape (OrthoPolyLine
uid 5822,0
va (VaSet
vasetType 3
)
xt "-28000,128000,-19750,128000"
pts [
"-19750,128000"
"-28000,128000"
]
)
start &258
end &269
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5825,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5826,0
va (VaSet
isHidden 1
)
xt "-27000,127000,-25600,128000"
st "sio"
blo "-27000,127800"
tm "WireNameMgr"
)
)
on &265
)
*989 (Wire
uid 5829,0
shape (OrthoPolyLine
uid 5830,0
va (VaSet
vasetType 3
)
xt "-28000,125000,-19750,125000"
pts [
"-19750,125000"
"-28000,125000"
]
)
start &254
end &270
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5834,0
va (VaSet
isHidden 1
)
xt "-27000,124000,-24000,125000"
st "dac_cs"
blo "-27000,124800"
tm "WireNameMgr"
)
)
on &266
)
*990 (Wire
uid 5837,0
shape (OrthoPolyLine
uid 5838,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-28000,124000,-19750,124000"
pts [
"-19750,124000"
"-28000,124000"
]
)
start &255
end &271
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5841,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5842,0
va (VaSet
isHidden 1
)
xt "-27000,123000,-22900,124000"
st "sensor_cs"
blo "-27000,123800"
tm "WireNameMgr"
)
)
on &267
)
*991 (Wire
uid 6064,0
shape (OrthoPolyLine
uid 6065,0
va (VaSet
vasetType 3
)
xt "3750,100000,13000,100000"
pts [
"13000,100000"
"3750,100000"
]
)
end &42
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6068,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6069,0
va (VaSet
)
xt "5000,99000,13000,100000"
st "current_dac_array"
blo "5000,99800"
tm "WireNameMgr"
)
)
on &545
)
*992 (Wire
uid 6072,0
shape (OrthoPolyLine
uid 6073,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-41250,23000,-26000,23000"
pts [
"-41250,23000"
"-26000,23000"
]
)
start &298
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6074,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6075,0
va (VaSet
)
xt "-29000,22000,-25700,23000"
st "CLK_25"
blo "-29000,22800"
tm "WireNameMgr"
)
)
on &187
)
*993 (Wire
uid 6160,0
shape (OrthoPolyLine
uid 6161,0
va (VaSet
vasetType 3
)
xt "-28000,127000,-19750,127000"
pts [
"-19750,127000"
"-28000,127000"
]
)
start &257
end &273
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6164,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6165,0
va (VaSet
isHidden 1
)
xt "-27000,126000,-25000,127000"
st "mosi"
blo "-27000,126800"
tm "WireNameMgr"
)
)
on &272
)
*994 (Wire
uid 6276,0
shape (OrthoPolyLine
uid 6277,0
va (VaSet
vasetType 3
)
xt "-58000,64000,-52750,64000"
pts [
"-58000,64000"
"-52750,64000"
]
)
end &152
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 6280,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6281,0
va (VaSet
)
xt "-58000,63000,-53200,64000"
st "CLK_25_PS"
blo "-58000,63800"
tm "WireNameMgr"
)
)
on &184
)
*995 (Wire
uid 6362,0
shape (OrthoPolyLine
uid 6363,0
va (VaSet
vasetType 3
)
xt "169000,83000,179000,88000"
pts [
"169000,83000"
"169000,88000"
"179000,88000"
]
)
start &659
end &275
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6367,0
ro 270
va (VaSet
isHidden 1
)
xt "168000,81800,169000,85000"
st "denable"
blo "168800,85000"
tm "WireNameMgr"
)
)
on &274
)
*996 (Wire
uid 6452,0
shape (OrthoPolyLine
uid 6453,0
va (VaSet
vasetType 3
)
xt "124750,80000,134000,80000"
pts [
"124750,80000"
"134000,80000"
]
)
start &111
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6456,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6457,0
va (VaSet
)
xt "125000,79000,134300,80000"
st "dwrite_enable_w5300"
blo "125000,79800"
tm "WireNameMgr"
)
)
on &625
)
*997 (Wire
uid 6540,0
shape (OrthoPolyLine
uid 6541,0
va (VaSet
vasetType 3
)
xt "-88000,76000,-72750,76000"
pts [
"-88000,76000"
"-72750,76000"
]
)
start &280
end &410
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6543,0
va (VaSet
)
xt "-88000,75000,-77500,76000"
st "dwrite_trigger_manager"
blo "-88000,75800"
tm "WireNameMgr"
)
)
on &646
)
*998 (Wire
uid 6548,0
shape (OrthoPolyLine
uid 6549,0
va (VaSet
vasetType 3
)
xt "-88000,78000,-42000,123000"
pts [
"-51000,123000"
"-42000,123000"
"-42000,111000"
"-77000,111000"
"-77000,78000"
"-88000,78000"
]
)
start &628
end &282
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6552,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6553,0
va (VaSet
)
xt "-51000,122000,-41700,123000"
st "dwrite_global_enable"
blo "-51000,122800"
tm "WireNameMgr"
)
)
on &626
)
*999 (Wire
uid 8752,0
shape (OrthoPolyLine
uid 8753,0
va (VaSet
vasetType 3
)
xt "124750,81000,134000,81000"
pts [
"124750,81000"
"134000,81000"
]
)
start &113
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 8756,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8757,0
va (VaSet
)
xt "125000,80000,130200,81000"
st "sclk_enable"
blo "125000,80800"
tm "WireNameMgr"
)
)
on &294
)
*1000 (Wire
uid 9006,0
shape (OrthoPolyLine
uid 9007,0
va (VaSet
vasetType 3
)
xt "-36000,95000,-24750,95000"
pts [
"-24750,95000"
"-36000,95000"
]
)
start &43
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9011,0
va (VaSet
)
xt "-35000,94000,-29900,95000"
st "adc_clk_en"
blo "-35000,94800"
tm "WireNameMgr"
)
)
on &295
)
*1001 (Wire
uid 9233,0
shape (OrthoPolyLine
uid 9234,0
va (VaSet
vasetType 3
)
xt "124750,83000,134000,83000"
pts [
"124750,83000"
"134000,83000"
]
)
start &114
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9237,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9238,0
va (VaSet
)
xt "125000,82000,130500,83000"
st "ps_direction"
blo "125000,82800"
tm "WireNameMgr"
)
)
on &310
)
*1002 (Wire
uid 9241,0
shape (OrthoPolyLine
uid 9242,0
va (VaSet
vasetType 3
)
xt "124750,84000,134000,84000"
pts [
"124750,84000"
"134000,84000"
]
)
start &115
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9245,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9246,0
va (VaSet
)
xt "125000,83000,133100,84000"
st "ps_do_phase_shift"
blo "125000,83800"
tm "WireNameMgr"
)
)
on &311
)
*1003 (Wire
uid 9253,0
shape (OrthoPolyLine
uid 9254,0
va (VaSet
vasetType 3
)
xt "-66000,15000,-60750,15000"
pts [
"-66000,15000"
"-60750,15000"
]
)
end &301
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 9257,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9258,0
va (VaSet
)
xt "-71000,14000,-65500,15000"
st "ps_direction"
blo "-71000,14800"
tm "WireNameMgr"
)
)
on &310
)
*1004 (Wire
uid 9261,0
shape (OrthoPolyLine
uid 9262,0
va (VaSet
vasetType 3
)
xt "-66000,16000,-60750,16000"
pts [
"-66000,16000"
"-60750,16000"
]
)
end &302
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 9265,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9266,0
va (VaSet
)
xt "-74000,15000,-65900,16000"
st "ps_do_phase_shift"
blo "-74000,15800"
tm "WireNameMgr"
)
)
on &311
)
*1005 (Wire
uid 9943,0
shape (OrthoPolyLine
uid 9944,0
va (VaSet
vasetType 3
)
xt "124750,85000,134000,85000"
pts [
"124750,85000"
"134000,85000"
]
)
start &116
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9947,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9948,0
va (VaSet
)
xt "125000,84000,128700,85000"
st "ps_reset"
blo "125000,84800"
tm "WireNameMgr"
)
)
on &312
)
*1006 (Wire
uid 9951,0
shape (OrthoPolyLine
uid 9952,0
va (VaSet
vasetType 3
)
xt "124750,88000,134000,88000"
pts [
"124750,88000"
"134000,88000"
]
)
start &117
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 9955,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9956,0
va (VaSet
)
xt "125000,87000,130600,88000"
st "srclk_enable"
blo "125000,87800"
tm "WireNameMgr"
)
)
on &313
)
*1007 (Wire
uid 10010,0
shape (OrthoPolyLine
uid 10011,0
va (VaSet
vasetType 3
)
xt "-66000,55000,-58750,56000"
pts [
"-58750,55000"
"-64000,55000"
"-64000,56000"
"-66000,56000"
]
)
start &220
end &318
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10014,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10015,0
va (VaSet
)
xt "-62750,54000,-59450,55000"
st "SRCLK1"
blo "-62750,54800"
tm "WireNameMgr"
)
)
on &332
)
*1008 (Wire
uid 10018,0
shape (OrthoPolyLine
uid 10019,0
va (VaSet
vasetType 3
)
xt "-66000,58000,-63000,58000"
pts [
"-63000,58000"
"-66000,58000"
]
)
end &320
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10022,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10023,0
va (VaSet
)
xt "-65000,58000,-59400,59000"
st "srclk_enable"
blo "-65000,58800"
tm "WireNameMgr"
)
)
on &313
)
*1009 (Wire
uid 10036,0
shape (OrthoPolyLine
uid 10037,0
va (VaSet
vasetType 3
)
xt "-66000,24000,-60750,24000"
pts [
"-66000,24000"
"-60750,24000"
]
)
end &303
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 10040,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10041,0
va (VaSet
)
xt "-65000,23000,-61300,24000"
st "ps_reset"
blo "-65000,23800"
tm "WireNameMgr"
)
)
on &312
)
*1010 (Wire
uid 10266,0
shape (OrthoPolyLine
uid 10267,0
va (VaSet
vasetType 3
)
xt "81000,66000,87250,66000"
pts [
"87250,66000"
"81000,66000"
]
)
start &109
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 10270,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10271,0
va (VaSet
)
xt "82000,65000,85900,66000"
st "s_trigger"
blo "82000,65800"
tm "WireNameMgr"
)
)
on &333
)
*1011 (Wire
uid 10298,0
shape (OrthoPolyLine
uid 10299,0
va (VaSet
vasetType 3
)
xt "-38250,57000,-24750,60000"
pts [
"-38250,57000"
"-36000,57000"
"-36000,60000"
"-24750,60000"
]
)
start &225
end &45
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10300,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10301,0
va (VaSet
)
xt "-36250,56000,-27450,57000"
st "start_srin_write_8b"
blo "-36250,56800"
tm "WireNameMgr"
)
)
on &334
)
*1012 (Wire
uid 10304,0
shape (OrthoPolyLine
uid 10305,0
va (VaSet
vasetType 3
)
xt "-38250,58000,-24750,61000"
pts [
"-38250,58000"
"-37000,58000"
"-37000,61000"
"-24750,61000"
]
)
start &223
end &46
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10306,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10307,0
va (VaSet
)
xt "-36250,57000,-29650,58000"
st "srin_write_ack"
blo "-36250,57800"
tm "WireNameMgr"
)
)
on &335
)
*1013 (Wire
uid 10310,0
shape (OrthoPolyLine
uid 10311,0
va (VaSet
vasetType 3
)
xt "-38250,59000,-24750,62000"
pts [
"-38250,59000"
"-38000,59000"
"-38000,62000"
"-24750,62000"
]
)
start &224
end &47
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10312,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10313,0
va (VaSet
)
xt "-36250,58000,-28850,59000"
st "srin_write_ready"
blo "-36250,58800"
tm "WireNameMgr"
)
)
on &336
)
*1014 (Wire
uid 10316,0
shape (OrthoPolyLine
uid 10317,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-38250,60000,-24750,63000"
pts [
"-24750,63000"
"-28000,63000"
"-28000,60000"
"-38250,60000"
]
)
start &44
end &221
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 10318,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10319,0
va (VaSet
)
xt "-36000,59000,-26800,60000"
st "drs_srin_data : (7:0)"
blo "-36000,59800"
tm "WireNameMgr"
)
)
on &337
)
*1015 (Wire
uid 10322,0
shape (OrthoPolyLine
uid 10323,0
va (VaSet
vasetType 3
)
xt "-74000,60000,-58750,60000"
pts [
"-58750,60000"
"-74000,60000"
]
)
start &222
end &339
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10327,0
va (VaSet
isHidden 1
)
xt "-64000,59000,-59800,60000"
st "SRIN_out"
blo "-64000,59800"
tm "WireNameMgr"
)
)
on &338
)
*1016 (Wire
uid 10629,0
shape (OrthoPolyLine
uid 10630,0
va (VaSet
vasetType 3
)
xt "124750,91000,133000,91000"
pts [
"124750,91000"
"133000,91000"
]
)
start &118
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 10633,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10634,0
va (VaSet
)
xt "125000,90000,132200,91000"
st "socks_connected"
blo "125000,90800"
tm "WireNameMgr"
)
)
on &363
)
*1017 (Wire
uid 10637,0
shape (OrthoPolyLine
uid 10638,0
va (VaSet
vasetType 3
)
xt "124750,92000,133000,92000"
pts [
"124750,92000"
"133000,92000"
]
)
start &119
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 10641,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10642,0
va (VaSet
)
xt "125000,91000,131100,92000"
st "socks_waiting"
blo "125000,91800"
tm "WireNameMgr"
)
)
on &364
)
*1018 (Wire
uid 10685,0
shape (OrthoPolyLine
uid 10686,0
va (VaSet
vasetType 3
)
xt "78000,131000,88250,131000"
pts [
"78000,131000"
"88250,131000"
]
)
end &377
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10689,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10690,0
va (VaSet
)
xt "79000,130000,85100,131000"
st "socks_waiting"
blo "79000,130800"
tm "WireNameMgr"
)
)
on &364
)
*1019 (Wire
uid 10691,0
shape (OrthoPolyLine
uid 10692,0
va (VaSet
vasetType 3
)
xt "78000,132000,88250,132000"
pts [
"78000,132000"
"88250,132000"
]
)
end &378
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10695,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10696,0
va (VaSet
)
xt "79000,131000,86200,132000"
st "socks_connected"
blo "79000,131800"
tm "WireNameMgr"
)
)
on &363
)
*1020 (Wire
uid 10699,0
shape (OrthoPolyLine
uid 10700,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "78000,129000,88250,129000"
pts [
"78000,129000"
"88250,129000"
]
)
end &372
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10703,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10704,0
va (VaSet
)
xt "80000,128000,83300,129000"
st "CLK_50"
blo "80000,128800"
tm "WireNameMgr"
)
)
on &186
)
*1021 (Wire
uid 10707,0
shape (OrthoPolyLine
uid 10708,0
va (VaSet
vasetType 3
)
xt "78000,130000,88250,130000"
pts [
"78000,130000"
"88250,130000"
]
)
end &376
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 10711,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10712,0
va (VaSet
)
xt "80000,129000,89000,130000"
st "drs_readout_started"
blo "80000,129800"
tm "WireNameMgr"
)
)
on &387
)
*1022 (Wire
uid 10723,0
shape (OrthoPolyLine
uid 10724,0
va (VaSet
vasetType 3
)
xt "107750,129000,113000,129000"
pts [
"107750,129000"
"113000,129000"
]
)
start &373
end &366
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10727,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10728,0
va (VaSet
isHidden 1
)
xt "109000,128000,111400,129000"
st "green"
blo "109000,128800"
tm "WireNameMgr"
)
)
on &365
)
*1023 (Wire
uid 10737,0
shape (OrthoPolyLine
uid 10738,0
va (VaSet
vasetType 3
)
xt "107750,130000,113000,130000"
pts [
"107750,130000"
"113000,130000"
]
)
start &374
end &368
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10741,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10742,0
va (VaSet
isHidden 1
)
xt "109000,129000,111700,130000"
st "amber"
blo "109000,129800"
tm "WireNameMgr"
)
)
on &367
)
*1024 (Wire
uid 10751,0
shape (OrthoPolyLine
uid 10752,0
va (VaSet
vasetType 3
)
xt "107750,131000,113000,131000"
pts [
"107750,131000"
"113000,131000"
]
)
start &375
end &370
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10755,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10756,0
va (VaSet
isHidden 1
)
xt "109000,130000,110700,131000"
st "red"
blo "109000,130800"
tm "WireNameMgr"
)
)
on &369
)
*1025 (Wire
uid 11405,0
shape (OrthoPolyLine
uid 11406,0
va (VaSet
vasetType 3
)
xt "3750,104000,13000,104000"
pts [
"3750,104000"
"13000,104000"
]
)
start &48
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 11409,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11410,0
va (VaSet
isHidden 1
)
xt "20000,110000,29000,111000"
st "drs_readout_started"
blo "20000,110800"
tm "WireNameMgr"
)
)
on &387
)
*1026 (Wire
uid 11858,0
shape (OrthoPolyLine
uid 11859,0
va (VaSet
vasetType 3
)
xt "124750,93000,133000,93000"
pts [
"124750,93000"
"133000,93000"
]
)
start &120
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 11862,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11863,0
va (VaSet
)
xt "125000,92000,131300,93000"
st "trigger_enable"
blo "125000,92800"
tm "WireNameMgr"
)
)
on &388
)
*1027 (Wire
uid 11952,0
shape (OrthoPolyLine
uid 11953,0
va (VaSet
vasetType 3
)
xt "-131000,71000,-119000,71000"
pts [
"-131000,71000"
"-119000,71000"
]
)
end &395
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11956,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11957,0
va (VaSet
)
xt "-131000,70000,-124700,71000"
st "trigger_enable"
blo "-131000,70800"
tm "WireNameMgr"
)
)
on &388
)
*1028 (Wire
uid 12306,0
shape (OrthoPolyLine
uid 12307,0
va (VaSet
vasetType 3
)
xt "-119000,67000,-119000,69000"
pts [
"-119000,67000"
"-119000,69000"
]
)
start &343
end &393
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12308,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12309,0
va (VaSet
)
xt "-124000,64000,-114700,65000"
st "trigger_or_s_trigger"
blo "-124000,64800"
tm "WireNameMgr"
)
)
on &546
)
*1029 (Wire
uid 12643,0
shape (OrthoPolyLine
uid 12644,0
va (VaSet
vasetType 3
)
xt "-97000,70000,-72750,74000"
pts [
"-97000,70000"
"-84000,70000"
"-84000,74000"
"-72750,74000"
]
)
start &785
end &408
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12645,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12646,0
va (VaSet
)
xt "-84000,73000,-71400,74000"
st "enabled_trigger_or_s_trigger"
blo "-84000,73800"
tm "WireNameMgr"
)
)
on &547
)
*1030 (Wire
uid 12649,0
shape (OrthoPolyLine
uid 12650,0
va (VaSet
vasetType 3
)
xt "-55250,74000,-24750,77000"
pts [
"-24750,77000"
"-29000,77000"
"-29000,74000"
"-55250,74000"
]
)
start &49
end &411
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 12651,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12652,0
va (VaSet
)
xt "-35000,76000,-26800,77000"
st "drs_readout_ready"
blo "-35000,76800"
tm "WireNameMgr"
)
)
on &417
)
*1031 (Wire
uid 12655,0
shape (OrthoPolyLine
uid 12656,0
va (VaSet
vasetType 3
)
xt "-55250,75000,-24750,81000"
pts [
"-24750,78000"
"-28000,78000"
"-28000,81000"
"-52000,81000"
"-52000,75000"
"-55250,75000"
]
)
start &50
end &412
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 12657,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12658,0
va (VaSet
)
xt "-34750,77000,-24250,78000"
st "drs_readout_ready_ack"
blo "-34750,77800"
tm "WireNameMgr"
)
)
on &418
)
*1032 (Wire
uid 12687,0
shape (OrthoPolyLine
uid 12688,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-77000,67000,-72750,72000"
pts [
"-77000,67000"
"-74000,67000"
"-74000,72000"
"-72750,72000"
]
)
end &413
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 12691,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12692,0
va (VaSet
)
xt "-76000,66000,-72700,67000"
st "CLK_25"
blo "-76000,66800"
tm "WireNameMgr"
)
)
on &187
)
*1033 (Wire
uid 13143,0
shape (OrthoPolyLine
uid 13144,0
va (VaSet
vasetType 3
)
xt "72750,62000,78000,62000"
pts [
"78000,62000"
"72750,62000"
]
)
end &420
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 13147,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13148,0
va (VaSet
)
xt "74000,61000,77300,62000"
st "CLK_25"
blo "74000,61800"
tm "WireNameMgr"
)
)
on &187
)
*1034 (Wire
uid 13159,0
shape (OrthoPolyLine
uid 13160,0
va (VaSet
vasetType 3
)
xt "72750,63000,87250,67000"
pts [
"87250,67000"
"77000,67000"
"77000,63000"
"72750,63000"
]
)
start &121
end &421
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 13161,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13162,0
va (VaSet
)
xt "79250,66000,86450,67000"
st "c_trigger_enable"
blo "79250,66800"
tm "WireNameMgr"
)
)
on &427
)
*1035 (Wire
uid 13210,0
shape (OrthoPolyLine
uid 13211,0
va (VaSet
vasetType 3
)
xt "9000,63000,20000,63000"
pts [
"20000,63000"
"9000,63000"
]
)
start &868
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 13212,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13213,0
va (VaSet
)
xt "8250,62000,13850,63000"
st "cont_trigger"
blo "8250,62800"
tm "WireNameMgr"
)
)
on &548
)
*1036 (Wire
uid 13216,0
shape (OrthoPolyLine
uid 13217,0
va (VaSet
vasetType 3
)
xt "-109000,68000,-103000,69000"
pts [
"-103000,69000"
"-109000,68000"
]
)
start &788
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13220,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13221,0
va (VaSet
)
xt "-109000,67000,-105100,68000"
st "s_trigger"
blo "-109000,67800"
tm "WireNameMgr"
)
)
on &333
)
*1037 (Wire
uid 13695,0
shape (OrthoPolyLine
uid 13696,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80000,95000,87250,95000"
pts [
"80000,95000"
"87250,95000"
]
)
start &428
end &123
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 13699,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13700,0
va (VaSet
isHidden 1
)
xt "82000,94000,87500,95000"
st "D_T_in : (1:0)"
blo "82000,94800"
tm "WireNameMgr"
)
)
on &429
)
*1038 (Wire
uid 13921,0
shape (OrthoPolyLine
uid 13922,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "79000,96000,87250,96000"
pts [
"79000,96000"
"87250,96000"
]
)
end &124
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 13925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13926,0
va (VaSet
)
xt "80000,95000,86700,96000"
st "board_id : (3:0)"
blo "80000,95800"
tm "WireNameMgr"
)
)
on &87
)
*1039 (Wire
uid 13929,0
shape (OrthoPolyLine
uid 13930,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "79000,97000,87250,97000"
pts [
"79000,97000"
"87250,97000"
]
)
end &125
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 13933,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13934,0
va (VaSet
)
xt "80000,96000,86400,97000"
st "crate_id : (1:0)"
blo "80000,96800"
tm "WireNameMgr"
)
)
on &148
)
*1040 (Wire
uid 14048,0
shape (OrthoPolyLine
uid 14049,0
va (VaSet
vasetType 3
)
xt "-72000,135000,-69750,135000"
pts [
"-72000,135000"
"-69750,135000"
]
)
start &430
end &436
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 14052,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14053,0
va (VaSet
isHidden 1
)
xt "-78000,134000,-71900,135000"
st "drs_refclk_in"
blo "-78000,134800"
tm "WireNameMgr"
)
)
on &431
)
*1041 (Wire
uid 14171,0
shape (OrthoPolyLine
uid 14172,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-90000,123000,-87000,123000"
pts [
"-90000,123000"
"-87000,123000"
]
)
start &432
end &556
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 14175,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14176,0
va (VaSet
isHidden 1
)
xt "-87000,127000,-80300,128000"
st "plllock_in : (3:0)"
blo "-87000,127800"
tm "WireNameMgr"
)
)
on &433
)
*1042 (Wire
uid 14427,0
shape (OrthoPolyLine
uid 14428,0
va (VaSet
vasetType 3
)
xt "-74000,134000,-69750,134000"
pts [
"-74000,134000"
"-69750,134000"
]
)
end &435
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 14431,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14432,0
va (VaSet
)
xt "-73000,133000,-69700,134000"
st "CLK_50"
blo "-73000,133800"
tm "WireNameMgr"
)
)
on &186
)
*1043 (Wire
uid 14479,0
shape (OrthoPolyLine
uid 14480,0
va (VaSet
vasetType 3
)
xt "-53250,135000,-51000,135000"
pts [
"-53250,135000"
"-51000,135000"
]
)
start &438
end &444
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 14483,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14484,0
va (VaSet
isHidden 1
)
xt "-52000,134000,-42000,135000"
st "alarm_refclk_too_high"
blo "-52000,134800"
tm "WireNameMgr"
)
)
on &443
)
*1044 (Wire
uid 14493,0
shape (OrthoPolyLine
uid 14494,0
va (VaSet
vasetType 3
)
xt "-53250,136000,-51000,136000"
pts [
"-53250,136000"
"-51000,136000"
]
)
start &439
end &446
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 14497,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14498,0
va (VaSet
isHidden 1
)
xt "-52000,135000,-42400,136000"
st "alarm_refclk_too_low"
blo "-52000,135800"
tm "WireNameMgr"
)
)
on &445
)
*1045 (Wire
uid 14622,0
shape (OrthoPolyLine
uid 14623,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-53250,134000,-42000,134000"
pts [
"-53250,134000"
"-42000,134000"
]
)
start &437
end &448
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 14626,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14627,0
va (VaSet
isHidden 1
)
xt "-52000,133000,-45600,134000"
st "counter_result"
blo "-52000,133800"
tm "WireNameMgr"
)
)
on &447
)
*1046 (Wire
uid 15071,0
shape (OrthoPolyLine
uid 15072,0
va (VaSet
vasetType 3
)
xt "124750,77000,160000,77000"
pts [
"124750,77000"
"160000,77000"
]
)
start &110
end &453
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15075,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15076,0
va (VaSet
)
xt "156000,76000,161800,77000"
st "denable_prim"
blo "156000,76800"
tm "WireNameMgr"
)
)
on &477
)
*1047 (Wire
uid 15081,0
shape (OrthoPolyLine
uid 15082,0
va (VaSet
vasetType 3
)
xt "158000,79000,160000,79000"
pts [
"160000,79000"
"158000,79000"
]
)
start &455
end &470
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15083,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15084,0
va (VaSet
isHidden 1
)
xt "159000,78000,160900,79000"
st "din1"
blo "159000,78800"
tm "WireNameMgr"
)
)
on &478
)
*1048 (Wire
uid 15130,0
shape (OrthoPolyLine
uid 15131,0
va (VaSet
vasetType 3
)
xt "143000,79000,153000,79000"
pts [
"143000,79000"
"153000,79000"
]
)
end &468
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15134,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15135,0
va (VaSet
)
xt "144000,78000,153600,79000"
st "alarm_refclk_too_low"
blo "144000,78800"
tm "WireNameMgr"
)
)
on &445
)
*1049 (Wire
uid 15379,0
shape (OrthoPolyLine
uid 15380,0
va (VaSet
vasetType 3
)
xt "29000,64000,29000,67250"
pts [
"29000,64000"
"29000,67250"
]
)
end &719
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15383,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15384,0
va (VaSet
)
xt "29000,64000,32300,65000"
st "CLK_25"
blo "29000,64800"
tm "WireNameMgr"
)
)
on &187
)
*1050 (Wire
uid 15494,0
optionalChildren [
*1051 (BdJunction
uid 15502,0
ps "OnConnectorStrategy"
shape (Circle
uid 15503,0
va (VaSet
vasetType 1
)
xt "-54390,71600,-53590,72400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 15495,0
va (VaSet
vasetType 3
)
xt "-55250,72000,-24750,75000"
pts [
"-55250,72000"
"-41000,72000"
"-41000,75000"
"-24750,75000"
]
)
start &409
end &75
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 15496,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15497,0
va (VaSet
)
xt "-53250,71000,-48050,72000"
st "trigger_out"
blo "-53250,71800"
tm "WireNameMgr"
)
)
on &479
)
*1052 (Wire
uid 15498,0
shape (OrthoPolyLine
uid 15499,0
va (VaSet
vasetType 3
)
xt "-53990,65000,-52750,72000"
pts [
"-52750,65000"
"-53990,65000"
"-53990,72000"
]
)
start &151
end &1051
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 15500,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15501,0
va (VaSet
isHidden 1
)
xt "-58000,65000,-52800,66000"
st "trigger_out"
blo "-58000,65800"
tm "WireNameMgr"
)
)
on &479
)
*1053 (Wire
uid 15750,0
shape (OrthoPolyLine
uid 15751,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-40250,65000,-24750,73000"
pts [
"-40250,65000"
"-39000,65000"
"-39000,73000"
"-24750,73000"
]
)
start &150
end &51
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 15752,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 15753,0
va (VaSet
)
xt "-38250,64000,-30750,65000"
st "trigger_id : (31:0)"
blo "-38250,64800"
tm "WireNameMgr"
)
)
on &480
)
*1054 (Wire
uid 16371,0
shape (OrthoPolyLine
uid 16372,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-36000,100000,-24750,100000"
pts [
"-36000,100000"
"-24750,100000"
]
)
end &53
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16375,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16376,0
va (VaSet
)
xt "-35000,99000,-25000,100000"
st "DCM_PS_status : (7:0)"
blo "-35000,99800"
tm "WireNameMgr"
)
)
on &481
)
*1055 (Wire
uid 16379,0
shape (OrthoPolyLine
uid 16380,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-41250,15000,-32000,15000"
pts [
"-41250,15000"
"-32000,15000"
]
)
start &304
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16383,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16384,0
va (VaSet
)
xt "-40000,14000,-30000,15000"
st "DCM_PS_status : (7:0)"
blo "-40000,14800"
tm "WireNameMgr"
)
)
on &481
)
*1056 (Wire
uid 16523,0
shape (OrthoPolyLine
uid 16524,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-36000,106000,-24750,106000"
pts [
"-36000,106000"
"-24750,106000"
]
)
end &57
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16527,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16528,0
va (VaSet
)
xt "-35000,105000,-25400,106000"
st "counter_result : (11:0)"
blo "-35000,105800"
tm "WireNameMgr"
)
)
on &447
)
*1057 (Wire
uid 16531,0
shape (OrthoPolyLine
uid 16532,0
va (VaSet
vasetType 3
)
xt "-36000,107000,-24750,107000"
pts [
"-36000,107000"
"-24750,107000"
]
)
end &58
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 16535,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16536,0
va (VaSet
)
xt "-35000,106000,-25000,107000"
st "alarm_refclk_too_high"
blo "-35000,106800"
tm "WireNameMgr"
)
)
on &443
)
*1058 (Wire
uid 16539,0
shape (OrthoPolyLine
uid 16540,0
va (VaSet
vasetType 3
)
xt "-36000,108000,-24750,108000"
pts [
"-36000,108000"
"-24750,108000"
]
)
end &59
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 16543,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16544,0
va (VaSet
)
xt "-35000,107000,-25400,108000"
st "alarm_refclk_too_low"
blo "-35000,107800"
tm "WireNameMgr"
)
)
on &445
)
*1059 (Wire
uid 16547,0
shape (OrthoPolyLine
uid 16548,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-56250,98000,-24750,101000"
pts [
"-56250,98000"
"-28000,98000"
"-28000,101000"
"-24750,101000"
]
)
start &484
end &54
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16551,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16552,0
va (VaSet
)
xt "-55000,97000,-49900,98000"
st "dna : (63:0)"
blo "-55000,97800"
tm "WireNameMgr"
)
)
on &489
)
*1060 (Wire
uid 16556,0
shape (OrthoPolyLine
uid 16557,0
va (VaSet
vasetType 3
)
xt "-72000,98000,-67750,98000"
pts [
"-72000,98000"
"-67750,98000"
]
)
end &483
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 16560,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16561,0
va (VaSet
)
xt "-71000,97000,-67700,98000"
st "CLK_25"
blo "-71000,97800"
tm "WireNameMgr"
)
)
on &187
)
*1061 (Wire
uid 16564,0
shape (OrthoPolyLine
uid 16565,0
va (VaSet
vasetType 3
)
xt "-56250,100000,-52000,100000"
pts [
"-56250,100000"
"-52000,100000"
]
)
start &485
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 16568,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16569,0
va (VaSet
)
xt "-55000,99000,-52500,100000"
st "ready"
blo "-55000,99800"
tm "WireNameMgr"
)
)
on &490
)
*1062 (Wire
uid 16877,0
shape (OrthoPolyLine
uid 16878,0
va (VaSet
vasetType 3
)
xt "-77000,145000,-69750,145000"
pts [
"-77000,145000"
"-69750,145000"
]
)
end &492
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 16881,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16882,0
va (VaSet
)
xt "-73000,144000,-69700,145000"
st "CLK_50"
blo "-73000,144800"
tm "WireNameMgr"
)
)
on &186
)
*1063 (Wire
uid 16885,0
shape (OrthoPolyLine
uid 16886,0
va (VaSet
vasetType 3
)
xt "-77000,146000,-69750,146000"
pts [
"-77000,146000"
"-69750,146000"
]
)
end &494
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 16889,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16890,0
va (VaSet
)
xt "-74000,145000,-68800,146000"
st "trigger_out"
blo "-74000,145800"
tm "WireNameMgr"
)
)
on &479
)
*1064 (Wire
uid 16914,0
shape (OrthoPolyLine
uid 16915,0
va (VaSet
vasetType 3
)
xt "-84000,147000,-69750,147000"
pts [
"-69750,147000"
"-84000,147000"
]
)
start &497
end &502
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 16916,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16917,0
va (VaSet
)
xt "-83000,146000,-79600,147000"
st "enable_i"
blo "-83000,146800"
tm "WireNameMgr"
)
)
on &510
)
*1065 (Wire
uid 16939,0
shape (OrthoPolyLine
uid 16940,0
va (VaSet
vasetType 3
)
xt "-79000,148000,-69750,148000"
pts [
"-69750,148000"
"-79000,148000"
]
)
start &496
end &512
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 16941,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16942,0
va (VaSet
)
xt "-75750,147000,-69550,148000"
st "reset_synch_i"
blo "-75750,147800"
tm "WireNameMgr"
)
)
on &519
)
*1066 (Wire
uid 16945,0
shape (OrthoPolyLine
uid 16946,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-48250,145000,-40000,145000"
pts [
"-48250,145000"
"-40000,145000"
]
)
start &493
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16949,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16950,0
va (VaSet
)
xt "-47000,144000,-41700,145000"
st "time : (31:0)"
blo "-47000,144800"
tm "WireNameMgr"
)
)
on &520
)
*1067 (Wire
uid 16955,0
shape (OrthoPolyLine
uid 16956,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-37000,109000,-24750,109000"
pts [
"-37000,109000"
"-24750,109000"
]
)
end &60
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 16959,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16960,0
va (VaSet
)
xt "-36000,108000,-30700,109000"
st "time : (31:0)"
blo "-36000,108800"
tm "WireNameMgr"
)
)
on &520
)
*1068 (Wire
uid 17003,0
shape (OrthoPolyLine
uid 17004,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-250,151000,11000,151000"
pts [
"-250,151000"
"11000,151000"
]
)
start &681
ss 0
sat 32
eat 16
sty 1
st 0
sf 1
si 0
tg (WTG
uid 17007,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17008,0
va (VaSet
)
xt "3000,150000,11300,151000"
st "rs465_data : (55:0)"
blo "3000,150800"
tm "WireNameMgr"
)
)
on &521
)
*1069 (Wire
uid 17011,0
shape (OrthoPolyLine
uid 17012,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-36000,103000,-24750,103000"
pts [
"-36000,103000"
"-24750,103000"
]
)
end &56
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 17015,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17016,0
va (VaSet
)
xt "-35000,102000,-26700,103000"
st "rs465_data : (55:0)"
blo "-35000,102800"
tm "WireNameMgr"
)
)
on &521
)
*1070 (Wire
uid 17019,0
shape (OrthoPolyLine
uid 17020,0
va (VaSet
vasetType 3
)
xt "-250,152000,12000,152000"
pts [
"-250,152000"
"12000,152000"
]
)
start &682
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 17023,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17024,0
va (VaSet
)
xt "4000,151000,12300,152000"
st "FTM_RS485_ready"
blo "4000,151800"
tm "WireNameMgr"
)
)
on &522
)
*1071 (Wire
uid 17027,0
shape (OrthoPolyLine
uid 17028,0
va (VaSet
vasetType 3
)
xt "-36000,102000,-24750,102000"
pts [
"-36000,102000"
"-24750,102000"
]
)
end &55
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 17031,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17032,0
va (VaSet
)
xt "-35000,101000,-26700,102000"
st "FTM_RS485_ready"
blo "-35000,101800"
tm "WireNameMgr"
)
)
on &522
)
*1072 (Wire
uid 17393,0
shape (OrthoPolyLine
uid 17394,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "72750,64000,87250,68000"
pts [
"87250,68000"
"76000,68000"
"76000,64000"
"72750,64000"
]
)
start &122
end &422
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 17395,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17396,0
va (VaSet
)
xt "77250,67000,87050,68000"
st "c_trigger_mult : (15:0)"
blo "77250,67800"
tm "WireNameMgr"
)
)
on &523
)
*1073 (Wire
uid 17401,0
shape (OrthoPolyLine
uid 17402,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-35000,110000,-24750,110000"
pts [
"-35000,110000"
"-24750,110000"
]
)
end &61
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 17405,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17406,0
va (VaSet
)
xt "-34000,109000,-24200,110000"
st "c_trigger_mult : (15:0)"
blo "-34000,109800"
tm "WireNameMgr"
)
)
on &523
)
*1074 (Wire
uid 18081,0
shape (OrthoPolyLine
uid 18082,0
va (VaSet
vasetType 3
)
xt "-63000,48000,-58750,48000"
pts [
"-63000,48000"
"-58750,48000"
]
)
end &210
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 18085,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18086,0
va (VaSet
)
xt "-62000,47000,-58700,48000"
st "CLK_25"
blo "-62000,47800"
tm "WireNameMgr"
)
)
on &187
)
*1075 (Wire
uid 18093,0
shape (OrthoPolyLine
uid 18094,0
va (VaSet
vasetType 3
)
xt "51750,47000,56000,47000"
pts [
"56000,47000"
"51750,47000"
]
)
end &926
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 18097,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18098,0
va (VaSet
)
xt "53000,46000,56300,47000"
st "CLK_50"
blo "53000,46800"
tm "WireNameMgr"
)
)
on &186
)
*1076 (Wire
uid 18101,0
shape (OrthoPolyLine
uid 18102,0
va (VaSet
vasetType 3
)
xt "32000,47000,36250,47000"
pts [
"32000,47000"
"36250,47000"
]
)
end &922
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 18105,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18106,0
va (VaSet
)
xt "33000,46000,36300,47000"
st "CLK_25"
blo "33000,46800"
tm "WireNameMgr"
)
)
on &187
)
*1077 (Wire
uid 18459,0
shape (OrthoPolyLine
uid 18460,0
va (VaSet
vasetType 3
)
xt "59750,83000,87250,83000"
pts [
"59750,83000"
"87250,83000"
]
)
start &734
end &132
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 18461,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18462,0
va (VaSet
)
xt "70000,82000,77200,83000"
st "data_ram_empty"
blo "70000,82800"
tm "WireNameMgr"
)
)
on &524
)
*1078 (Wire
uid 18974,0
shape (OrthoPolyLine
uid 18975,0
va (VaSet
vasetType 3
)
xt "-53000,36000,-51000,36000"
pts [
"-51000,36000"
"-53000,36000"
]
)
start &528
end &525
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 18978,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18979,0
va (VaSet
isHidden 1
)
xt "-70000,44000,-66000,45000"
st "ADC_CLK"
blo "-70000,44800"
tm "WireNameMgr"
)
)
on &526
)
*1079 (Wire
uid 19231,0
shape (OrthoPolyLine
uid 19232,0
va (VaSet
vasetType 3
)
xt "-45000,24000,-39000,35000"
pts [
"-45000,35000"
"-39000,35000"
"-39000,24000"
]
)
start &533
end &962
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19233,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19234,0
va (VaSet
)
xt "-43000,34000,-38200,35000"
st "CLK_25_PS"
blo "-43000,34800"
tm "WireNameMgr"
)
)
on &184
)
*1080 (Wire
uid 19276,0
shape (OrthoPolyLine
uid 19277,0
va (VaSet
vasetType 3
)
xt "-45000,37000,-41000,37000"
pts [
"-41000,37000"
"-45000,37000"
]
)
end &531
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19280,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19281,0
va (VaSet
)
xt "-46000,36000,-40900,37000"
st "adc_clk_en"
blo "-46000,36800"
tm "WireNameMgr"
)
)
on &295
)
*1081 (Wire
uid 20153,0
shape (OrthoPolyLine
uid 20154,0
va (VaSet
vasetType 3
)
xt "-2250,130000,6000,130000"
pts [
"-2250,130000"
"6000,130000"
]
)
start &259
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 20157,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20158,0
va (VaSet
)
xt "-1000,129000,7000,130000"
st "current_dac_array"
blo "-1000,129800"
tm "WireNameMgr"
)
)
on &545
)
*1082 (Wire
uid 20923,0
shape (OrthoPolyLine
uid 20924,0
va (VaSet
vasetType 3
)
xt "80000,119000,87250,119000"
pts [
"87250,119000"
"80000,119000"
]
)
start &126
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 20927,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20928,0
va (VaSet
)
xt "81000,118000,86300,119000"
st "dac_setting"
blo "81000,118800"
tm "WireNameMgr"
)
)
on &549
)
*1083 (Wire
uid 20931,0
shape (OrthoPolyLine
uid 20932,0
va (VaSet
vasetType 3
)
xt "-2250,129000,6000,129000"
pts [
"6000,129000"
"-2250,129000"
]
)
end &249
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 20935,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20936,0
va (VaSet
)
xt "1000,128000,6300,129000"
st "dac_setting"
blo "1000,128800"
tm "WireNameMgr"
)
)
on &549
)
*1084 (Wire
uid 20939,0
shape (OrthoPolyLine
uid 20940,0
va (VaSet
vasetType 3
)
xt "80000,120000,87250,120000"
pts [
"87250,120000"
"80000,120000"
]
)
start &129
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 20943,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20944,0
va (VaSet
)
xt "81000,119000,86000,120000"
st "roi_setting"
blo "81000,119800"
tm "WireNameMgr"
)
)
on &550
)
*1085 (Wire
uid 20945,0
shape (OrthoPolyLine
uid 20946,0
va (VaSet
vasetType 3
)
xt "22000,86000,27250,86000"
pts [
"22000,86000"
"27250,86000"
]
)
end &722
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 20949,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20950,0
va (VaSet
)
xt "23000,85000,28000,86000"
st "roi_setting"
blo "23000,85800"
tm "WireNameMgr"
)
)
on &550
)
*1086 (Wire
uid 20953,0
shape (OrthoPolyLine
uid 20954,0
va (VaSet
vasetType 3
)
xt "3750,101000,13000,101000"
pts [
"13000,101000"
"3750,101000"
]
)
end &32
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 20957,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20958,0
va (VaSet
)
xt "7000,100000,12000,101000"
st "roi_setting"
blo "7000,100800"
tm "WireNameMgr"
)
)
on &550
)
*1087 (Wire
uid 20987,0
shape (OrthoPolyLine
uid 20988,0
va (VaSet
vasetType 3
)
xt "73000,107000,87250,107000"
pts [
"87250,107000"
"73000,107000"
]
)
start &127
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 20991,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20992,0
va (VaSet
)
xt "74000,106000,86900,107000"
st "memory_manager_config_start"
blo "74000,106800"
tm "WireNameMgr"
)
)
on &551
)
*1088 (Wire
uid 21003,0
shape (OrthoPolyLine
uid 21004,0
va (VaSet
vasetType 3
)
xt "73000,108000,87250,108000"
pts [
"73000,108000"
"87250,108000"
]
)
end &128
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 21007,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21008,0
va (VaSet
)
xt "74000,107000,86600,108000"
st "memory_manager_config_valid"
blo "74000,107800"
tm "WireNameMgr"
)
)
on &552
)
*1089 (Wire
uid 21011,0
shape (OrthoPolyLine
uid 21012,0
va (VaSet
vasetType 3
)
xt "74000,111000,87250,111000"
pts [
"87250,111000"
"74000,111000"
]
)
start &130
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 21015,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21016,0
va (VaSet
)
xt "75000,110000,86500,111000"
st "spi_interface_config_start"
blo "75000,110800"
tm "WireNameMgr"
)
)
on &553
)
*1090 (Wire
uid 21027,0
shape (OrthoPolyLine
uid 21028,0
va (VaSet
vasetType 3
)
xt "74000,112000,87250,112000"
pts [
"74000,112000"
"87250,112000"
]
)
end &131
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 21031,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21032,0
va (VaSet
)
xt "75000,111000,86200,112000"
st "spi_interface_config_valid"
blo "75000,111800"
tm "WireNameMgr"
)
)
on &554
)
*1091 (Wire
uid 21049,0
shape (OrthoPolyLine
uid 21050,0
va (VaSet
vasetType 3
)
xt "-2250,125000,10000,125000"
pts [
"10000,125000"
"-2250,125000"
]
)
end &251
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 21053,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21054,0
va (VaSet
)
xt "-1000,124000,10500,125000"
st "spi_interface_config_start"
blo "-1000,124800"
tm "WireNameMgr"
)
)
on &553
)
*1092 (Wire
uid 21061,0
shape (OrthoPolyLine
uid 21062,0
va (VaSet
vasetType 3
)
xt "-2250,126000,10000,126000"
pts [
"-2250,126000"
"10000,126000"
]
)
start &250
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 21065,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21066,0
va (VaSet
)
xt "-1000,125000,10200,126000"
st "spi_interface_config_valid"
blo "-1000,125800"
tm "WireNameMgr"
)
)
on &554
)
*1093 (Wire
uid 21067,0
shape (OrthoPolyLine
uid 21068,0
va (VaSet
vasetType 3
)
xt "14000,76000,27250,76000"
pts [
"27250,76000"
"14000,76000"
]
)
start &720
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 21073,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21074,0
va (VaSet
)
xt "15000,75000,27900,76000"
st "memory_manager_config_start"
blo "15000,75800"
tm "WireNameMgr"
)
)
on &551
)
*1094 (Wire
uid 21083,0
shape (OrthoPolyLine
uid 21084,0
va (VaSet
vasetType 3
)
xt "14000,77000,27250,77000"
pts [
"14000,77000"
"27250,77000"
]
)
end &724
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 21089,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21090,0
va (VaSet
)
xt "15000,76000,27600,77000"
st "memory_manager_config_valid"
blo "15000,76800"
tm "WireNameMgr"
)
)
on &552
)
*1095 (Wire
uid 21559,0
shape (OrthoPolyLine
uid 21560,0
va (VaSet
vasetType 3
)
xt "-26000,130000,-19750,130000"
pts [
"-26000,130000"
"-19750,130000"
]
)
end &260
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 21565,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21566,0
va (VaSet
)
xt "-25000,129000,-19800,130000"
st "sclk_enable"
blo "-25000,129800"
tm "WireNameMgr"
)
)
on &294
)
*1096 (Wire
uid 21768,0
shape (OrthoPolyLine
uid 21769,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-36000,99000,-24750,99000"
pts [
"-36000,99000"
"-24750,99000"
]
)
end &52
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 21774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21775,0
va (VaSet
)
xt "-35000,98000,-28300,99000"
st "plllock_in : (3:0)"
blo "-35000,98800"
tm "WireNameMgr"
)
)
on &433
)
*1097 (Wire
uid 21917,0
shape (OrthoPolyLine
uid 21918,0
va (VaSet
vasetType 3
)
xt "-83000,120000,-81000,120000"
pts [
"-83000,120000"
"-81000,120000"
]
)
start &567
end &585
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 21919,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21920,0
va (VaSet
isHidden 1
)
xt "-81000,119000,-78400,120000"
st "dout0"
blo "-81000,119800"
tm "WireNameMgr"
)
)
on &596
)
*1098 (Wire
uid 21923,0
shape (OrthoPolyLine
uid 21924,0
va (VaSet
vasetType 3
)
xt "-83000,122000,-81000,122000"
pts [
"-83000,122000"
"-81000,122000"
]
)
start &568
end &587
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 21925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21926,0
va (VaSet
isHidden 1
)
xt "-81000,121000,-78500,122000"
st "dout1"
blo "-81000,121800"
tm "WireNameMgr"
)
)
on &597
)
*1099 (Wire
uid 21929,0
shape (OrthoPolyLine
uid 21930,0
va (VaSet
vasetType 3
)
xt "-83000,124000,-81000,124000"
pts [
"-83000,124000"
"-81000,124000"
]
)
start &569
end &589
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 21931,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21932,0
va (VaSet
isHidden 1
)
xt "-81000,123000,-78400,124000"
st "dout2"
blo "-81000,123800"
tm "WireNameMgr"
)
)
on &598
)
*1100 (Wire
uid 21935,0
shape (OrthoPolyLine
uid 21936,0
va (VaSet
vasetType 3
)
xt "-83000,126000,-81000,126000"
pts [
"-83000,126000"
"-81000,126000"
]
)
start &570
end &591
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 21937,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21938,0
va (VaSet
isHidden 1
)
xt "-81000,125000,-78400,126000"
st "dout3"
blo "-81000,125800"
tm "WireNameMgr"
)
)
on &599
)
*1101 (Wire
uid 21986,0
shape (OrthoPolyLine
uid 21987,0
va (VaSet
vasetType 3
)
xt "-75000,123000,-66000,123000"
pts [
"-75000,123000"
"-66000,123000"
]
)
start &575
end &616
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 21988,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21989,0
va (VaSet
isHidden 1
)
xt "-66000,122000,-63900,123000"
st "dout"
blo "-66000,122800"
tm "WireNameMgr"
)
)
on &623
)
*1102 (Wire
uid 21992,0
shape (OrthoPolyLine
uid 21993,0
va (VaSet
vasetType 3
lineColor "65535,0,0"
lineWidth 6
)
xt "-94000,125000,-66000,128000"
pts [
"-94000,128000"
"-70000,128000"
"-70000,125000"
"-66000,125000"
]
)
start &648
end &618
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 21996,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 21997,0
va (VaSet
)
xt "-72000,129000,-62400,130000"
st "I_really_want_dwrite"
blo "-72000,129800"
tm "WireNameMgr"
)
)
on &624
)
*1103 (Wire
uid 22068,0
shape (OrthoPolyLine
uid 22069,0
va (VaSet
vasetType 3
)
xt "-68000,114000,-57000,122000"
pts [
"-68000,114000"
"-59000,114000"
"-59000,122000"
"-57000,122000"
]
)
end &631
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 22074,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 22075,0
va (VaSet
)
xt "-68000,113000,-58700,114000"
st "dwrite_enable_w5300"
blo "-68000,113800"
tm "WireNameMgr"
)
)
on &625
)
*1104 (Wire
uid 22127,0
shape (OrthoPolyLine
uid 22128,0
va (VaSet
vasetType 3
)
xt "-60000,124000,-57000,124000"
pts [
"-60000,124000"
"-57000,124000"
]
)
start &601
end &633
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 22129,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 22130,0
va (VaSet
isHidden 1
)
xt "-58000,123000,-55400,124000"
st "dout4"
blo "-58000,123800"
tm "WireNameMgr"
)
)
on &645
)
*1105 (Wire
uid 22352,0
shape (OrthoPolyLine
uid 22353,0
va (VaSet
vasetType 3
)
xt "78000,134000,88250,134000"
pts [
"78000,134000"
"88250,134000"
]
)
end &381
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 22358,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 22359,0
va (VaSet
)
xt "79000,133000,88600,134000"
st "alarm_refclk_too_low"
blo "79000,133800"
tm "WireNameMgr"
)
)
on &445
)
*1106 (Wire
uid 22360,0
shape (OrthoPolyLine
uid 22361,0
va (VaSet
vasetType 3
)
xt "78000,133000,88250,133000"
pts [
"78000,133000"
"88250,133000"
]
)
end &380
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 22366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 22367,0
va (VaSet
)
xt "79000,132000,89000,133000"
st "alarm_refclk_too_high"
blo "79000,132800"
tm "WireNameMgr"
)
)
on &443
)
*1107 (Wire
uid 23047,0
shape (OrthoPolyLine
uid 23048,0
va (VaSet
vasetType 3
)
xt "166000,78000,169000,81000"
pts [
"166000,78000"
"169000,78000"
"169000,81000"
]
)
start &450
end &657
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 23049,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23050,0
va (VaSet
)
xt "168000,77000,173200,78000"
st "denable_sig"
blo "168000,77800"
tm "WireNameMgr"
)
)
on &669
)
*1108 (Wire
uid 23055,0
shape (OrthoPolyLine
uid 23056,0
va (VaSet
vasetType 3
)
xt "-36000,113000,-24750,113000"
pts [
"-36000,113000"
"-24750,113000"
]
)
end &69
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 23061,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23062,0
va (VaSet
)
xt "-35000,112000,-29800,113000"
st "denable_sig"
blo "-35000,112800"
tm "WireNameMgr"
)
)
on &669
)
*1109 (Wire
uid 23063,0
shape (OrthoPolyLine
uid 23064,0
va (VaSet
vasetType 3
)
xt "-36000,114000,-24750,114000"
pts [
"-36000,114000"
"-24750,114000"
]
)
end &70
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 23069,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23070,0
va (VaSet
)
xt "-35000,113000,-25700,114000"
st "dwrite_enable_w5300"
blo "-35000,113800"
tm "WireNameMgr"
)
)
on &625
)
*1110 (Wire
uid 23343,0
shape (OrthoPolyLine
uid 23344,0
va (VaSet
vasetType 3
)
xt "-35000,111000,-24750,111000"
pts [
"-35000,111000"
"-24750,111000"
]
)
end &67
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 23347,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23348,0
va (VaSet
)
xt "-34000,110000,-25500,111000"
st "DCM_locked_status"
blo "-34000,110800"
tm "WireNameMgr"
)
)
on &670
)
*1111 (Wire
uid 23351,0
shape (OrthoPolyLine
uid 23352,0
va (VaSet
vasetType 3
)
xt "-36000,112000,-24750,112000"
pts [
"-36000,112000"
"-24750,112000"
]
)
end &68
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 23355,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23356,0
va (VaSet
)
xt "-35000,111000,-26800,112000"
st "DCM_ready_status"
blo "-35000,111800"
tm "WireNameMgr"
)
)
on &671
)
*1112 (Wire
uid 23357,0
shape (OrthoPolyLine
uid 23358,0
va (VaSet
vasetType 3
)
xt "-41250,17000,-32000,17000"
pts [
"-41250,17000"
"-32000,17000"
]
)
start &306
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 23363,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23364,0
va (VaSet
)
xt "-40000,16000,-31800,17000"
st "DCM_ready_status"
blo "-40000,16800"
tm "WireNameMgr"
)
)
on &671
)
*1113 (Wire
uid 23365,0
shape (OrthoPolyLine
uid 23366,0
va (VaSet
vasetType 3
)
xt "-41250,16000,-32000,16000"
pts [
"-41250,16000"
"-32000,16000"
]
)
start &305
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 23371,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23372,0
va (VaSet
)
xt "-40000,15000,-31500,16000"
st "DCM_locked_status"
blo "-40000,15800"
tm "WireNameMgr"
)
)
on &670
)
*1114 (Wire
uid 23600,0
shape (OrthoPolyLine
uid 23601,0
va (VaSet
vasetType 3
)
xt "-36000,115000,-24750,115000"
pts [
"-36000,115000"
"-24750,115000"
]
)
end &71
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 23606,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23607,0
va (VaSet
)
xt "-36000,114000,-30800,115000"
st "sclk_enable"
blo "-36000,114800"
tm "WireNameMgr"
)
)
on &294
)
*1115 (Wire
uid 23833,0
shape (OrthoPolyLine
uid 23834,0
va (VaSet
vasetType 3
)
xt "124750,86000,134000,86000"
pts [
"124750,86000"
"134000,86000"
]
)
start &133
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 23839,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 23840,0
va (VaSet
)
xt "126000,85000,134200,86000"
st "DCM_ready_status"
blo "126000,85800"
tm "WireNameMgr"
)
)
on &671
)
*1116 (Wire
uid 24078,0
shape (OrthoPolyLine
uid 24079,0
va (VaSet
vasetType 3
)
xt "59000,99000,65000,99000"
pts [
"59000,99000"
"65000,99000"
]
)
start &828
end &673
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 24082,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24083,0
ro 270
va (VaSet
isHidden 1
)
xt "58000,92400,59000,98000"
st "trigger_veto"
blo "58800,98000"
tm "WireNameMgr"
)
)
on &672
)
*1117 (Wire
uid 24646,0
shape (OrthoPolyLine
uid 24647,0
va (VaSet
vasetType 3
)
xt "-250,157000,4000,157000"
pts [
"-250,157000"
"4000,157000"
]
)
start &678
end &687
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 24650,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24651,0
va (VaSet
isHidden 1
)
xt "1000,156000,9100,157000"
st "FTM_RS485_tx_d"
blo "1000,156800"
tm "WireNameMgr"
)
)
on &692
)
*1118 (Wire
uid 24660,0
shape (OrthoPolyLine
uid 24661,0
va (VaSet
vasetType 3
)
xt "-250,158000,4000,158000"
pts [
"4000,158000"
"-250,158000"
]
)
start &688
end &676
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 24664,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24665,0
va (VaSet
isHidden 1
)
xt "1000,157000,9100,158000"
st "FTM_RS485_rx_d"
blo "1000,157800"
tm "WireNameMgr"
)
)
on &691
)
*1119 (Wire
uid 24674,0
shape (OrthoPolyLine
uid 24675,0
va (VaSet
vasetType 3
)
xt "-250,159000,5000,159000"
pts [
"-250,159000"
"5000,159000"
]
)
start &677
end &689
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 24678,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24679,0
va (VaSet
isHidden 1
)
xt "1000,158000,9400,159000"
st "FTM_RS485_rx_en"
blo "1000,158800"
tm "WireNameMgr"
)
)
on &693
)
*1120 (Wire
uid 24688,0
shape (OrthoPolyLine
uid 24689,0
va (VaSet
vasetType 3
)
xt "-250,160000,5000,160000"
pts [
"-250,160000"
"5000,160000"
]
)
start &679
end &690
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 24692,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24693,0
va (VaSet
isHidden 1
)
xt "1000,159000,9400,160000"
st "FTM_RS485_tx_en"
blo "1000,159800"
tm "WireNameMgr"
)
)
on &694
)
*1121 (Wire
uid 24708,0
shape (OrthoPolyLine
uid 24709,0
va (VaSet
vasetType 3
)
xt "-29000,149000,-21750,149000"
pts [
"-29000,149000"
"-21750,149000"
]
)
end &675
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 24714,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24715,0
va (VaSet
)
xt "-25000,148000,-21700,149000"
st "CLK_50"
blo "-25000,148800"
tm "WireNameMgr"
)
)
on &186
)
*1122 (Wire
uid 24724,0
shape (OrthoPolyLine
uid 24725,0
va (VaSet
vasetType 3
)
xt "-250,150000,12000,150000"
pts [
"-250,150000"
"12000,150000"
]
)
start &680
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 24730,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24731,0
va (VaSet
)
xt "2000,149000,11000,150000"
st "drs_readout_started"
blo "2000,149800"
tm "WireNameMgr"
)
)
on &387
)
*1123 (Wire
uid 24738,0
shape (OrthoPolyLine
uid 24739,0
va (VaSet
vasetType 3
)
xt "-250,153000,11000,153000"
pts [
"-250,153000"
"11000,153000"
]
)
start &683
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 24742,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24743,0
va (VaSet
)
xt "1000,152000,9800,153000"
st "rec_timeout_occured"
blo "1000,152800"
tm "WireNameMgr"
)
)
on &695
)
*1124 (Wire
uid 24750,0
shape (OrthoPolyLine
uid 24751,0
va (VaSet
vasetType 3
)
xt "-36000,104000,-24750,104000"
pts [
"-36000,104000"
"-24750,104000"
]
)
end &73
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 24756,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 24757,0
va (VaSet
)
xt "-36000,103000,-27200,104000"
st "rec_timeout_occured"
blo "-36000,103800"
tm "WireNameMgr"
)
)
on &695
)
*1125 (Wire
uid 25029,0
shape (OrthoPolyLine
uid 25030,0
va (VaSet
vasetType 3
)
xt "124750,94000,133000,94000"
pts [
"124750,94000"
"133000,94000"
]
)
start &135
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 25033,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25034,0
va (VaSet
)
xt "125000,93000,132200,94000"
st "reset_trigger_id"
blo "125000,93800"
tm "WireNameMgr"
)
)
on &696
)
*1126 (Wire
uid 25035,0
shape (OrthoPolyLine
uid 25036,0
va (VaSet
vasetType 3
)
xt "-61000,66000,-52750,66000"
pts [
"-61000,66000"
"-52750,66000"
]
)
end &153
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 25041,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25042,0
va (VaSet
)
xt "-61000,65000,-53800,66000"
st "reset_trigger_id"
blo "-61000,65800"
tm "WireNameMgr"
)
)
on &696
)
*1127 (Wire
uid 25298,0
shape (OrthoPolyLine
uid 25299,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "124750,108000,132000,108000"
pts [
"124750,108000"
"132000,108000"
]
)
start &136
end &697
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 25302,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25303,0
va (VaSet
isHidden 1
)
xt "126000,107000,132000,108000"
st "w5300_state"
blo "126000,107800"
tm "WireNameMgr"
)
)
on &698
)
*1128 (Wire
uid 25543,0
shape (OrthoPolyLine
uid 25544,0
va (VaSet
vasetType 3
)
xt "124750,109000,137000,109000"
pts [
"124750,109000"
"137000,109000"
]
)
start &137
end &700
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 25547,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25548,0
va (VaSet
isHidden 1
)
xt "126000,108000,136400,109000"
st "debug_data_ram_empty"
blo "126000,108800"
tm "WireNameMgr"
)
)
on &699
)
*1129 (Wire
uid 25557,0
shape (OrthoPolyLine
uid 25558,0
va (VaSet
vasetType 3
)
xt "124750,110000,135000,110000"
pts [
"124750,110000"
"135000,110000"
]
)
start &138
end &702
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 25561,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25562,0
va (VaSet
isHidden 1
)
xt "126000,109000,133500,110000"
st "debug_data_valid"
blo "126000,109800"
tm "WireNameMgr"
)
)
on &701
)
*1130 (Wire
uid 25842,0
shape (OrthoPolyLine
uid 25843,0
va (VaSet
vasetType 3
)
xt "-40000,76000,-24750,78000"
pts [
"-24750,76000"
"-28000,76000"
"-28000,78000"
"-40000,78000"
]
)
start &76
end &704
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 25844,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 25845,0
va (VaSet
)
xt "-34750,75000,-26250,76000"
st "software_trigger_in"
blo "-34750,75800"
tm "WireNameMgr"
)
)
on &711
)
*1131 (Wire
uid 26073,0
shape (OrthoPolyLine
uid 26074,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59750,86000,67000,86000"
pts [
"59750,86000"
"67000,86000"
]
)
start &718
end &712
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 26077,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 26078,0
va (VaSet
isHidden 1
)
xt "61000,85000,69500,86000"
st "mem_manager_state"
blo "61000,85800"
tm "WireNameMgr"
)
)
on &713
)
*1132 (Wire
uid 26336,0
shape (OrthoPolyLine
uid 26337,0
va (VaSet
vasetType 3
)
xt "3750,103000,13000,103000"
pts [
"3750,103000"
"13000,103000"
]
)
start &77
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 26340,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 26341,0
va (VaSet
)
xt "9000,102000,11800,103000"
st "is_idle"
blo "9000,102800"
tm "WireNameMgr"
)
)
on &714
)
*1133 (Wire
uid 26344,0
shape (OrthoPolyLine
uid 26345,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3750,108000,7000,108000"
pts [
"3750,108000"
"7000,108000"
]
)
start &78
end &715
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 26348,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 26349,0
va (VaSet
isHidden 1
)
xt "5000,107000,9000,108000"
st "DG_state"
blo "5000,107800"
tm "WireNameMgr"
)
)
on &716
)
*1134 (Wire
uid 26356,0
shape (OrthoPolyLine
uid 26357,0
va (VaSet
vasetType 3
)
xt "80000,92000,87250,92000"
pts [
"80000,92000"
"87250,92000"
]
)
end &139
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 26362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 26363,0
va (VaSet
)
xt "83000,91000,85800,92000"
st "is_idle"
blo "83000,91800"
tm "WireNameMgr"
)
)
on &714
)
*1135 (Wire
uid 27133,0
shape (OrthoPolyLine
uid 27134,0
va (VaSet
vasetType 3
)
xt "59750,80000,87250,80000"
pts [
"87250,80000"
"59750,80000"
]
)
start &112
end &735
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 27135,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 27136,0
va (VaSet
)
xt "79250,79000,85850,80000"
st "data_valid_ack"
blo "79250,79800"
tm "WireNameMgr"
)
)
on &741
)
*1136 (Wire
uid 27149,0
shape (OrthoPolyLine
uid 27150,0
va (VaSet
vasetType 3
)
xt "3750,83000,27250,86000"
pts [
"27250,83000"
"7000,83000"
"7000,86000"
"3750,86000"
]
)
start &737
end &66
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 27151,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 27152,0
va (VaSet
)
xt "19250,82000,26250,83000"
st "dg_start_config"
blo "19250,82800"
tm "WireNameMgr"
)
)
on &742
)
*1137 (Wire
uid 27155,0
shape (OrthoPolyLine
uid 27156,0
va (VaSet
vasetType 3
)
xt "3750,84000,27250,87000"
pts [
"27250,84000"
"14000,84000"
"14000,87000"
"3750,87000"
]
)
start &736
end &65
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 27157,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 27158,0
va (VaSet
)
xt "19250,83000,25950,84000"
st "dg_config_done"
blo "19250,83800"
tm "WireNameMgr"
)
)
on &743
)
*1138 (Wire
uid 27605,0
shape (OrthoPolyLine
uid 27606,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-35000,105000,-24750,105000"
pts [
"-35000,105000"
"-24750,105000"
]
)
end &74
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 27609,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 27610,0
va (VaSet
)
xt "-34000,104000,-26400,105000"
st "runnumber : (31:0)"
blo "-34000,104800"
tm "WireNameMgr"
)
)
on &744
)
*1139 (Wire
uid 27611,0
shape (OrthoPolyLine
uid 27612,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "80000,121000,87250,121000"
pts [
"80000,121000"
"87250,121000"
]
)
end &134
sat 16
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 27617,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 27618,0
va (VaSet
)
xt "81000,120000,88600,121000"
st "runnumber : (31:0)"
blo "81000,120800"
tm "WireNameMgr"
)
)
on &744
)
*1140 (Wire
uid 28278,0
shape (OrthoPolyLine
uid 28279,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "124750,114000,139000,114000"
pts [
"124750,114000"
"139000,114000"
]
)
start &140
end &746
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 28282,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 28283,0
va (VaSet
isHidden 1
)
xt "126000,113000,134600,114000"
st "socket_tx_free_out"
blo "126000,113800"
tm "WireNameMgr"
)
)
on &745
)
*1141 (Wire
uid 29079,0
shape (OrthoPolyLine
uid 29080,0
va (VaSet
vasetType 3
)
xt "12000,72000,17000,94000"
pts [
"12000,72000"
"12000,94000"
"17000,94000"
]
)
start &955
end &771
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 29081,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 29082,0
va (VaSet
)
xt "10000,93000,16100,94000"
st "ram_write_ea"
blo "10000,93800"
tm "WireNameMgr"
)
)
on &164
)
*1142 (Wire
uid 29087,0
shape (OrthoPolyLine
uid 29088,0
va (VaSet
vasetType 3
)
xt "22000,94000,24000,94000"
pts [
"22000,94000"
"24000,94000"
]
)
start &773
end &748
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 29089,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 29090,0
va (VaSet
isHidden 1
)
xt "24000,93000,26600,94000"
st "dout5"
blo "24000,93800"
tm "WireNameMgr"
)
)
on &780
)
*1143 (Wire
uid 29093,0
shape (OrthoPolyLine
uid 29094,0
va (VaSet
vasetType 3
)
xt "3750,96000,24000,107000"
pts [
"3750,107000"
"14000,107000"
"14000,96000"
"24000,96000"
]
)
start &72
end &753
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 29095,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 29096,0
va (VaSet
)
xt "5750,106000,11750,107000"
st "trigger_veto1"
blo "5750,106800"
tm "WireNameMgr"
)
)
on &781
)
*1144 (Wire
uid 30719,0
shape (OrthoPolyLine
uid 30720,0
va (VaSet
vasetType 3
)
xt "-137000,66000,-125000,66000"
pts [
"-125000,66000"
"-137000,66000"
]
)
start &346
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 30725,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30726,0
va (VaSet
)
xt "-137750,65000,-132150,66000"
st "cont_trigger"
blo "-137750,65800"
tm "WireNameMgr"
)
)
on &548
)
*1145 (Wire
uid 30729,0
shape (OrthoPolyLine
uid 30730,0
va (VaSet
vasetType 3
)
xt "-113000,70000,-103000,71000"
pts [
"-113000,70000"
"-109000,70000"
"-103000,71000"
]
)
start &390
end &783
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 30731,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30732,0
va (VaSet
isHidden 1
)
xt "-111000,69000,-108400,70000"
st "dout6"
blo "-111000,69800"
tm "WireNameMgr"
)
)
on &805
)
*1146 (Wire
uid 30772,0
shape (OrthoPolyLine
uid 30773,0
va (VaSet
vasetType 3
)
xt "30000,95000,32000,95000"
pts [
"30000,95000"
"32000,95000"
]
)
start &750
end &810
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 30774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30775,0
va (VaSet
)
xt "29000,94000,35500,95000"
st "busy_high_active"
blo "29000,94800"
tm "WireNameMgr"
)
)
on &866
)
*1147 (Wire
uid 30792,0
shape (OrthoPolyLine
uid 30793,0
va (VaSet
vasetType 3
)
xt "124750,115000,152000,115000"
pts [
"124750,115000"
"152000,115000"
]
)
start &141
end &911
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 30796,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30797,0
va (VaSet
)
xt "146000,114000,151400,115000"
st "busy_enable"
blo "146000,114800"
tm "WireNameMgr"
)
)
on &824
)
*1148 (Wire
uid 30845,0
shape (OrthoPolyLine
uid 30846,0
va (VaSet
vasetType 3
)
xt "47000,97000,59000,97000"
pts [
"47000,97000"
"59000,97000"
]
)
start &888
end &826
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 30847,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30848,0
va (VaSet
isHidden 1
)
xt "49000,98000,52900,99000"
st "trig_veto"
blo "49000,98800"
tm "WireNameMgr"
)
)
on &838
)
*1149 (Wire
uid 30880,0
shape (OrthoPolyLine
uid 30881,0
va (VaSet
vasetType 3
)
xt "78000,135000,88250,135000"
pts [
"78000,135000"
"88250,135000"
]
)
end &382
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 30886,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30887,0
va (VaSet
)
xt "80000,134000,83900,135000"
st "trig_veto"
blo "80000,134800"
tm "WireNameMgr"
)
)
on &838
)
*1150 (Wire
uid 30923,0
shape (OrthoPolyLine
uid 30924,0
va (VaSet
vasetType 3
)
xt "124750,53000,137000,54000"
pts [
"124750,54000"
"137000,53000"
]
)
start &92
end &840
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 30925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30926,0
va (VaSet
)
xt "126750,53000,131850,54000"
st "wiz_reset1"
blo "126750,53800"
tm "WireNameMgr"
)
)
on &852
)
*1151 (Wire
uid 30927,0
shape (OrthoPolyLine
uid 30928,0
va (VaSet
vasetType 3
)
xt "78000,136000,88250,136000"
pts [
"78000,136000"
"88250,136000"
]
)
end &383
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 30933,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 30934,0
va (VaSet
)
xt "79750,135000,84850,136000"
st "wiz_reset1"
blo "79750,135800"
tm "WireNameMgr"
)
)
on &852
)
*1152 (Wire
uid 31176,0
shape (OrthoPolyLine
uid 31177,0
va (VaSet
vasetType 3
)
xt "-36000,116000,-24750,116000"
pts [
"-36000,116000"
"-24750,116000"
]
)
end &79
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 31182,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31183,0
va (VaSet
)
xt "-31000,115000,-25600,116000"
st "busy_enable"
blo "-31000,115800"
tm "WireNameMgr"
)
)
on &824
)
*1153 (Wire
uid 31184,0
shape (OrthoPolyLine
uid 31185,0
va (VaSet
vasetType 3
)
xt "-36000,117000,-24750,117000"
pts [
"-24750,117000"
"-36000,117000"
]
)
start &80
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 31190,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31191,0
va (VaSet
)
xt "-32750,116000,-25550,117000"
st "c_trigger_enable"
blo "-32750,116800"
tm "WireNameMgr"
)
)
on &427
)
*1154 (Wire
uid 31194,0
shape (OrthoPolyLine
uid 31195,0
va (VaSet
vasetType 3
)
xt "124750,116000,137000,116000"
pts [
"124750,116000"
"137000,116000"
]
)
start &142
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 31198,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31199,0
va (VaSet
)
xt "126000,115000,136200,116000"
st "socket_send_mode_out"
blo "126000,115800"
tm "WireNameMgr"
)
)
on &853
)
*1155 (Wire
uid 31200,0
shape (OrthoPolyLine
uid 31201,0
va (VaSet
vasetType 3
)
xt "-36000,118000,-24750,118000"
pts [
"-36000,118000"
"-24750,118000"
]
)
end &81
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 31206,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31207,0
va (VaSet
)
xt "-36000,117000,-25800,118000"
st "socket_send_mode_out"
blo "-36000,117800"
tm "WireNameMgr"
)
)
on &853
)
*1156 (Wire
uid 31216,0
shape (OrthoPolyLine
uid 31217,0
va (VaSet
vasetType 3
)
xt "-36000,119000,-24750,119000"
pts [
"-36000,119000"
"-24750,119000"
]
)
end &82
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 31222,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31223,0
va (VaSet
)
xt "-36000,118000,-29700,119000"
st "trigger_enable"
blo "-36000,118800"
tm "WireNameMgr"
)
)
on &388
)
*1157 (Wire
uid 31735,0
shape (OrthoPolyLine
uid 31736,0
va (VaSet
vasetType 3
)
xt "26000,62000,59250,62000"
pts [
"59250,62000"
"26000,62000"
]
)
start &423
end &871
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 31737,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31738,0
ro 270
va (VaSet
)
xt "58250,58000,59250,61200"
st "trigger1"
blo "59050,61200"
tm "WireNameMgr"
)
)
on &854
)
*1158 (Wire
uid 31739,0
shape (OrthoPolyLine
uid 31740,0
va (VaSet
vasetType 3
)
xt "35000,63000,45000,63000"
pts [
"35000,63000"
"45000,63000"
]
)
start &856
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 31745,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 31746,0
va (VaSet
)
xt "37000,63000,43500,64000"
st "busy_high_active"
blo "37000,63800"
tm "WireNameMgr"
)
)
on &866
)
*1159 (Wire
uid 31773,0
shape (OrthoPolyLine
uid 31774,0
va (VaSet
vasetType 3
)
xt "26000,63000,30000,64000"
pts [
"30000,63000"
"28000,63000"
"28000,64000"
"26000,64000"
]
)
start &858
end &873
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 31775,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 31776,0
va (VaSet
isHidden 1
)
xt "29000,67000,31200,68000"
st "dout8"
blo "29000,67800"
tm "WireNameMgr"
)
)
on &865
)
*1160 (Wire
uid 32335,0
shape (OrthoPolyLine
uid 32336,0
va (VaSet
vasetType 3
)
xt "38000,96000,41000,96000"
pts [
"38000,96000"
"41000,96000"
]
)
start &807
end &886
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 32337,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32338,0
va (VaSet
isHidden 1
)
xt "40000,95000,42600,96000"
st "dout7"
blo "40000,95800"
tm "WireNameMgr"
)
)
on &908
)
*1161 (Wire
uid 32363,0
shape (OrthoPolyLine
uid 32364,0
va (VaSet
vasetType 3
)
xt "124750,95000,133000,95000"
pts [
"124750,95000"
"133000,95000"
]
)
start &143
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 32367,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32368,0
va (VaSet
)
xt "126000,94000,131500,95000"
st "busy_manual"
blo "126000,94800"
tm "WireNameMgr"
)
)
on &909
)
*1162 (Wire
uid 32369,0
shape (OrthoPolyLine
uid 32370,0
va (VaSet
vasetType 3
)
xt "38000,98000,41000,98000"
pts [
"38000,98000"
"41000,98000"
]
)
end &891
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 32375,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32376,0
va (VaSet
)
xt "38000,97000,43500,98000"
st "busy_manual"
blo "38000,97800"
tm "WireNameMgr"
)
)
on &909
)
*1163 (Wire
uid 32377,0
shape (OrthoPolyLine
uid 32378,0
va (VaSet
vasetType 3
)
xt "80000,101000,87250,101000"
pts [
"80000,101000"
"87250,101000"
]
)
end &144
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 32383,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32384,0
va (VaSet
)
xt "80000,100000,86100,101000"
st "ram_write_ea"
blo "80000,100800"
tm "WireNameMgr"
)
)
on &164
)
*1164 (Wire
uid 32393,0
shape (OrthoPolyLine
uid 32394,0
va (VaSet
vasetType 3
)
xt "-36000,120000,-24750,120000"
pts [
"-36000,120000"
"-24750,120000"
]
)
end &83
es 0
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 32399,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32400,0
va (VaSet
)
xt "-35000,119000,-29500,120000"
st "busy_manual"
blo "-35000,119800"
tm "WireNameMgr"
)
)
on &909
)
*1165 (Wire
uid 32666,0
shape (OrthoPolyLine
uid 32667,0
va (VaSet
vasetType 3
)
xt "157000,115000,169000,115000"
pts [
"157000,115000"
"169000,115000"
]
)
start &913
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 32670,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32671,0
va (VaSet
)
xt "158000,114000,165100,115000"
st "not_busy_enable"
blo "158000,114800"
tm "WireNameMgr"
)
)
on &920
)
*1166 (Wire
uid 32676,0
shape (OrthoPolyLine
uid 32677,0
va (VaSet
vasetType 3
)
xt "29000,97000,32000,97000"
pts [
"29000,97000"
"32000,97000"
]
)
end &812
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 32682,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 32683,0
va (VaSet
)
xt "27000,96000,34100,97000"
st "not_busy_enable"
blo "27000,96800"
tm "WireNameMgr"
)
)
on &920
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *1167 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*1168 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
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use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use ieee.STD_LOGIC_UNSIGNED.all;

library fact_fad_lib;
use fact_fad_lib.fad_definitions.all;

library UNISIM;
--use UNISIM.VComponents.all;
USE IEEE.NUMERIC_STD.all;
USE IEEE.std_logic_signed.all;
USE fact_fad_lib.fad_rs485_constants.all;
LIBRARY hds_package_library;
USE hds_package_library.random_generators.all;"
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)
*1212 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
o 64
suid 3,0
)
)
uid 518,0
)
*1213 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 DOWNTO 0)"
o 70
suid 4,0
)
)
uid 520,0
)
*1214 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
o 105
suid 9,0
)
)
uid 530,0
)
*1215 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 downto 0)"
o 106
suid 10,0
)
)
uid 532,0
)
*1216 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 50
suid 11,0
i "'1'"
)
)
uid 534,0
)
*1217 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 47
suid 12,0
)
)
uid 536,0
)
*1218 (LeafLogPort
port (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 53
suid 13,0
)
)
uid 538,0
)
*1219 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 48
suid 14,0
i "'1'"
)
)
uid 540,0
)
*1220 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 51
suid 15,0
i "'1'"
)
)
uid 542,0
)
*1221 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 49
suid 17,0
i "'1'"
)
)
uid 546,0
)
*1222 (LeafLogPort
port (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 18,0
)
)
uid 548,0
)
*1223 (LeafLogPort
port (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 28,0
)
)
uid 1455,0
)
*1224 (LeafLogPort
port (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 29,0
)
)
uid 1457,0
)
*1225 (LeafLogPort
port (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 30,0
)
)
uid 1694,0
)
*1226 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 107
suid 36,0
)
)
uid 2305,0
)
*1227 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 139
suid 39,0
i "'0'"
)
)
uid 2512,0
)
*1228 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 142
suid 40,0
i "(others => '0')"
)
)
uid 2514,0
)
*1229 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
preAdd 0
o 138
suid 41,0
i "(others => '0')"
)
)
uid 2516,0
)
*1230 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 137
suid 42,0
i "(others => '0')"
)
)
uid 2518,0
)
*1231 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_end"
t "std_logic"
o 140
suid 43,0
i "'0'"
)
)
uid 2520,0
)
*1232 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "wiz_write_header"
t "std_logic"
o 141
suid 44,0
i "'0'"
)
)
uid 2522,0
)
*1233 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_write_ea"
t "std_logic"
o 108
suid 48,0
)
)
uid 2604,0
)
*1234 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ram_write_ready"
t "std_logic"
o 109
suid 49,0
i "'0'"
)
)
uid 2606,0
)
*1235 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "roi_max"
t "roi_max_type"
o 114
suid 52,0
)
)
uid 2612,0
)
*1236 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 101
suid 54,0
)
)
uid 2646,0
)
*1237 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 57,0
i "'1'"
)
)
uid 2812,0
)
*1238 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 81,0
)
)
uid 3902,0
)
*1239 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 90,0
)
)
uid 4070,0
)
*1240 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CLK_25"
t "std_logic"
preAdd 0
posAdd 0
o 54
suid 91,0
)
)
uid 4212,0
)
*1241 (LeafLogPort
port (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 92,0
)
)
uid 4234,0
)
*1242 (LeafLogPort
port (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 95,0
)
)
uid 4262,0
)
*1243 (LeafLogPort
port (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 96,0
)
)
uid 4276,0
)
*1244 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_clk_en"
t "std_logic"
o 85
suid 97,0
i "'0'"
)
)
uid 4563,0
)
*1245 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 91
suid 98,0
)
)
uid 4565,0
)
*1246 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 86
suid 100,0
i "'0'"
)
)
uid 4569,0
)
*1247 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 109,0
i "(others => '0')"
)
)
uid 4585,0
)
*1248 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 110,0
i "'1'"
)
)
uid 4587,0
)
*1249 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 112,0
)
)
uid 4733,0
)
*1250 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 113,0
)
)
uid 4735,0
)
*1251 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 114,0
)
)
uid 4737,0
)
*1252 (LeafLogPort
port (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 115,0
)
)
uid 4739,0
)
*1253 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 87
suid 116,0
)
)
uid 4749,0
)
*1254 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 117,0
i "'0'"
)
)
uid 4974,0
)
*1255 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 118,0
i "'0'"
)
)
uid 4976,0
)
*1256 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 133,0
i "(OTHERS => '0')"
)
)
uid 5226,0
)
*1257 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_ready"
t "std_logic"
o 122
suid 140,0
)
)
uid 5502,0
)
*1258 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 121
suid 141,0
)
)
uid 5504,0
)
*1259 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 63
suid 146,0
)
)
uid 5642,0
)
*1260 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 62
suid 147,0
)
)
uid 5644,0
)
*1261 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 151,0
)
)
uid 5867,0
)
*1262 (LeafLogPort
port (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 152,0
)
)
uid 5869,0
)
*1263 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 153,0
)
)
uid 5871,0
)
*1264 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 154,0
)
)
uid 5873,0
)
*1265 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 162,0
i "'0'"
)
)
uid 6172,0
)
*1266 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 166,0
i "'0'"
)
)
uid 6374,0
)
*1267 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sclk_enable"
t "std_logic"
o 120
suid 194,0
)
)
uid 8760,0
)
*1268 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "adc_clk_en"
t "std_logic"
o 61
suid 195,0
)
)
uid 9018,0
)
*1269 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_direction"
t "std_logic"
eolc "-- default phase shift upwards"
posAdd 0
o 102
suid 196,0
i "'1'"
)
)
uid 9247,0
)
*1270 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 103
suid 197,0
i "'0'"
)
)
uid 9249,0
)
*1271 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 104
suid 221,0
i "'0'"
)
)
uid 10024,0
)
*1272 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "srclk_enable"
t "std_logic"
o 128
suid 222,0
i "'0'"
)
)
uid 10026,0
)
*1273 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "SRCLK1"
t "std_logic"
o 60
suid 224,0
i "'0'"
)
)
uid 10028,0
)
*1274 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "s_trigger"
t "std_logic"
o 118
suid 230,0
)
)
uid 10294,0
)
*1275 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "start_srin_write_8b"
t "std_logic"
o 131
suid 231,0
)
)
uid 10334,0
)
*1276 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "srin_write_ack"
t "std_logic"
o 129
suid 232,0
i "'0'"
)
)
uid 10336,0
)
*1277 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "srin_write_ready"
t "std_logic"
o 130
suid 233,0
i "'0'"
)
)
uid 10338,0
)
*1278 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_srin_data"
t "std_logic_vector"
b "(7 downto 0)"
o 92
suid 234,0
i "(others => '0')"
)
)
uid 10340,0
)
*1279 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 235,0
i "'0'"
)
)
uid 10342,0
)
*1280 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socks_connected"
t "std_logic"
o 123
suid 243,0
)
)
uid 10763,0
)
*1281 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socks_waiting"
t "std_logic"
o 124
suid 244,0
)
)
uid 10765,0
)
*1282 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 248,0
)
)
uid 10767,0
)
*1283 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 249,0
)
)
uid 10769,0
)
*1284 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 250,0
)
)
uid 10771,0
)
*1285 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_readout_started"
t "std_logic"
o 90
suid 252,0
)
)
uid 11411,0
)
*1286 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_enable"
t "std_logic"
o 133
suid 254,0
)
)
uid 11966,0
)
*1287 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_readout_ready"
t "std_logic"
prec "-- --
--      drs_dwrite : out std_logic := '1';"
preAdd 0
posAdd 0
o 88
suid 266,0
i "'0'"
)
)
uid 12661,0
)
*1288 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "drs_readout_ready_ack"
t "std_logic"
o 89
suid 267,0
)
)
uid 12663,0
)
*1289 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 65
suid 275,0
i "'0'"
)
)
uid 13275,0
)
*1290 (LeafLogPort
port (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 281,0
)
)
uid 13687,0
scheme 0
)
*1291 (LeafLogPort
port (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 284,0
)
)
uid 14040,0
scheme 0
)
*1292 (LeafLogPort
port (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 285,0
)
)
uid 14163,0
scheme 0
)
*1293 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 290,0
)
)
uid 14507,0
)
*1294 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 291,0
)
)
uid 14509,0
)
*1295 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 292,0
)
)
uid 14634,0
)
*1296 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "denable_prim"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 73
suid 294,0
i "'0'"
)
)
uid 15144,0
)
*1297 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "din1"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 77
suid 295,0
i "'0'"
)
)
uid 15146,0
)
*1298 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_out"
t "std_logic"
o 136
suid 301,0
)
)
uid 15504,0
)
*1299 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(31 downto 0)"
preAdd 0
posAdd 0
o 134
suid 302,0
)
)
uid 15754,0
)
*1300 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DCM_PS_status"
t "std_logic_vector"
b "(7 DOWNTO 0)"
preAdd 0
posAdd 0
o 55
suid 304,0
i "(OTHERS => '0')"
)
)
uid 16386,0
)
*1301 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dna"
t "STD_LOGIC_VECTOR"
b "(63 DOWNTO 0)"
preAdd 0
posAdd 0
o 78
suid 309,0
i "(others => '0')"
)
)
uid 16571,0
)
*1302 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ready"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 110
suid 311,0
i "'0'"
)
)
uid 16573,0
)
*1303 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enable_i"
t "std_logic"
o 96
suid 314,0
)
)
uid 16961,0
)
*1304 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset_synch_i"
t "std_logic"
o 112
suid 315,0
)
)
uid 16963,0
)
*1305 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "time"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 132
suid 317,0
)
)
uid 16965,0
)
*1306 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "rs465_data"
t "std_logic_vector"
b "(55 DOWNTO 0)"
eolc "--7 byte"
posAdd 0
o 116
suid 319,0
)
)
uid 17033,0
)
*1307 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "FTM_RS485_ready"
t "std_logic"
prec "--

-- EVT HEADER - part 2  --> FTM trigger informaton, comes in late ...
-- during EVT header wrinting, this field is left out ... and only written into event header,
-- when the DRS chip were read out already."
preAdd 0
o 58
suid 322,0
)
)
uid 17035,0
)
*1308 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
posAdd 0
o 66
suid 327,0
)
)
uid 17397,0
)
*1309 (LeafLogPort
port (LogicalPort
lang 2
m 4
decl (Decl
n "data_ram_empty"
t "std_logic"
o 71
suid 333,0
)
)
uid 18463,0
)
*1310 (LeafLogPort
port (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 334,0
)
)
uid 18966,0
scheme 0
)
*1311 (LeafLogPort
port (LogicalPort
lang 10
m 4
decl (Decl
n "current_dac_array"
t "dac_array_type"
o 68
suid 337,0
i "( others => 0)"
)
)
uid 20159,0
)
*1312 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_or_s_trigger"
t "std_logic"
preAdd 0
posAdd 0
o 135
suid 338,0
)
)
uid 20515,0
)
*1313 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "enabled_trigger_or_s_trigger"
t "std_logic"
preAdd 0
posAdd 0
o 97
suid 339,0
)
)
uid 20517,0
)
*1314 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "cont_trigger"
t "std_logic"
o 67
suid 340,0
)
)
uid 20523,0
)
*1315 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dac_setting"
t "dac_array_type"
eolc "--<<-- default defined in fad_definitions.vhd"
posAdd 0
o 69
suid 342,0
i "DEFAULT_DAC"
)
)
uid 21091,0
)
*1316 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "roi_setting"
t "roi_array_type"
o 115
suid 344,0
)
)
uid 21093,0
)
*1317 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memory_manager_config_start"
t "std_logic"
o 99
suid 356,0
i "'0'"
)
)
uid 21097,0
)
*1318 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memory_manager_config_valid"
t "std_logic"
o 100
suid 358,0
)
)
uid 21101,0
)
*1319 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "spi_interface_config_start"
t "std_logic"
o 126
suid 359,0
i "'0'"
)
)
uid 21103,0
)
*1320 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "spi_interface_config_valid"
t "std_logic"
o 127
suid 361,0
)
)
uid 21107,0
)
*1321 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout0"
t "STD_LOGIC"
o 80
suid 365,0
)
)
uid 22029,0
)
*1322 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout1"
t "STD_LOGIC"
o 81
suid 366,0
)
)
uid 22031,0
)
*1323 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout2"
t "STD_LOGIC"
o 82
suid 367,0
)
)
uid 22033,0
)
*1324 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout3"
t "STD_LOGIC"
o 83
suid 368,0
)
)
uid 22035,0
)
*1325 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout"
t "STD_LOGIC"
o 79
suid 369,0
)
)
uid 22037,0
)
*1326 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "I_really_want_dwrite"
t "STD_LOGIC"
o 59
suid 371,0
)
)
uid 22039,0
)
*1327 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dwrite_enable_w5300"
t "std_logic"
o 93
suid 374,0
i "'1'"
)
)
uid 22133,0
)
*1328 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dwrite_global_enable"
t "std_logic"
o 94
suid 376,0
i "'1'"
)
)
uid 22135,0
)
*1329 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout4"
t "STD_LOGIC"
o 84
suid 377,0
)
)
uid 22137,0
)
*1330 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dwrite_trigger_manager"
t "std_logic"
o 95
suid 378,0
i "'1'"
)
)
uid 22139,0
)
*1331 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "denable_sig"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 74
suid 380,0
i "'0'"
)
)
uid 23053,0
)
*1332 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DCM_locked_status"
t "std_logic"
o 56
suid 382,0
)
)
uid 23373,0
)
*1333 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DCM_ready_status"
t "std_logic"
o 57
suid 383,0
)
)
uid 23375,0
)
*1334 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 385,0
i "'1'"
)
)
uid 24090,0
)
*1335 (LeafLogPort
port (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 395,0
)
)
uid 24716,0
)
*1336 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 396,0
)
)
uid 24718,0
)
*1337 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 397,0
)
)
uid 24720,0
)
*1338 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 398,0
)
)
uid 24722,0
)
*1339 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "rec_timeout_occured"
t "std_logic"
o 111
suid 399,0
i "'0'"
)
)
uid 24744,0
)
*1340 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 113
suid 403,0
i "'0'"
)
)
uid 25043,0
)
*1341 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 406,0
)
)
uid 25312,0
)
*1342 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 407,0
)
)
uid 25569,0
)
*1343 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 408,0
)
)
uid 25571,0
)
*1344 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "software_trigger_in"
t "std_logic"
o 125
suid 409,0
)
)
uid 25846,0
)
*1345 (LeafLogPort
port (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 411,0
)
)
uid 26087,0
)
*1346 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "is_idle"
t "std_logic"
o 98
suid 413,0
)
)
uid 26364,0
)
*1347 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 415,0
)
)
uid 26593,0
)
*1348 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "data_valid_ack"
t "std_logic"
o 72
suid 416,0
i "'0'"
)
)
uid 27137,0
)
*1349 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dg_start_config"
t "std_logic"
o 76
suid 417,0
i "'0'"
)
)
uid 27159,0
)
*1350 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dg_config_done"
t "std_logic"
o 75
suid 418,0
)
)
uid 27161,0
)
*1351 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 downto 0)"
prec "-- EVT HEADER - part 6"
preAdd 0
posAdd 0
o 117
suid 419,0
)
)
uid 27619,0
)
*1352 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 421,0
)
)
uid 28290,0
)
*1353 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout5"
t "std_logic"
o 144
suid 422,0
)
)
uid 29097,0
)
*1354 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger_veto1"
t "std_logic"
o 145
suid 423,0
i "'1'"
)
)
uid 29099,0
)
*1355 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout6"
t "std_logic"
preAdd 0
posAdd 0
o 145
suid 431,0
)
)
uid 30806,0
)
*1356 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "busy_enable"
t "std_logic"
o 147
suid 434,0
i "'1'"
)
)
uid 30810,0
)
*1357 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trig_veto"
t "std_logic"
o 148
suid 436,0
)
)
uid 30935,0
)
*1358 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "wiz_reset1"
t "std_logic"
preAdd 0
posAdd 0
o 149
suid 437,0
i "'1'"
)
)
uid 30937,0
)
*1359 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "socket_send_mode_out"
t "std_logic"
o 150
suid 438,0
)
)
uid 31224,0
)
*1360 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "trigger1"
t "std_logic"
o 151
suid 439,0
)
)
uid 31777,0
)
*1361 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout8"
t "std_logic"
o 152
suid 440,0
)
)
uid 31779,0
)
*1362 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "busy_high_active"
t "std_logic"
o 146
suid 441,0
)
)
uid 31820,0
)
*1363 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout7"
t "std_logic"
o 153
suid 442,0
)
)
uid 32385,0
)
*1364 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "busy_manual"
t "std_logic"
o 154
suid 444,0
)
)
uid 32387,0
)
*1365 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "not_busy_enable"
t "STD_LOGIC"
o 79
suid 446,0
)
)
uid 32684,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*1366 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *1367 (MRCItem
litem &1198
pos 155
dimension 20
)
uid 69,0
optionalChildren [
*1368 (MRCItem
litem &1199
pos 0
dimension 20
uid 70,0
)
*1369 (MRCItem
litem &1200
pos 1
dimension 23
uid 71,0
)
*1370 (MRCItem
litem &1201
pos 2
hidden 1
dimension 20
uid 72,0
)
*1371 (MRCItem
litem &1211
pos 54
dimension 20
uid 517,0
)
*1372 (MRCItem
litem &1212
pos 55
dimension 20
uid 519,0
)
*1373 (MRCItem
litem &1213
pos 56
dimension 20
uid 521,0
)
*1374 (MRCItem
litem &1214
pos 57
dimension 20
uid 531,0
)
*1375 (MRCItem
litem &1215
pos 58
dimension 20
uid 533,0
)
*1376 (MRCItem
litem &1216
pos 0
dimension 20
uid 535,0
)
*1377 (MRCItem
litem &1217
pos 1
dimension 20
uid 537,0
)
*1378 (MRCItem
litem &1218
pos 2
dimension 20
uid 539,0
)
*1379 (MRCItem
litem &1219
pos 3
dimension 20
uid 541,0
)
*1380 (MRCItem
litem &1220
pos 4
dimension 20
uid 543,0
)
*1381 (MRCItem
litem &1221
pos 5
dimension 20
uid 547,0
)
*1382 (MRCItem
litem &1222
pos 6
dimension 20
uid 549,0
)
*1383 (MRCItem
litem &1223
pos 8
dimension 20
uid 1456,0
)
*1384 (MRCItem
litem &1224
pos 7
dimension 20
uid 1458,0
)
*1385 (MRCItem
litem &1225
pos 9
dimension 20
uid 1695,0
)
*1386 (MRCItem
litem &1226
pos 59
dimension 20
uid 2306,0
)
*1387 (MRCItem
litem &1227
pos 60
dimension 20
uid 2513,0
)
*1388 (MRCItem
litem &1228
pos 61
dimension 20
uid 2515,0
)
*1389 (MRCItem
litem &1229
pos 62
dimension 20
uid 2517,0
)
*1390 (MRCItem
litem &1230
pos 63
dimension 20
uid 2519,0
)
*1391 (MRCItem
litem &1231
pos 64
dimension 20
uid 2521,0
)
*1392 (MRCItem
litem &1232
pos 65
dimension 20
uid 2523,0
)
*1393 (MRCItem
litem &1233
pos 66
dimension 20
uid 2605,0
)
*1394 (MRCItem
litem &1234
pos 67
dimension 20
uid 2607,0
)
*1395 (MRCItem
litem &1235
pos 68
dimension 20
uid 2613,0
)
*1396 (MRCItem
litem &1236
pos 69
dimension 20
uid 2647,0
)
*1397 (MRCItem
litem &1237
pos 10
dimension 20
uid 2813,0
)
*1398 (MRCItem
litem &1238
pos 11
dimension 20
uid 3903,0
)
*1399 (MRCItem
litem &1239
pos 12
dimension 20
uid 4071,0
)
*1400 (MRCItem
litem &1240
pos 70
dimension 20
uid 4213,0
)
*1401 (MRCItem
litem &1241
pos 13
dimension 20
uid 4235,0
)
*1402 (MRCItem
litem &1242
pos 14
dimension 20
uid 4263,0
)
*1403 (MRCItem
litem &1243
pos 15
dimension 20
uid 4277,0
)
*1404 (MRCItem
litem &1244
pos 71
dimension 20
uid 4564,0
)
*1405 (MRCItem
litem &1245
pos 72
dimension 20
uid 4566,0
)
*1406 (MRCItem
litem &1246
pos 73
dimension 20
uid 4570,0
)
*1407 (MRCItem
litem &1247
pos 16
dimension 20
uid 4586,0
)
*1408 (MRCItem
litem &1248
pos 17
dimension 20
uid 4588,0
)
*1409 (MRCItem
litem &1249
pos 18
dimension 20
uid 4734,0
)
*1410 (MRCItem
litem &1250
pos 19
dimension 20
uid 4736,0
)
*1411 (MRCItem
litem &1251
pos 20
dimension 20
uid 4738,0
)
*1412 (MRCItem
litem &1252
pos 21
dimension 20
uid 4740,0
)
*1413 (MRCItem
litem &1253
pos 74
dimension 20
uid 4750,0
)
*1414 (MRCItem
litem &1254
pos 22
dimension 20
uid 4975,0
)
*1415 (MRCItem
litem &1255
pos 23
dimension 20
uid 4977,0
)
*1416 (MRCItem
litem &1256
pos 24
dimension 20
uid 5227,0
)
*1417 (MRCItem
litem &1257
pos 75
dimension 20
uid 5503,0
)
*1418 (MRCItem
litem &1258
pos 76
dimension 20
uid 5505,0
)
*1419 (MRCItem
litem &1259
pos 77
dimension 20
uid 5643,0
)
*1420 (MRCItem
litem &1260
pos 78
dimension 20
uid 5645,0
)
*1421 (MRCItem
litem &1261
pos 25
dimension 20
uid 5868,0
)
*1422 (MRCItem
litem &1262
pos 26
dimension 20
uid 5870,0
)
*1423 (MRCItem
litem &1263
pos 27
dimension 20
uid 5872,0
)
*1424 (MRCItem
litem &1264
pos 28
dimension 20
uid 5874,0
)
*1425 (MRCItem
litem &1265
pos 29
dimension 20
uid 6173,0
)
*1426 (MRCItem
litem &1266
pos 30
dimension 20
uid 6375,0
)
*1427 (MRCItem
litem &1267
pos 79
dimension 20
uid 8761,0
)
*1428 (MRCItem
litem &1268
pos 53
dimension 20
uid 9019,0
)
*1429 (MRCItem
litem &1269
pos 80
dimension 20
uid 9248,0
)
*1430 (MRCItem
litem &1270
pos 81
dimension 20
uid 9250,0
)
*1431 (MRCItem
litem &1271
pos 82
dimension 20
uid 10025,0
)
*1432 (MRCItem
litem &1272
pos 83
dimension 20
uid 10027,0
)
*1433 (MRCItem
litem &1273
pos 84
dimension 20
uid 10029,0
)
*1434 (MRCItem
litem &1274
pos 85
dimension 20
uid 10295,0
)
*1435 (MRCItem
litem &1275
pos 86
dimension 20
uid 10335,0
)
*1436 (MRCItem
litem &1276
pos 87
dimension 20
uid 10337,0
)
*1437 (MRCItem
litem &1277
pos 88
dimension 20
uid 10339,0
)
*1438 (MRCItem
litem &1278
pos 89
dimension 20
uid 10341,0
)
*1439 (MRCItem
litem &1279
pos 31
dimension 20
uid 10343,0
)
*1440 (MRCItem
litem &1280
pos 90
dimension 20
uid 10764,0
)
*1441 (MRCItem
litem &1281
pos 91
dimension 20
uid 10766,0
)
*1442 (MRCItem
litem &1282
pos 32
dimension 20
uid 10768,0
)
*1443 (MRCItem
litem &1283
pos 33
dimension 20
uid 10770,0
)
*1444 (MRCItem
litem &1284
pos 34
dimension 20
uid 10772,0
)
*1445 (MRCItem
litem &1285
pos 92
dimension 20
uid 11412,0
)
*1446 (MRCItem
litem &1286
pos 93
dimension 20
uid 11967,0
)
*1447 (MRCItem
litem &1287
pos 94
dimension 20
uid 12662,0
)
*1448 (MRCItem
litem &1288
pos 95
dimension 20
uid 12664,0
)
*1449 (MRCItem
litem &1289
pos 96
dimension 20
uid 13276,0
)
*1450 (MRCItem
litem &1290
pos 35
dimension 20
uid 13688,0
)
*1451 (MRCItem
litem &1291
pos 36
dimension 20
uid 14041,0
)
*1452 (MRCItem
litem &1292
pos 37
dimension 20
uid 14164,0
)
*1453 (MRCItem
litem &1293
pos 38
dimension 20
uid 14508,0
)
*1454 (MRCItem
litem &1294
pos 39
dimension 20
uid 14510,0
)
*1455 (MRCItem
litem &1295
pos 40
dimension 20
uid 14635,0
)
*1456 (MRCItem
litem &1296
pos 97
dimension 20
uid 15145,0
)
*1457 (MRCItem
litem &1297
pos 98
dimension 20
uid 15147,0
)
*1458 (MRCItem
litem &1298
pos 99
dimension 20
uid 15505,0
)
*1459 (MRCItem
litem &1299
pos 100
dimension 20
uid 15755,0
)
*1460 (MRCItem
litem &1300
pos 101
dimension 20
uid 16387,0
)
*1461 (MRCItem
litem &1301
pos 102
dimension 20
uid 16572,0
)
*1462 (MRCItem
litem &1302
pos 103
dimension 20
uid 16574,0
)
*1463 (MRCItem
litem &1303
pos 104
dimension 20
uid 16962,0
)
*1464 (MRCItem
litem &1304
pos 105
dimension 20
uid 16964,0
)
*1465 (MRCItem
litem &1305
pos 106
dimension 20
uid 16966,0
)
*1466 (MRCItem
litem &1306
pos 107
dimension 20
uid 17034,0
)
*1467 (MRCItem
litem &1307
pos 108
dimension 20
uid 17036,0
)
*1468 (MRCItem
litem &1308
pos 109
dimension 20
uid 17398,0
)
*1469 (MRCItem
litem &1309
pos 110
dimension 20
uid 18464,0
)
*1470 (MRCItem
litem &1310
pos 41
dimension 20
uid 18967,0
)
*1471 (MRCItem
litem &1311
pos 111
dimension 20
uid 20160,0
)
*1472 (MRCItem
litem &1312
pos 112
dimension 20
uid 20516,0
)
*1473 (MRCItem
litem &1313
pos 113
dimension 20
uid 20518,0
)
*1474 (MRCItem
litem &1314
pos 114
dimension 20
uid 20524,0
)
*1475 (MRCItem
litem &1315
pos 115
dimension 20
uid 21092,0
)
*1476 (MRCItem
litem &1316
pos 116
dimension 20
uid 21094,0
)
*1477 (MRCItem
litem &1317
pos 117
dimension 20
uid 21098,0
)
*1478 (MRCItem
litem &1318
pos 118
dimension 20
uid 21102,0
)
*1479 (MRCItem
litem &1319
pos 119
dimension 20
uid 21104,0
)
*1480 (MRCItem
litem &1320
pos 120
dimension 20
uid 21108,0
)
*1481 (MRCItem
litem &1321
pos 121
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uid 22032,0
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uid 22034,0
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*1484 (MRCItem
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uid 22036,0
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*1485 (MRCItem
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uid 22040,0
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uid 22134,0
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uid 22136,0
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*1489 (MRCItem
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pos 129
dimension 20
uid 22138,0
)
*1490 (MRCItem
litem &1330
pos 130
dimension 20
uid 22140,0
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*1491 (MRCItem
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pos 131
dimension 20
uid 23054,0
)
*1492 (MRCItem
litem &1332
pos 132
dimension 20
uid 23374,0
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*1493 (MRCItem
litem &1333
pos 133
dimension 20
uid 23376,0
)
*1494 (MRCItem
litem &1334
pos 42
dimension 20
uid 24091,0
)
*1495 (MRCItem
litem &1335
pos 43
dimension 20
uid 24717,0
)
*1496 (MRCItem
litem &1336
pos 44
dimension 20
uid 24719,0
)
*1497 (MRCItem
litem &1337
pos 45
dimension 20
uid 24721,0
)
*1498 (MRCItem
litem &1338
pos 46
dimension 20
uid 24723,0
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*1499 (MRCItem
litem &1339
pos 134
dimension 20
uid 24745,0
)
*1500 (MRCItem
litem &1340
pos 135
dimension 20
uid 25044,0
)
*1501 (MRCItem
litem &1341
pos 47
dimension 20
uid 25313,0
)
*1502 (MRCItem
litem &1342
pos 48
dimension 20
uid 25570,0
)
*1503 (MRCItem
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pos 49
dimension 20
uid 25572,0
)
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litem &1344
pos 136
dimension 20
uid 25847,0
)
*1505 (MRCItem
litem &1345
pos 50
dimension 20
uid 26088,0
)
*1506 (MRCItem
litem &1346
pos 137
dimension 20
uid 26365,0
)
*1507 (MRCItem
litem &1347
pos 51
dimension 20
uid 26594,0
)
*1508 (MRCItem
litem &1348
pos 138
dimension 20
uid 27138,0
)
*1509 (MRCItem
litem &1349
pos 139
dimension 20
uid 27160,0
)
*1510 (MRCItem
litem &1350
pos 140
dimension 20
uid 27162,0
)
*1511 (MRCItem
litem &1351
pos 141
dimension 20
uid 27620,0
)
*1512 (MRCItem
litem &1352
pos 52
dimension 20
uid 28291,0
)
*1513 (MRCItem
litem &1353
pos 142
dimension 20
uid 29098,0
)
*1514 (MRCItem
litem &1354
pos 143
dimension 20
uid 29100,0
)
*1515 (MRCItem
litem &1355
pos 144
dimension 20
uid 30807,0
)
*1516 (MRCItem
litem &1356
pos 145
dimension 20
uid 30811,0
)
*1517 (MRCItem
litem &1357
pos 146
dimension 20
uid 30936,0
)
*1518 (MRCItem
litem &1358
pos 147
dimension 20
uid 30938,0
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litem &1359
pos 148
dimension 20
uid 31225,0
)
*1520 (MRCItem
litem &1360
pos 149
dimension 20
uid 31778,0
)
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litem &1361
pos 150
dimension 20
uid 31780,0
)
*1522 (MRCItem
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pos 151
dimension 20
uid 31821,0
)
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litem &1363
pos 152
dimension 20
uid 32386,0
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*1524 (MRCItem
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dimension 20
uid 32388,0
)
*1525 (MRCItem
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uid 32685,0
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propVa (MVa
cellColor "0,49152,49152"
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uid 74,0
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pos 4
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litem &1208
pos 5
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litem &1209
pos 6
dimension 50
uid 80,0
)
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pos 7
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uid 81,0
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)
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vaOverrides [
]
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)
uid 53,0
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genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *1534 (LEmptyRow
)
uid 83,0
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*1535 (RefLabelRowHdr
)
*1536 (TitleRowHdr
)
*1537 (FilterRowHdr
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*1538 (RefLabelColHdr
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*1539 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*1540 (GroupColHdr
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*1541 (NameColHdr
tm "GenericNameColHdrMgr"
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*1542 (TypeColHdr
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*1543 (InitColHdr
tm "GenericValueColHdrMgr"
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*1544 (PragmaColHdr
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*1545 (EolColHdr
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cellVa (MVa
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groupVa (MVa
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