source: firmware/FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb.bak@ 18342

Last change on this file since 18342 was 11755, checked in by neise, 13 years ago
reinit of this svn repos .... it was all too messy deleted the old folders and restarted with FACT_FAD_lib only. (well and the testbenches)
File size: 30.6 KB
Line 
1DocumentHdrVersion "1.1"
2Header (DocumentHdr
3version 2
4dmPackageRefs [
5(DmPackageRef
6library "ieee"
7unitName "std_logic_1164"
8)
9(DmPackageRef
10library "ieee"
11unitName "std_logic_arith"
12)
13]
14libraryRefs [
15"ieee"
16]
17)
18version "24.1"
19appVersion "2009.1 (Build 12)"
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37)
38*6 (RowExpandColHdr
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40)
41*7 (GroupColHdr
42tm "GroupColHdrMgr"
43)
44*8 (NameColHdr
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46)
47*9 (ModeColHdr
48tm "ModeColHdrMgr"
49)
50*10 (TypeColHdr
51tm "TypeColHdrMgr"
52)
53*11 (BoundsColHdr
54tm "BoundsColHdrMgr"
55)
56*12 (InitColHdr
57tm "InitColHdrMgr"
58)
59*13 (EolColHdr
60tm "EolColHdrMgr"
61)
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71)
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490fixedCol 4
491fixedRow 2
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528*70 (InitColHdr
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531*71 (PragmaColHdr
532tm "GenericPragmaColHdrMgr"
533)
534*72 (EolColHdr
535tm "GenericEolColHdrMgr"
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642fixedCol 3
643fixedRow 2
644name "Ports"
645uid 95,0
646vaOverrides [
647]
648)
649]
650)
651uid 81,0
652type 1
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654VExpander (VariableExpander
655vvMap [
656(vvPair
657variable "HDLDir"
658value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl"
659)
660(vvPair
661variable "HDSDir"
662value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds"
663)
664(vvPair
665variable "SideDataDesignDir"
666value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.info"
667)
668(vvPair
669variable "SideDataUserDir"
670value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.user"
671)
672(vvPair
673variable "SourceDir"
674value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds"
675)
676(vvPair
677variable "appl"
678value "HDL Designer"
679)
680(vvPair
681variable "arch_name"
682value "symbol"
683)
684(vvPair
685variable "config"
686value "%(unit)_%(view)_config"
687)
688(vvPair
689variable "d"
690value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"
691)
692(vvPair
693variable "d_logical"
694value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"
695)
696(vvPair
697variable "date"
698value "13.04.2010"
699)
700(vvPair
701variable "day"
702value "Di"
703)
704(vvPair
705variable "day_long"
706value "Dienstag"
707)
708(vvPair
709variable "dd"
710value "13"
711)
712(vvPair
713variable "entity_name"
714value "FAD_main"
715)
716(vvPair
717variable "ext"
718value "<TBD>"
719)
720(vvPair
721variable "f"
722value "symbol.sb"
723)
724(vvPair
725variable "f_logical"
726value "symbol.sb"
727)
728(vvPair
729variable "f_noext"
730value "symbol"
731)
732(vvPair
733variable "group"
734value "UNKNOWN"
735)
736(vvPair
737variable "host"
738value "E5PCXX"
739)
740(vvPair
741variable "language"
742value "VHDL"
743)
744(vvPair
745variable "library"
746value "FACT_FAD_lib"
747)
748(vvPair
749variable "library_downstream_HdsLintPlugin"
750value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
751)
752(vvPair
753variable "library_downstream_ISEPARInvoke"
754value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
755)
756(vvPair
757variable "library_downstream_ImpactInvoke"
758value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
759)
760(vvPair
761variable "library_downstream_ModelSimCompiler"
762value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
763)
764(vvPair
765variable "library_downstream_PrecisionSynthesisDataPrep"
766value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
767)
768(vvPair
769variable "library_downstream_XSTDataPrep"
770value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
771)
772(vvPair
773variable "mm"
774value "04"
775)
776(vvPair
777variable "module_name"
778value "FAD_main"
779)
780(vvPair
781variable "month"
782value "Apr"
783)
784(vvPair
785variable "month_long"
786value "April"
787)
788(vvPair
789variable "p"
790value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb"
791)
792(vvPair
793variable "p_logical"
794value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb"
795)
796(vvPair
797variable "package_name"
798value "<Undefined Variable>"
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800(vvPair
801variable "project_name"
802value "FACT_FAD"
803)
804(vvPair
805variable "series"
806value "HDL Designer Series"
807)
808(vvPair
809variable "task_DesignCompilerPath"
810value "<TBD>"
811)
812(vvPair
813variable "task_LeonardoPath"
814value "$HDS_HOME/../Exemplar/bin/win32"
815)
816(vvPair
817variable "task_ModelSimPath"
818value "D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32"
819)
820(vvPair
821variable "task_NC-SimPath"
822value "<TBD>"
823)
824(vvPair
825variable "task_PrecisionRTLPath"
826value "$HDS_HOME/../Precision/Mgc_home/bin"
827)
828(vvPair
829variable "task_QuestaSimPath"
830value "<TBD>"
831)
832(vvPair
833variable "task_VCSPath"
834value "<TBD>"
835)
836(vvPair
837variable "this_ext"
838value "sb"
839)
840(vvPair
841variable "this_file"
842value "symbol"
843)
844(vvPair
845variable "this_file_logical"
846value "symbol"
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848(vvPair
849variable "time"
850value "15:16:53"
851)
852(vvPair
853variable "unit"
854value "FAD_main"
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856(vvPair
857variable "user"
858value "kai"
859)
860(vvPair
861variable "version"
862value "2009.1 (Build 12)"
863)
864(vvPair
865variable "view"
866value "symbol"
867)
868(vvPair
869variable "year"
870value "2010"
871)
872(vvPair
873variable "yy"
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875)
876]
877)
878LanguageMgr "VhdlLangMgr"
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1017o 6
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1052font "Courier New,8,0"
1053)
1054xt "44000,9200,77000,10000"
1055st "adc_oeb : OUT std_logic := '1' ;"
1056)
1057thePort (LogicalPort
1058m 1
1059decl (Decl
1060n "adc_oeb"
1061t "std_logic"
1062o 10
1063suid 21,0
1064i "'1'"
1065)
1066)
1067)
1068*90 (CptPort
1069uid 923,0
1070ps "OnEdgeStrategy"
1071shape (Triangle
1072uid 924,0
1073ro 90
1074va (VaSet
1075vasetType 1
1076fg "0,65535,0"
1077)
1078xt "14250,16625,15000,17375"
1079)
1080tg (CPTG
1081uid 925,0
1082ps "CptPortTextPlaceStrategy"
1083stg "VerticalLayoutStrategy"
1084f (Text
1085uid 926,0
1086va (VaSet
1087)
1088xt "16000,16500,21900,17500"
1089st "board_id : (3:0)"
1090blo "16000,17300"
1091tm "CptPortNameMgr"
1092)
1093)
1094dt (MLText
1095uid 927,0
1096va (VaSet
1097font "Courier New,8,0"
1098)
1099xt "44000,4400,73500,5200"
1100st "board_id : IN std_logic_vector (3 downto 0) ;"
1101)
1102thePort (LogicalPort
1103decl (Decl
1104n "board_id"
1105t "std_logic_vector"
1106b "(3 downto 0)"
1107preAdd 0
1108posAdd 0
1109o 4
1110suid 24,0
1111)
1112)
1113)
1114*91 (CptPort
1115uid 928,0
1116ps "OnEdgeStrategy"
1117shape (Triangle
1118uid 929,0
1119ro 90
1120va (VaSet
1121vasetType 1
1122fg "0,65535,0"
1123)
1124xt "14250,17625,15000,18375"
1125)
1126tg (CPTG
1127uid 930,0
1128ps "CptPortTextPlaceStrategy"
1129stg "VerticalLayoutStrategy"
1130f (Text
1131uid 931,0
1132va (VaSet
1133)
1134xt "16000,17500,21700,18500"
1135st "crate_id : (1:0)"
1136blo "16000,18300"
1137tm "CptPortNameMgr"
1138)
1139)
1140dt (MLText
1141uid 932,0
1142va (VaSet
1143font "Courier New,8,0"
1144)
1145xt "44000,5200,73500,6000"
1146st "crate_id : IN std_logic_vector (1 downto 0) ;"
1147)
1148thePort (LogicalPort
1149decl (Decl
1150n "crate_id"
1151t "std_logic_vector"
1152b "(1 downto 0)"
1153o 5
1154suid 25,0
1155)
1156)
1157)
1158*92 (CptPort
1159uid 1037,0
1160ps "OnEdgeStrategy"
1161shape (Triangle
1162uid 1038,0
1163ro 90
1164va (VaSet
1165vasetType 1
1166fg "0,65535,0"
1167)
1168xt "43000,26625,43750,27375"
1169)
1170tg (CPTG
1171uid 1039,0
1172ps "CptPortTextPlaceStrategy"
1173stg "RightVerticalLayoutStrategy"
1174f (Text
1175uid 1040,0
1176va (VaSet
1177)
1178xt "36000,26500,42000,27500"
1179st "wiz_addr : (9:0)"
1180ju 2
1181blo "42000,27300"
1182tm "CptPortNameMgr"
1183)
1184)
1185dt (MLText
1186uid 1041,0
1187va (VaSet
1188font "Courier New,8,0"
1189)
1190xt "44000,10800,73500,11600"
1191st "wiz_addr : OUT std_logic_vector (9 DOWNTO 0) ;"
1192)
1193thePort (LogicalPort
1194m 1
1195decl (Decl
1196n "wiz_addr"
1197t "std_logic_vector"
1198b "(9 DOWNTO 0)"
1199o 12
1200suid 26,0
1201)
1202)
1203)
1204*93 (CptPort
1205uid 1042,0
1206ps "OnEdgeStrategy"
1207shape (Diamond
1208uid 1043,0
1209ro 90
1210va (VaSet
1211vasetType 1
1212fg "0,65535,0"
1213)
1214xt "43000,27625,43750,28375"
1215)
1216tg (CPTG
1217uid 1044,0
1218ps "CptPortTextPlaceStrategy"
1219stg "RightVerticalLayoutStrategy"
1220f (Text
1221uid 1045,0
1222va (VaSet
1223)
1224xt "35700,27500,42000,28500"
1225st "wiz_data : (15:0)"
1226ju 2
1227blo "42000,28300"
1228tm "CptPortNameMgr"
1229)
1230)
1231dt (MLText
1232uid 1046,0
1233va (VaSet
1234font "Courier New,8,0"
1235)
1236xt "44000,14800,73000,15600"
1237st "wiz_data : INOUT std_logic_vector (15 DOWNTO 0)"
1238)
1239thePort (LogicalPort
1240m 2
1241decl (Decl
1242n "wiz_data"
1243t "std_logic_vector"
1244b "(15 DOWNTO 0)"
1245o 17
1246suid 27,0
1247)
1248)
1249)
1250*94 (CptPort
1251uid 1047,0
1252ps "OnEdgeStrategy"
1253shape (Triangle
1254uid 1048,0
1255ro 90
1256va (VaSet
1257vasetType 1
1258fg "0,65535,0"
1259)
1260xt "43000,28625,43750,29375"
1261)
1262tg (CPTG
1263uid 1049,0
1264ps "CptPortTextPlaceStrategy"
1265stg "RightVerticalLayoutStrategy"
1266f (Text
1267uid 1050,0
1268va (VaSet
1269)
1270xt "39300,28500,42000,29500"
1271st "wiz_cs"
1272ju 2
1273blo "42000,29300"
1274tm "CptPortNameMgr"
1275)
1276)
1277dt (MLText
1278uid 1051,0
1279va (VaSet
1280font "Courier New,8,0"
1281)
1282xt "44000,11600,77000,12400"
1283st "wiz_cs : OUT std_logic := '1' ;"
1284)
1285thePort (LogicalPort
1286m 1
1287decl (Decl
1288n "wiz_cs"
1289t "std_logic"
1290o 13
1291suid 28,0
1292i "'1'"
1293)
1294)
1295)
1296*95 (CptPort
1297uid 1052,0
1298ps "OnEdgeStrategy"
1299shape (Triangle
1300uid 1053,0
1301ro 90
1302va (VaSet
1303vasetType 1
1304fg "0,65535,0"
1305)
1306xt "43000,29625,43750,30375"
1307)
1308tg (CPTG
1309uid 1054,0
1310ps "CptPortTextPlaceStrategy"
1311stg "RightVerticalLayoutStrategy"
1312f (Text
1313uid 1055,0
1314va (VaSet
1315)
1316xt "39300,29500,42000,30500"
1317st "wiz_wr"
1318ju 2
1319blo "42000,30300"
1320tm "CptPortNameMgr"
1321)
1322)
1323dt (MLText
1324uid 1056,0
1325va (VaSet
1326font "Courier New,8,0"
1327)
1328xt "44000,14000,77000,14800"
1329st "wiz_wr : OUT std_logic := '1' ;"
1330)
1331thePort (LogicalPort
1332m 1
1333decl (Decl
1334n "wiz_wr"
1335t "std_logic"
1336o 16
1337suid 29,0
1338i "'1'"
1339)
1340)
1341)
1342*96 (CptPort
1343uid 1057,0
1344ps "OnEdgeStrategy"
1345shape (Triangle
1346uid 1058,0
1347ro 90
1348va (VaSet
1349vasetType 1
1350fg "0,65535,0"
1351)
1352xt "43000,30625,43750,31375"
1353)
1354tg (CPTG
1355uid 1059,0
1356ps "CptPortTextPlaceStrategy"
1357stg "RightVerticalLayoutStrategy"
1358f (Text
1359uid 1060,0
1360va (VaSet
1361)
1362xt "39400,30500,42000,31500"
1363st "wiz_rd"
1364ju 2
1365blo "42000,31300"
1366tm "CptPortNameMgr"
1367)
1368)
1369dt (MLText
1370uid 1061,0
1371va (VaSet
1372font "Courier New,8,0"
1373)
1374xt "44000,12400,77000,13200"
1375st "wiz_rd : OUT std_logic := '1' ;"
1376)
1377thePort (LogicalPort
1378m 1
1379decl (Decl
1380n "wiz_rd"
1381t "std_logic"
1382o 14
1383suid 30,0
1384i "'1'"
1385)
1386)
1387)
1388*97 (CptPort
1389uid 1062,0
1390ps "OnEdgeStrategy"
1391shape (Triangle
1392uid 1063,0
1393ro 90
1394va (VaSet
1395vasetType 1
1396fg "0,65535,0"
1397)
1398xt "14250,18625,15000,19375"
1399)
1400tg (CPTG
1401uid 1064,0
1402ps "CptPortTextPlaceStrategy"
1403stg "VerticalLayoutStrategy"
1404f (Text
1405uid 1065,0
1406va (VaSet
1407)
1408xt "16000,18500,18700,19500"
1409st "wiz_int"
1410blo "16000,19300"
1411tm "CptPortNameMgr"
1412)
1413)
1414dt (MLText
1415uid 1066,0
1416va (VaSet
1417font "Courier New,8,0"
1418)
1419xt "44000,6800,63500,7600"
1420st "wiz_int : IN std_logic ;"
1421)
1422thePort (LogicalPort
1423decl (Decl
1424n "wiz_int"
1425t "std_logic"
1426o 7
1427suid 31,0
1428)
1429)
1430)
1431*98 (CptPort
1432uid 1389,0
1433ps "OnEdgeStrategy"
1434shape (Triangle
1435uid 1390,0
1436ro 90
1437va (VaSet
1438vasetType 1
1439fg "0,65535,0"
1440)
1441xt "43000,31625,43750,32375"
1442)
1443tg (CPTG
1444uid 1391,0
1445ps "CptPortTextPlaceStrategy"
1446stg "RightVerticalLayoutStrategy"
1447f (Text
1448uid 1392,0
1449va (VaSet
1450)
1451xt "37500,31500,42000,32500"
1452st "CLK_25_PS"
1453ju 2
1454blo "42000,32300"
1455tm "CptPortNameMgr"
1456)
1457)
1458dt (MLText
1459uid 1393,0
1460va (VaSet
1461font "Courier New,8,0"
1462)
1463xt "44000,7600,63500,8400"
1464st "CLK_25_PS : OUT std_logic ;"
1465)
1466thePort (LogicalPort
1467m 1
1468decl (Decl
1469n "CLK_25_PS"
1470t "std_logic"
1471o 8
1472suid 35,0
1473)
1474)
1475)
1476*99 (CptPort
1477uid 1725,0
1478ps "OnEdgeStrategy"
1479shape (Triangle
1480uid 1726,0
1481ro 90
1482va (VaSet
1483vasetType 1
1484fg "0,65535,0"
1485)
1486xt "43000,32625,43750,33375"
1487)
1488tg (CPTG
1489uid 1727,0
1490ps "CptPortTextPlaceStrategy"
1491stg "RightVerticalLayoutStrategy"
1492f (Text
1493uid 1728,0
1494va (VaSet
1495)
1496xt "38900,32500,42000,33500"
1497st "CLK_50"
1498ju 2
1499blo "42000,33300"
1500tm "CptPortNameMgr"
1501)
1502)
1503dt (MLText
1504uid 1729,0
1505va (VaSet
1506font "Courier New,8,0"
1507)
1508xt "44000,8400,63500,9200"
1509st "CLK_50 : OUT std_logic ;"
1510)
1511thePort (LogicalPort
1512m 1
1513decl (Decl
1514n "CLK_50"
1515t "std_logic"
1516preAdd 0
1517posAdd 0
1518o 9
1519suid 37,0
1520)
1521)
1522)
1523*100 (CptPort
1524uid 1755,0
1525ps "OnEdgeStrategy"
1526shape (Triangle
1527uid 1756,0
1528ro 90
1529va (VaSet
1530vasetType 1
1531fg "0,65535,0"
1532)
1533xt "14250,19625,15000,20375"
1534)
1535tg (CPTG
1536uid 1757,0
1537ps "CptPortTextPlaceStrategy"
1538stg "VerticalLayoutStrategy"
1539f (Text
1540uid 1758,0
1541va (VaSet
1542)
1543xt "16000,19500,17900,20500"
1544st "CLK"
1545blo "16000,20300"
1546tm "CptPortNameMgr"
1547)
1548)
1549dt (MLText
1550uid 1759,0
1551va (VaSet
1552font "Courier New,8,0"
1553)
1554xt "44000,2000,63500,2800"
1555st "CLK : IN std_logic ;"
1556)
1557thePort (LogicalPort
1558decl (Decl
1559n "CLK"
1560t "std_logic"
1561o 1
1562suid 38,0
1563)
1564)
1565)
1566*101 (CptPort
1567uid 1976,0
1568ps "OnEdgeStrategy"
1569shape (Triangle
1570uid 1977,0
1571ro 90
1572va (VaSet
1573vasetType 1
1574fg "0,65535,0"
1575)
1576xt "14250,21625,15000,22375"
1577)
1578tg (CPTG
1579uid 1978,0
1580ps "CptPortTextPlaceStrategy"
1581stg "VerticalLayoutStrategy"
1582f (Text
1583uid 1979,0
1584va (VaSet
1585)
1586xt "16000,21500,24000,22500"
1587st "adc_otr_array : (3:0)"
1588blo "16000,22300"
1589tm "CptPortNameMgr"
1590)
1591)
1592dt (MLText
1593uid 1980,0
1594va (VaSet
1595font "Courier New,8,0"
1596)
1597xt "44000,3600,73500,4400"
1598st "adc_otr_array : IN std_logic_vector (3 DOWNTO 0) ;"
1599)
1600thePort (LogicalPort
1601decl (Decl
1602n "adc_otr_array"
1603t "std_logic_vector"
1604b "(3 DOWNTO 0)"
1605o 3
1606suid 40,0
1607)
1608)
1609)
1610*102 (CptPort
1611uid 2282,0
1612ps "OnEdgeStrategy"
1613shape (Triangle
1614uid 2283,0
1615ro 90
1616va (VaSet
1617vasetType 1
1618fg "0,65535,0"
1619)
1620xt "14250,22625,15000,23375"
1621)
1622tg (CPTG
1623uid 2284,0
1624ps "CptPortTextPlaceStrategy"
1625stg "VerticalLayoutStrategy"
1626f (Text
1627uid 2285,0
1628va (VaSet
1629)
1630xt "16000,22500,21900,23500"
1631st "adc_data_array"
1632blo "16000,23300"
1633tm "CptPortNameMgr"
1634)
1635)
1636dt (MLText
1637uid 2286,0
1638va (VaSet
1639font "Courier New,8,0"
1640)
1641xt "44000,2800,69000,3600"
1642st "adc_data_array : IN adc_data_array_type ;"
1643)
1644thePort (LogicalPort
1645decl (Decl
1646n "adc_data_array"
1647t "adc_data_array_type"
1648o 2
1649suid 41,0
1650)
1651)
1652)
1653]
1654shape (Rectangle
1655uid 584,0
1656va (VaSet
1657vasetType 1
1658fg "0,65535,0"
1659lineColor "0,32896,0"
1660lineWidth 2
1661)
1662xt "15000,-1000,43000,34000"
1663)
1664oxt "15000,-1000,43000,26000"
1665biTextGroup (BiTextGroup
1666uid 10,0
1667ps "CenterOffsetStrategy"
1668stg "VerticalLayoutStrategy"
1669first (Text
1670uid 11,0
1671va (VaSet
1672font "Arial,8,1"
1673)
1674xt "22200,8000,28400,9000"
1675st "FACT_FAD_lib"
1676blo "22200,8800"
1677)
1678second (Text
1679uid 12,0
1680va (VaSet
1681font "Arial,8,1"
1682)
1683xt "22200,9000,26400,10000"
1684st "FAD_main"
1685blo "22200,9800"
1686)
1687)
1688gi *103 (GenericInterface
1689uid 13,0
1690ps "CenterOffsetStrategy"
1691matrix (Matrix
1692uid 14,0
1693text (MLText
1694uid 15,0
1695va (VaSet
1696font "Courier New,8,0"
1697)
1698xt "0,12000,11500,12800"
1699st "Generic Declarations"
1700)
1701header "Generic Declarations"
1702showHdrWhenContentsEmpty 1
1703)
1704elements [
1705]
1706)
1707portInstanceVisAsIs 1
1708portInstanceVis (PortSigDisplay
1709)
1710portVis (PortSigDisplay
1711)
1712)
1713*104 (Grouping
1714uid 16,0
1715optionalChildren [
1716*105 (CommentText
1717uid 18,0
1718shape (Rectangle
1719uid 19,0
1720sl 0
1721va (VaSet
1722vasetType 1
1723fg "65280,65280,46080"
1724)
1725xt "36000,48000,53000,49000"
1726)
1727oxt "18000,70000,35000,71000"
1728text (MLText
1729uid 20,0
1730va (VaSet
1731fg "0,0,32768"
1732bg "0,0,32768"
1733)
1734xt "36200,48000,44400,49000"
1735st "
1736by %user on %dd %month %year
1737"
1738tm "CommentText"
1739wrapOption 3
1740visibleHeight 1000
1741visibleWidth 17000
1742)
1743position 1
1744ignorePrefs 1
1745titleBlock 1
1746)
1747*106 (CommentText
1748uid 21,0
1749shape (Rectangle
1750uid 22,0
1751sl 0
1752va (VaSet
1753vasetType 1
1754fg "65280,65280,46080"
1755)
1756xt "53000,44000,57000,45000"
1757)
1758oxt "35000,66000,39000,67000"
1759text (MLText
1760uid 23,0
1761va (VaSet
1762fg "0,0,32768"
1763bg "0,0,32768"
1764)
1765xt "53200,44000,56200,45000"
1766st "
1767Project:
1768"
1769tm "CommentText"
1770wrapOption 3
1771visibleHeight 1000
1772visibleWidth 4000
1773)
1774position 1
1775ignorePrefs 1
1776titleBlock 1
1777)
1778*107 (CommentText
1779uid 24,0
1780shape (Rectangle
1781uid 25,0
1782sl 0
1783va (VaSet
1784vasetType 1
1785fg "65280,65280,46080"
1786)
1787xt "36000,46000,53000,47000"
1788)
1789oxt "18000,68000,35000,69000"
1790text (MLText
1791uid 26,0
1792va (VaSet
1793fg "0,0,32768"
1794bg "0,0,32768"
1795)
1796xt "36200,46000,46200,47000"
1797st "
1798<enter diagram title here>
1799"
1800tm "CommentText"
1801wrapOption 3
1802visibleHeight 1000
1803visibleWidth 17000
1804)
1805position 1
1806ignorePrefs 1
1807titleBlock 1
1808)
1809*108 (CommentText
1810uid 27,0
1811shape (Rectangle
1812uid 28,0
1813sl 0
1814va (VaSet
1815vasetType 1
1816fg "65280,65280,46080"
1817)
1818xt "32000,46000,36000,47000"
1819)
1820oxt "14000,68000,18000,69000"
1821text (MLText
1822uid 29,0
1823va (VaSet
1824fg "0,0,32768"
1825bg "0,0,32768"
1826)
1827xt "32200,46000,34300,47000"
1828st "
1829Title:
1830"
1831tm "CommentText"
1832wrapOption 3
1833visibleHeight 1000
1834visibleWidth 4000
1835)
1836position 1
1837ignorePrefs 1
1838titleBlock 1
1839)
1840*109 (CommentText
1841uid 30,0
1842shape (Rectangle
1843uid 31,0
1844sl 0
1845va (VaSet
1846vasetType 1
1847fg "65280,65280,46080"
1848)
1849xt "53000,45000,73000,49000"
1850)
1851oxt "35000,67000,55000,71000"
1852text (MLText
1853uid 32,0
1854va (VaSet
1855fg "0,0,32768"
1856bg "0,0,32768"
1857)
1858xt "53200,45200,62400,46200"
1859st "
1860<enter comments here>
1861"
1862tm "CommentText"
1863wrapOption 3
1864visibleHeight 4000
1865visibleWidth 20000
1866)
1867ignorePrefs 1
1868titleBlock 1
1869)
1870*110 (CommentText
1871uid 33,0
1872shape (Rectangle
1873uid 34,0
1874sl 0
1875va (VaSet
1876vasetType 1
1877fg "65280,65280,46080"
1878)
1879xt "57000,44000,73000,45000"
1880)
1881oxt "39000,66000,55000,67000"
1882text (MLText
1883uid 35,0
1884va (VaSet
1885fg "0,0,32768"
1886bg "0,0,32768"
1887)
1888xt "57200,44000,61700,45000"
1889st "
1890%project_name
1891"
1892tm "CommentText"
1893wrapOption 3
1894visibleHeight 1000
1895visibleWidth 16000
1896)
1897position 1
1898ignorePrefs 1
1899titleBlock 1
1900)
1901*111 (CommentText
1902uid 36,0
1903shape (Rectangle
1904uid 37,0
1905sl 0
1906va (VaSet
1907vasetType 1
1908fg "65280,65280,46080"
1909)
1910xt "32000,44000,53000,46000"
1911)
1912oxt "14000,66000,35000,68000"
1913text (MLText
1914uid 38,0
1915va (VaSet
1916fg "32768,0,0"
1917)
1918xt "39150,44500,45850,45500"
1919st "
1920<company name>
1921"
1922ju 0
1923tm "CommentText"
1924wrapOption 3
1925visibleHeight 2000
1926visibleWidth 21000
1927)
1928position 1
1929ignorePrefs 1
1930titleBlock 1
1931)
1932*112 (CommentText
1933uid 39,0
1934shape (Rectangle
1935uid 40,0
1936sl 0
1937va (VaSet
1938vasetType 1
1939fg "65280,65280,46080"
1940)
1941xt "32000,47000,36000,48000"
1942)
1943oxt "14000,69000,18000,70000"
1944text (MLText
1945uid 41,0
1946va (VaSet
1947fg "0,0,32768"
1948bg "0,0,32768"
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