source: firmware/FAD/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb@ 18260

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
)
]
libraryRefs [
"ieee"
"FACT_FAD_lib"
]
)
version "24.1"
appVersion "2009.1 (Build 12)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 111,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 53,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 50
suid 2,0
i "'1'"
)
)
uid 111,0
)
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 7,0
i "(OTHERS => '0')"
)
)
uid 121,0
)
*16 (LogPort
port (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 18,0
)
)
uid 453,0
)
*17 (LogPort
port (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 21,0
i "'1'"
)
)
uid 825,0
)
*18 (LogPort
port (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 24,0
)
)
uid 920,0
)
*19 (LogPort
port (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 25,0
)
)
uid 922,0
)
*20 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 47
suid 26,0
)
)
uid 1026,0
)
*21 (LogPort
port (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 53
suid 27,0
)
)
uid 1028,0
)
*22 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 48
suid 28,0
i "'1'"
)
)
uid 1030,0
)
*23 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 51
suid 29,0
i "'1'"
)
)
uid 1032,0
)
*24 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 49
suid 30,0
i "'1'"
)
)
uid 1034,0
)
*25 (LogPort
port (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 31,0
)
)
uid 1036,0
)
*26 (LogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 35,0
)
)
uid 1388,0
)
*27 (LogPort
port (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 37,0
)
)
uid 1724,0
)
*28 (LogPort
port (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
uid 1754,0
)
*29 (LogPort
port (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 40,0
)
)
uid 1975,0
)
*30 (LogPort
port (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 41,0
)
)
uid 2281,0
)
*31 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 48,0
i "(others => '0')"
)
)
uid 2415,0
)
*32 (LogPort
port (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 49,0
i "'1'"
)
)
uid 2417,0
)
*33 (LogPort
port (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 52,0
)
)
uid 2693,0
)
*34 (LogPort
port (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 53,0
)
)
uid 2695,0
)
*35 (LogPort
port (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 54,0
)
)
uid 2697,0
)
*36 (LogPort
port (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 55,0
)
)
uid 2699,0
)
*37 (LogPort
port (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 56,0
i "'0'"
)
)
uid 2984,0
)
*38 (LogPort
port (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 57,0
i "'0'"
)
)
uid 2986,0
)
*39 (LogPort
port (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 62,0
)
)
uid 3624,0
)
*40 (LogPort
port (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 63,0
)
)
uid 3626,0
)
*41 (LogPort
port (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 64,0
)
)
uid 3628,0
)
*42 (LogPort
port (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 65,0
)
)
uid 3630,0
)
*43 (LogPort
port (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 66,0
i "'0'"
)
)
uid 4066,0
)
*44 (LogPort
port (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 67,0
i "'0'"
)
)
uid 4143,0
)
*45 (LogPort
port (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 85,0
i "'0'"
)
)
uid 4779,0
)
*46 (LogPort
port (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 86,0
)
)
uid 4901,0
)
*47 (LogPort
port (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 87,0
)
)
uid 4903,0
)
*48 (LogPort
port (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 88,0
)
)
uid 4905,0
)
*49 (LogPort
port (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 91,0
)
)
uid 5327,0
)
*50 (LogPort
port (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 92,0
)
)
uid 5426,0
)
*51 (LogPort
port (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 93,0
)
)
uid 5502,0
)
*52 (LogPort
port (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 94,0
)
)
uid 5624,0
)
*53 (LogPort
port (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 95,0
)
)
uid 5626,0
)
*54 (LogPort
port (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 96,0
)
)
uid 5628,0
)
*55 (LogPort
port (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 97,0
)
)
uid 6703,0
)
*56 (LogPort
port (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 98,0
i "'1'"
)
)
uid 7538,0
)
*57 (LogPort
port (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 99,0
)
)
uid 7614,0
)
*58 (LogPort
port (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 100,0
)
)
uid 7616,0
)
*59 (LogPort
port (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 101,0
)
)
uid 7618,0
)
*60 (LogPort
port (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 102,0
)
)
uid 7620,0
)
*61 (LogPort
port (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 103,0
)
)
uid 7849,0
)
*62 (LogPort
port (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 104,0
)
)
uid 7879,0
)
*63 (LogPort
port (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 105,0
)
)
uid 7881,0
)
*64 (LogPort
port (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 106,0
)
)
uid 7962,0
)
*65 (LogPort
port (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 108,0
)
)
uid 8022,0
)
*66 (LogPort
port (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 109,0
)
)
uid 8282,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 66,0
optionalChildren [
*67 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *68 (MRCItem
litem &1
pos 17
dimension 20
)
uid 68,0
optionalChildren [
*69 (MRCItem
litem &2
pos 0
dimension 20
uid 69,0
)
*70 (MRCItem
litem &3
pos 1
dimension 23
uid 70,0
)
*71 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 71,0
)
*72 (MRCItem
litem &14
pos 0
dimension 20
uid 110,0
)
*73 (MRCItem
litem &15
pos 24
dimension 20
uid 120,0
)
*74 (MRCItem
litem &16
pos 7
dimension 20
uid 452,0
)
*75 (MRCItem
litem &17
pos 10
dimension 20
uid 824,0
)
*76 (MRCItem
litem &18
pos 8
dimension 20
uid 919,0
)
*77 (MRCItem
litem &19
pos 9
dimension 20
uid 921,0
)
*78 (MRCItem
litem &20
pos 1
dimension 20
uid 1025,0
)
*79 (MRCItem
litem &21
pos 2
dimension 20
uid 1027,0
)
*80 (MRCItem
litem &22
pos 3
dimension 20
uid 1029,0
)
*81 (MRCItem
litem &23
pos 4
dimension 20
uid 1031,0
)
*82 (MRCItem
litem &24
pos 5
dimension 20
uid 1033,0
)
*83 (MRCItem
litem &25
pos 6
dimension 20
uid 1035,0
)
*84 (MRCItem
litem &26
pos 11
dimension 20
uid 1387,0
)
*85 (MRCItem
litem &27
pos 12
dimension 20
uid 1723,0
)
*86 (MRCItem
litem &28
pos 13
dimension 20
uid 1753,0
)
*87 (MRCItem
litem &29
pos 14
dimension 20
uid 1974,0
)
*88 (MRCItem
litem &30
pos 15
dimension 20
uid 2280,0
)
*89 (MRCItem
litem &31
pos 16
dimension 20
uid 2414,0
)
*90 (MRCItem
litem &32
pos 17
dimension 20
uid 2416,0
)
*91 (MRCItem
litem &33
pos 18
dimension 20
uid 2692,0
)
*92 (MRCItem
litem &34
pos 19
dimension 20
uid 2694,0
)
*93 (MRCItem
litem &35
pos 20
dimension 20
uid 2696,0
)
*94 (MRCItem
litem &36
pos 21
dimension 20
uid 2698,0
)
*95 (MRCItem
litem &37
pos 22
dimension 20
uid 2983,0
)
*96 (MRCItem
litem &38
pos 23
dimension 20
uid 2985,0
)
*97 (MRCItem
litem &39
pos 25
dimension 20
uid 3623,0
)
*98 (MRCItem
litem &40
pos 26
dimension 20
uid 3625,0
)
*99 (MRCItem
litem &41
pos 27
dimension 20
uid 3627,0
)
*100 (MRCItem
litem &42
pos 28
dimension 20
uid 3629,0
)
*101 (MRCItem
litem &43
pos 29
dimension 20
uid 4065,0
)
*102 (MRCItem
litem &44
pos 30
dimension 20
uid 4142,0
)
*103 (MRCItem
litem &45
pos 31
dimension 20
uid 4778,0
)
*104 (MRCItem
litem &46
pos 32
dimension 20
uid 4900,0
)
*105 (MRCItem
litem &47
pos 33
dimension 20
uid 4902,0
)
*106 (MRCItem
litem &48
pos 34
dimension 20
uid 4904,0
)
*107 (MRCItem
litem &49
pos 35
dimension 20
uid 5326,0
)
*108 (MRCItem
litem &50
pos 36
dimension 20
uid 5425,0
)
*109 (MRCItem
litem &51
pos 37
dimension 20
uid 5501,0
)
*110 (MRCItem
litem &52
pos 40
dimension 20
uid 5623,0
)
*111 (MRCItem
litem &53
pos 38
dimension 20
uid 5625,0
)
*112 (MRCItem
litem &54
pos 39
dimension 20
uid 5627,0
)
*113 (MRCItem
litem &55
pos 41
dimension 20
uid 6702,0
)
*114 (MRCItem
litem &56
pos 42
dimension 20
uid 7537,0
)
*115 (MRCItem
litem &57
pos 43
dimension 20
uid 7613,0
)
*116 (MRCItem
litem &58
pos 44
dimension 20
uid 7615,0
)
*117 (MRCItem
litem &59
pos 45
dimension 20
uid 7617,0
)
*118 (MRCItem
litem &60
pos 46
dimension 20
uid 7619,0
)
*119 (MRCItem
litem &61
pos 47
dimension 20
uid 7848,0
)
*120 (MRCItem
litem &62
pos 48
dimension 20
uid 7878,0
)
*121 (MRCItem
litem &63
pos 49
dimension 20
uid 7880,0
)
*122 (MRCItem
litem &64
pos 50
dimension 20
uid 7961,0
)
*123 (MRCItem
litem &65
pos 51
dimension 20
uid 8021,0
)
*124 (MRCItem
litem &66
pos 52
dimension 20
uid 8281,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 72,0
optionalChildren [
*125 (MRCItem
litem &5
pos 0
dimension 20
uid 73,0
)
*126 (MRCItem
litem &7
pos 1
dimension 50
uid 74,0
)
*127 (MRCItem
litem &8
pos 2
dimension 100
uid 75,0
)
*128 (MRCItem
litem &9
pos 3
dimension 50
uid 76,0
)
*129 (MRCItem
litem &10
pos 4
dimension 100
uid 77,0
)
*130 (MRCItem
litem &11
pos 5
dimension 100
uid 78,0
)
*131 (MRCItem
litem &12
pos 6
dimension 50
uid 79,0
)
*132 (MRCItem
litem &13
pos 7
dimension 80
uid 80,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 67,0
vaOverrides [
]
)
]
)
uid 52,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *133 (LEmptyRow
)
uid 82,0
optionalChildren [
*134 (RefLabelRowHdr
)
*135 (TitleRowHdr
)
*136 (FilterRowHdr
)
*137 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*138 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*139 (GroupColHdr
tm "GroupColHdrMgr"
)
*140 (NameColHdr
tm "GenericNameColHdrMgr"
)
*141 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*142 (InitColHdr
tm "GenericValueColHdrMgr"
)
*143 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*144 (EolColHdr
tm "GenericEolColHdrMgr"
)
*145 (LogGeneric
generic (GiElement
name "RAMADDRWIDTH64b"
type "integer"
value "12"
)
uid 4249,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 94,0
optionalChildren [
*146 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *147 (MRCItem
litem &133
pos 0
dimension 20
)
uid 96,0
optionalChildren [
*148 (MRCItem
litem &134
pos 0
dimension 20
uid 97,0
)
*149 (MRCItem
litem &135
pos 1
dimension 23
uid 98,0
)
*150 (MRCItem
litem &136
pos 2
hidden 1
dimension 20
uid 99,0
)
*151 (MRCItem
litem &145
pos 0
dimension 20
uid 4248,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 100,0
optionalChildren [
*152 (MRCItem
litem &137
pos 0
dimension 20
uid 101,0
)
*153 (MRCItem
litem &139
pos 1
dimension 50
uid 102,0
)
*154 (MRCItem
litem &140
pos 2
dimension 100
uid 103,0
)
*155 (MRCItem
litem &141
pos 3
dimension 100
uid 104,0
)
*156 (MRCItem
litem &142
pos 4
dimension 50
uid 105,0
)
*157 (MRCItem
litem &143
pos 5
dimension 50
uid 106,0
)
*158 (MRCItem
litem &144
pos 6
dimension 80
uid 107,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 95,0
vaOverrides [
]
)
]
)
uid 81,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main"
)
(vvPair
variable "d_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main"
)
(vvPair
variable "date"
value "09.06.2011"
)
(vvPair
variable "day"
value "Do"
)
(vvPair
variable "day_long"
value "Donnerstag"
)
(vvPair
variable "dd"
value "09"
)
(vvPair
variable "entity_name"
value "FAD_main"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "IHP110"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "06"
)
(vvPair
variable "module_name"
value "FAD_main"
)
(vvPair
variable "month"
value "Jun"
)
(vvPair
variable "month_long"
value "Juni"
)
(vvPair
variable "p"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@a@d_main\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FAD_main\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "D:\\modeltech_6.5e\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "16:55:25"
)
(vvPair
variable "unit"
value "FAD_main"
)
(vvPair
variable "user"
value "daqct3"
)
(vvPair
variable "version"
value "2009.1 (Build 12)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 51,0
optionalChildren [
*159 (SymbolBody
uid 8,0
optionalChildren [
*160 (CptPort
uid 135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-3375,43750,-2625"
)
tg (CPTG
uid 137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 138,0
va (VaSet
)
xt "37800,-3500,42000,-2500"
st "wiz_reset"
ju 2
blo "42000,-2700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 140,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,42000,80500,42800"
st "wiz_reset             : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
o 50
suid 2,0
i "'1'"
)
)
)
*161 (CptPort
uid 163,0
ps "OnEdgeStrategy"
shape (Triangle
uid 164,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,42625,43750,43375"
)
tg (CPTG
uid 165,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 166,0
va (VaSet
)
xt "37600,42500,42000,43500"
st "led : (7:0)"
ju 2
blo "42000,43300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 168,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,32400,86500,33200"
st "led                   : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 38
suid 7,0
i "(OTHERS => '0')"
)
)
)
*162 (CptPort
uid 464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 465,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,4625,15000,5375"
)
tg (CPTG
uid 466,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 467,0
va (VaSet
)
xt "16000,4500,19000,5500"
st "trigger"
blo "16000,5300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 468,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12400,67500,13200"
st "trigger               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 18,0
)
)
)
*163 (CptPort
uid 833,0
ps "OnEdgeStrategy"
shape (Triangle
uid 834,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
tg (CPTG
uid 835,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 836,0
va (VaSet
)
xt "16000,15500,19500,16500"
st "adc_oeb"
blo "16000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 837,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,22800,80500,23600"
st "adc_oeb               : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 26
suid 21,0
i "'1'"
)
)
)
*164 (CptPort
uid 923,0
ps "OnEdgeStrategy"
shape (Triangle
uid 924,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
tg (CPTG
uid 925,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 926,0
va (VaSet
)
xt "16000,6500,22700,7500"
st "board_id : (3:0)"
blo "16000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 927,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,77000,10000"
st "board_id              : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 24,0
)
)
)
*165 (CptPort
uid 928,0
ps "OnEdgeStrategy"
shape (Triangle
uid 929,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
tg (CPTG
uid 930,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 931,0
va (VaSet
)
xt "16000,7500,22400,8500"
st "crate_id : (1:0)"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 932,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,77000,10800"
st "crate_id              : IN     std_logic_vector (1 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 11
suid 25,0
)
)
)
*166 (CptPort
uid 1037,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1038,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-6375,43750,-5625"
)
tg (CPTG
uid 1039,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1040,0
va (VaSet
)
xt "35100,-6500,42000,-5500"
st "wiz_addr : (9:0)"
ju 2
blo "42000,-5700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1041,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,39600,77000,40400"
st "wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 47
suid 26,0
)
)
)
*167 (CptPort
uid 1042,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1043,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-5375,43750,-4625"
)
tg (CPTG
uid 1044,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1045,0
va (VaSet
)
xt "34800,-5500,42000,-4500"
st "wiz_data : (15:0)"
ju 2
blo "42000,-4700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1046,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,44400,76500,45200"
st "wiz_data              : INOUT  std_logic_vector (15 DOWNTO 0)
"
)
thePort (LogicalPort
m 2
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 53
suid 27,0
)
)
)
*168 (CptPort
uid 1047,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1048,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,625,43750,1375"
)
tg (CPTG
uid 1049,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1050,0
va (VaSet
)
xt "39000,500,42000,1500"
st "wiz_cs"
ju 2
blo "42000,1300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1051,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,40400,80500,41200"
st "wiz_cs                : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_cs"
t "std_logic"
o 48
suid 28,0
i "'1'"
)
)
)
*169 (CptPort
uid 1052,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1053,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-1375,43750,-625"
)
tg (CPTG
uid 1054,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1055,0
va (VaSet
)
xt "38800,-1500,42000,-500"
st "wiz_wr"
ju 2
blo "42000,-700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1056,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,42800,80500,43600"
st "wiz_wr                : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_wr"
t "std_logic"
o 51
suid 29,0
i "'1'"
)
)
)
*170 (CptPort
uid 1057,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1058,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-2375,43750,-1625"
)
tg (CPTG
uid 1059,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1060,0
va (VaSet
)
xt "38900,-2500,42000,-1500"
st "wiz_rd"
ju 2
blo "42000,-1700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1061,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,41200,80500,42000"
st "wiz_rd                : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_rd"
t "std_logic"
o 49
suid 30,0
i "'1'"
)
)
)
*171 (CptPort
uid 1062,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1063,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,-375,43750,375"
)
tg (CPTG
uid 1064,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1065,0
va (VaSet
)
xt "38800,-500,42000,500"
st "wiz_int"
ju 2
blo "42000,300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1066,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13200,67500,14000"
st "wiz_int               : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "wiz_int"
t "std_logic"
o 15
suid 31,0
)
)
)
*172 (CptPort
uid 1389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1390,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,-4375,15000,-3625"
)
tg (CPTG
uid 1391,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1392,0
va (VaSet
)
xt "16000,-4500,20800,-3500"
st "CLK_25_PS"
blo "16000,-3700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1393,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14800,67500,15600"
st "CLK_25_PS             : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 17
suid 35,0
)
)
)
*173 (CptPort
uid 1725,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1726,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,-5375,15000,-4625"
)
tg (CPTG
uid 1727,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1728,0
va (VaSet
)
xt "16000,-5500,19300,-4500"
st "CLK_50"
blo "16000,-4700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1729,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15600,67500,16400"
st "CLK_50                : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
preAdd 0
posAdd 0
o 18
suid 37,0
)
)
)
*174 (CptPort
uid 1755,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1756,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,-6375,15000,-5625"
)
tg (CPTG
uid 1757,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1758,0
va (VaSet
)
xt "16000,-6500,17900,-5500"
st "CLK"
blo "16000,-5700"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1759,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,67500,2800"
st "CLK                   : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 38,0
)
)
)
*175 (CptPort
uid 1976,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1977,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
tg (CPTG
uid 1978,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1979,0
va (VaSet
)
xt "16000,14500,25300,15500"
st "adc_otr_array : (3:0)"
blo "16000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1980,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,77000,9200"
st "adc_otr_array         : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 9
suid 40,0
)
)
)
*176 (CptPort
uid 2282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,20625,15000,21375"
)
tg (CPTG
uid 2284,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2285,0
va (VaSet
)
xt "16000,20500,22900,21500"
st "adc_data_array"
blo "16000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2286,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,72500,8400"
st "adc_data_array        : IN     adc_data_array_type  ;
"
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 8
suid 41,0
)
)
)
*177 (CptPort
uid 2448,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2449,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,34625,15000,35375"
)
tg (CPTG
uid 2450,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2451,0
va (VaSet
)
xt "16000,34500,25500,35500"
st "drs_channel_id : (3:0)"
blo "16000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2452,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,30000,86500,30800"
st "drs_channel_id        : OUT    std_logic_vector (3 downto 0) := (others => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 35
suid 48,0
i "(others => '0')"
)
)
)
*178 (CptPort
uid 2453,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2454,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,35625,15000,36375"
)
tg (CPTG
uid 2455,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2456,0
va (VaSet
)
xt "16000,35500,21200,36500"
st "drs_dwrite"
blo "16000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2457,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,30800,80500,31600"
st "drs_dwrite            : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 36
suid 49,0
i "'1'"
)
)
)
*179 (CptPort
uid 2710,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2711,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,30625,15000,31375"
)
tg (CPTG
uid 2712,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2713,0
va (VaSet
)
xt "16000,30500,21800,31500"
st "SROUT_in_0"
blo "16000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2714,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,67500,5200"
st "SROUT_in_0            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
suid 52,0
)
)
)
*180 (CptPort
uid 2715,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2716,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,31625,15000,32375"
)
tg (CPTG
uid 2717,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2718,0
va (VaSet
)
xt "16000,31500,21700,32500"
st "SROUT_in_1"
blo "16000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2719,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,67500,6000"
st "SROUT_in_1            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
suid 53,0
)
)
)
*181 (CptPort
uid 2720,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2721,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,32625,15000,33375"
)
tg (CPTG
uid 2722,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2723,0
va (VaSet
)
xt "16000,32500,21800,33500"
st "SROUT_in_2"
blo "16000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2724,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,67500,6800"
st "SROUT_in_2            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
suid 54,0
)
)
)
*182 (CptPort
uid 2725,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2726,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,33625,15000,34375"
)
tg (CPTG
uid 2727,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2728,0
va (VaSet
)
xt "16000,33500,21800,34500"
st "SROUT_in_3"
blo "16000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2729,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,67500,7600"
st "SROUT_in_3            : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
suid 55,0
)
)
)
*183 (CptPort
uid 2987,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2988,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,36625,15000,37375"
)
tg (CPTG
uid 2989,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2990,0
va (VaSet
)
xt "16000,36500,20200,37500"
st "RSRLOAD"
blo "16000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2991,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,20400,80500,21200"
st "RSRLOAD               : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 23
suid 56,0
i "'0'"
)
)
)
*184 (CptPort
uid 2992,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2993,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,38625,15000,39375"
)
tg (CPTG
uid 2994,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2995,0
va (VaSet
)
xt "16000,38500,18900,39500"
st "SRCLK"
blo "16000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2996,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,21200,80500,22000"
st "SRCLK                 : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 24
suid 57,0
i "'0'"
)
)
)
*185 (CptPort
uid 3631,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3632,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,23625,43750,24375"
)
tg (CPTG
uid 3633,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3634,0
va (VaSet
)
xt "40100,23500,42000,24500"
st "sclk"
ju 2
blo "42000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3635,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,35600,67500,36400"
st "sclk                  : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 42
suid 62,0
)
)
)
*186 (CptPort
uid 3636,0
ps "OnEdgeStrategy"
shape (Diamond
uid 3637,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,24625,43750,25375"
)
tg (CPTG
uid 3638,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3639,0
va (VaSet
)
xt "40600,24500,42000,25500"
st "sio"
ju 2
blo "42000,25300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3640,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,43600,67500,44400"
st "sio                   : INOUT  std_logic  ;
"
)
thePort (LogicalPort
m 2
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 52
suid 63,0
)
)
)
*187 (CptPort
uid 3641,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3642,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,12625,43750,13375"
)
tg (CPTG
uid 3643,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3644,0
va (VaSet
)
xt "39000,12500,42000,13500"
st "dac_cs"
ju 2
blo "42000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3645,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,26800,67500,27600"
st "dac_cs                : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 31
suid 64,0
)
)
)
*188 (CptPort
uid 3646,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3647,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,14625,43750,15375"
)
tg (CPTG
uid 3648,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3649,0
va (VaSet
)
xt "35000,14500,42000,15500"
st "sensor_cs : (3:0)"
ju 2
blo "42000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 3650,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,36400,77000,37200"
st "sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 43
suid 65,0
)
)
)
*189 (CptPort
uid 4067,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4068,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,25625,43750,26375"
)
tg (CPTG
uid 4069,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4070,0
va (VaSet
)
xt "40000,25500,42000,26500"
st "mosi"
ju 2
blo "42000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4071,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,34000,80500,34800"
st "mosi                  : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 40
suid 66,0
i "'0'"
)
)
)
*190 (CptPort
uid 4144,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4145,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,43625,43750,44375"
)
tg (CPTG
uid 4146,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4147,0
va (VaSet
)
xt "38800,43500,42000,44500"
st "denable"
ju 2
blo "42000,44300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4148,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,29200,94000,30000"
st "denable               : OUT    std_logic                     := '0' ; -- default domino wave off
"
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 34
suid 67,0
i "'0'"
)
)
)
*191 (CptPort
uid 4780,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4781,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,60625,43750,61375"
)
tg (CPTG
uid 4782,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4783,0
va (VaSet
)
xt "37800,60500,42000,61500"
st "SRIN_out"
ju 2
blo "42000,61300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4784,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,22000,80500,22800"
st "SRIN_out              : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "SRIN_out"
t "std_logic"
o 25
suid 85,0
i "'0'"
)
)
)
*192 (CptPort
uid 4906,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4907,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,61625,43750,62375"
)
tg (CPTG
uid 4908,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4909,0
va (VaSet
)
xt "39600,61500,42000,62500"
st "green"
ju 2
blo "42000,62300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4910,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,31600,67500,32400"
st "green                 : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "green"
t "std_logic"
o 37
suid 86,0
)
)
)
*193 (CptPort
uid 4911,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4912,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,62625,43750,63375"
)
tg (CPTG
uid 4913,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4914,0
va (VaSet
)
xt "39300,62500,42000,63500"
st "amber"
ju 2
blo "42000,63300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4915,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,25200,67500,26000"
st "amber                 : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "amber"
t "std_logic"
o 29
suid 87,0
)
)
)
*194 (CptPort
uid 4916,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4917,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,63625,43750,64375"
)
tg (CPTG
uid 4918,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4919,0
va (VaSet
)
xt "40300,63500,42000,64500"
st "red"
ju 2
blo "42000,64300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 4920,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,34800,67500,35600"
st "red                   : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "red"
t "std_logic"
o 41
suid 88,0
)
)
)
*195 (CptPort
uid 5328,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5329,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,39625,15000,40375"
)
tg (CPTG
uid 5330,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5331,0
va (VaSet
)
xt "16000,39500,21500,40500"
st "D_T_in : (1:0)"
blo "16000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 5332,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,77000,3600"
st "D_T_in                : IN     std_logic_vector (1 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "D_T_in"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 2
suid 91,0
)
)
)
*196 (CptPort
uid 5427,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5428,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,40625,15000,41375"
)
tg (CPTG
uid 5429,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5430,0
va (VaSet
)
xt "16000,40500,22100,41500"
st "drs_refclk_in"
blo "16000,41300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 5431,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,99000,11600"
st "drs_refclk_in         : IN     std_logic  ; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
"
)
thePort (LogicalPort
decl (Decl
n "drs_refclk_in"
t "std_logic"
eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
o 12
suid 92,0
)
)
)
*197 (CptPort
uid 5503,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5504,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,41625,15000,42375"
)
tg (CPTG
uid 5505,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5506,0
va (VaSet
)
xt "16000,41500,22700,42500"
st "plllock_in : (3:0)"
blo "16000,42300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 5507,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,106500,12400"
st "plllock_in            : IN     std_logic_vector (3 DOWNTO 0) ; -- high level, if dominowave is running and DRS PLL locked
"
)
thePort (LogicalPort
decl (Decl
n "plllock_in"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- high level, if dominowave is running and DRS PLL locked"
o 13
suid 93,0
)
)
)
*198 (CptPort
uid 5629,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5630,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,65625,43750,66375"
)
tg (CPTG
uid 5631,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5632,0
va (VaSet
)
xt "32400,65500,42000,66500"
st "counter_result : (11:0)"
ju 2
blo "42000,66300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 5633,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,26000,77500,26800"
st "counter_result        : OUT    std_logic_vector (11 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "counter_result"
t "std_logic_vector"
b "(11 DOWNTO 0)"
o 30
suid 94,0
)
)
)
*199 (CptPort
uid 5634,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5635,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,66625,43750,67375"
)
tg (CPTG
uid 5636,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5637,0
va (VaSet
)
xt "32000,66500,42000,67500"
st "alarm_refclk_too_high"
ju 2
blo "42000,67300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 5638,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,23600,67500,24400"
st "alarm_refclk_too_high : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_high"
t "std_logic"
o 27
suid 95,0
)
)
)
*200 (CptPort
uid 5639,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5640,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,67625,43750,68375"
)
tg (CPTG
uid 5641,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5642,0
va (VaSet
)
xt "32400,67500,42000,68500"
st "alarm_refclk_too_low"
ju 2
blo "42000,68300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 5643,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,24400,67500,25200"
st "alarm_refclk_too_low  : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "alarm_refclk_too_low"
t "std_logic"
posAdd 0
o 28
suid 96,0
)
)
)
*201 (CptPort
uid 6704,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6705,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,68625,43750,69375"
)
tg (CPTG
uid 6706,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6707,0
va (VaSet
)
xt "38000,68500,42000,69500"
st "ADC_CLK"
ju 2
blo "42000,69300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 6708,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14000,67500,14800"
st "ADC_CLK               : OUT    std_logic  ;
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ADC_CLK"
t "std_logic"
o 16
suid 97,0
)
)
)
*202 (CptPort
uid 7539,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7540,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,69625,43750,70375"
)
tg (CPTG
uid 7541,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7542,0
va (VaSet
)
xt "36400,69500,42000,70500"
st "trigger_veto"
ju 2
blo "42000,70300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7543,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,38000,80500,38800"
st "trigger_veto          : OUT    std_logic                     := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_veto"
t "std_logic"
o 45
suid 98,0
i "'1'"
)
)
)
*203 (CptPort
uid 7621,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7622,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,42625,15000,43375"
)
tg (CPTG
uid 7623,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7624,0
va (VaSet
)
xt "16000,42500,24100,43500"
st "FTM_RS485_rx_d"
blo "16000,43300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7625,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,67500,4400"
st "FTM_RS485_rx_d        : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "FTM_RS485_rx_d"
t "std_logic"
o 3
suid 99,0
)
)
)
*204 (CptPort
uid 7626,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7627,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,70625,43750,71375"
)
tg (CPTG
uid 7628,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7629,0
va (VaSet
)
xt "33900,70500,42000,71500"
st "FTM_RS485_tx_d"
ju 2
blo "42000,71300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7630,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18800,67500,19600"
st "FTM_RS485_tx_d        : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_d"
t "std_logic"
o 21
suid 100,0
)
)
)
*205 (CptPort
uid 7631,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7632,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,71625,43750,72375"
)
tg (CPTG
uid 7633,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7634,0
va (VaSet
)
xt "33600,71500,42000,72500"
st "FTM_RS485_rx_en"
ju 2
blo "42000,72300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7635,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18000,67500,18800"
st "FTM_RS485_rx_en       : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_rx_en"
t "std_logic"
o 20
suid 101,0
)
)
)
*206 (CptPort
uid 7636,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7637,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,72625,43750,73375"
)
tg (CPTG
uid 7638,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7639,0
va (VaSet
)
xt "33600,72500,42000,73500"
st "FTM_RS485_tx_en"
ju 2
blo "42000,73300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7640,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,19600,67500,20400"
st "FTM_RS485_tx_en       : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "FTM_RS485_tx_en"
t "std_logic"
o 22
suid 102,0
)
)
)
*207 (CptPort
uid 7850,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7851,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,73625,43750,74375"
)
tg (CPTG
uid 7852,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7853,0
va (VaSet
)
xt "33600,73500,42000,74500"
st "w5300_state : (7:0)"
ju 2
blo "42000,74300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7854,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,38800,102500,39600"
st "w5300_state           : OUT    std_logic_vector (7 DOWNTO 0) ; -- state is encoded here ... useful for debugging.
"
)
thePort (LogicalPort
m 1
decl (Decl
n "w5300_state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 46
suid 103,0
)
)
)
*208 (CptPort
uid 7882,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7883,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,74625,43750,75375"
)
tg (CPTG
uid 7884,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7885,0
va (VaSet
)
xt "31600,74500,42000,75500"
st "debug_data_ram_empty"
ju 2
blo "42000,75300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7886,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,27600,67500,28400"
st "debug_data_ram_empty  : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 32
suid 104,0
)
)
)
*209 (CptPort
uid 7887,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7888,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,75625,43750,76375"
)
tg (CPTG
uid 7889,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7890,0
va (VaSet
)
xt "34500,75500,42000,76500"
st "debug_data_valid"
ju 2
blo "42000,76300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7891,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,28400,67500,29200"
st "debug_data_valid      : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 33
suid 105,0
)
)
)
*210 (CptPort
uid 7963,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7964,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,76625,43750,77375"
)
tg (CPTG
uid 7965,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7966,0
va (VaSet
)
xt "30600,76500,42000,77500"
st "mem_manager_state : (3:0)"
ju 2
blo "42000,77300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 7967,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,33200,102500,34000"
st "mem_manager_state     : OUT    std_logic_vector (3 DOWNTO 0) ; -- state is encoded here ... useful for debugging.
"
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "mem_manager_state"
t "std_logic_vector"
b "(3 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 39
suid 106,0
)
)
)
*211 (CptPort
uid 8023,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8024,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,77625,43750,78375"
)
tg (CPTG
uid 8025,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8026,0
va (VaSet
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xt "35100,77500,42000,78500"
st "DG_state : (7:0)"
ju 2
blo "42000,78300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 8027,0
va (VaSet
font "Courier New,8,0"
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xt "44000,16400,77000,18000"
st "-- for debugging
DG_state              : OUT    std_logic_vector (7 downto 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "DG_state"
t "std_logic_vector"
b "(7 downto 0)"
prec "-- for debugging"
preAdd 0
o 19
suid 108,0
)
)
)
*212 (CptPort
uid 8283,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8284,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,78625,43750,79375"
)
tg (CPTG
uid 8285,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8286,0
va (VaSet
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xt "30100,78500,42000,79500"
st "socket_tx_free_out : (16:0)"
ju 2
blo "42000,79300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 8287,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,37200,92500,38000"
st "socket_tx_free_out    : OUT    std_logic_vector (16 DOWNTO 0) ; -- 17bit value .. that's true
"
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 44
suid 109,0
)
)
)
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shape (Rectangle
uid 4141,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,-8000,43000,81000"
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oxt "15000,-8000,43000,45000"
biTextGroup (BiTextGroup
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ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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uid 11,0
va (VaSet
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xt "15200,45000,21400,46000"
st "FACT_FAD_lib"
blo "15200,45800"
)
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xt "15200,46000,19400,47000"
st "FAD_main"
blo "15200,46800"
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ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
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xt "0,12000,15500,14400"
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)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
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value "12"
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portVis (PortSigDisplay
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xt "36200,48000,47000,49000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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shape (Rectangle
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xt "53200,44000,56500,45000"
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tm "CommentText"
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xt "36000,46000,53000,47000"
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text (MLText
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xt "36200,46000,47100,47000"
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tm "CommentText"
wrapOption 3
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position 1
ignorePrefs 1
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uid 27,0
shape (Rectangle
uid 28,0
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va (VaSet
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xt "32000,46000,36000,47000"
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oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
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bg "0,0,32768"
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xt "32200,46000,34500,47000"
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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position 1
ignorePrefs 1
titleBlock 1
)
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uid 30,0
shape (Rectangle
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va (VaSet
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xt "53000,45000,73000,49000"
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oxt "35000,67000,55000,71000"
text (MLText
uid 32,0
va (VaSet
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bg "0,0,32768"
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xt "53200,45200,63000,46200"
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tm "CommentText"
wrapOption 3
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ignorePrefs 1
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shape (Rectangle
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va (VaSet
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xt "57000,44000,73000,45000"
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oxt "39000,66000,55000,67000"
text (MLText
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va (VaSet
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bg "0,0,32768"
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xt "57200,44000,61900,45000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
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shape (Rectangle
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va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "32000,44000,53000,46000"
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oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
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xt "39200,44500,45800,45500"
st "
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ju 0
tm "CommentText"
wrapOption 3
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)
position 1
ignorePrefs 1
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uid 39,0
shape (Rectangle
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sl 0
va (VaSet
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xt "32000,47000,36000,48000"
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oxt "14000,69000,18000,70000"
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va (VaSet
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bg "0,0,32768"
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xt "32200,47000,34500,48000"
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tm "CommentText"
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va (VaSet
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fg "65280,65280,46080"
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xt "32000,48000,36000,49000"
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oxt "14000,70000,18000,71000"
text (MLText
uid 44,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "32200,48000,35300,49000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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)
position 1
ignorePrefs 1
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shape (Rectangle
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va (VaSet
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xt "36000,47000,53000,48000"
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oxt "18000,69000,35000,70000"
text (MLText
uid 47,0
va (VaSet
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bg "0,0,32768"
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xt "36200,47000,50400,48000"
st "
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tm "CommentText"
wrapOption 3
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position 1
ignorePrefs 1
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shape (GroupingShape
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xt "32000,44000,73000,49000"
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oxt "14000,66000,55000,71000"
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bg "65535,65535,65535"
grid (Grid
origin "0,0"
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isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
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packageList *225 (PackageList
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stg "VerticalLayoutStrategy"
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uid 49,0
va (VaSet
font "arial,8,1"
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xt "0,0,5400,1000"
st "Package List"
blo "0,800"
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uid 50,0
va (VaSet
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xt "0,1000,16100,6000"
st "LIBRARY ieee;
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tm "PackageList"
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)
windowSize "0,0,1553,1028"
viewArea "-12542,-31642,130863,66614"
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va (VaSet
vasetType 1
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xt "0,0,15000,5000"
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text (MLText
va (VaSet
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xt "200,200,2400,1200"
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tm "CommentText"
wrapOption 3
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defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
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xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
parentGraphicsRef (HdmGraphicsRef
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entityName ""
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defaultSymbolBody (SymbolBody
shape (Rectangle
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lineColor "0,32896,0"
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xt "15000,6000,33000,26000"
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biTextGroup (BiTextGroup
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va (VaSet
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xt "22200,15000,25800,16000"
st "<library>"
blo "22200,15800"
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second (Text
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xt "22200,16000,24800,17000"
st "<cell>"
blo "22200,16800"
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matrix (Matrix
text (MLText
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xt "0,12000,11500,12800"
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header "Generic Declarations"
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portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
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portVis (PortSigDisplay
sIVOD 1
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defaultCptPort (CptPort
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shape (Triangle
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va (VaSet
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xt "0,0,750,750"
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tg (CPTG
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stg "VerticalLayoutStrategy"
f (Text
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xt "0,750,1400,1750"
st "In0"
blo "0,1550"
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dt (MLText
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thePort (LogicalPort
decl (Decl
n "In0"
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b "(15 DOWNTO 0)"
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defaultCptPortBuffer (CptPort
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tg (CPTG
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stg "VerticalLayoutStrategy"
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xt "0,750,2800,1750"
st "Buffer0"
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dt (MLText
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tm "SyDeclarativeTextMgr"
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xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
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