source: firmware/FAD/FACT_FAD_lib/hds/dna_gen/@behavioral.bd@ 18752

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
]
instances [
(Instance
name "DNA_PORT_inst"
duLibraryName "unisim"
duName "DNA_PORT"
elements [
(GiElement
name "SIM_DNA_VALUE"
type "bit_vector"
value "DNA_FOR_SIM"
)
]
mwi 0
uid 97,0
)
]
embeddedInstances [
(EmbeddedInstance
name "SM"
number "1"
view 1
machine (Machine
name "FTU_dna_gen_State"
children [
(Machine
name "FTU_dna_gen_State"
children [
]
stateSignalName "FTU_dna_gen_State"
)
]
)
)
(EmbeddedInstance
name "eb1"
number "2"
)
]
)
version "29.1"
appVersion "2009.2 (Build 10)"
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen\\@behavioral.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen\\@behavioral.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "Behavioral"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen"
)
(vvPair
variable "d_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FTU_dna_gen"
)
(vvPair
variable "date"
value "15.02.2011"
)
(vvPair
variable "day"
value "Di"
)
(vvPair
variable "day_long"
value "Dienstag"
)
(vvPair
variable "dd"
value "15"
)
(vvPair
variable "entity_name"
value "FTU_dna_gen"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "@behavioral.bd"
)
(vvPair
variable "f_logical"
value "Behavioral.bd"
)
(vvPair
variable "f_noext"
value "@behavioral"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "E5B-LABOR6"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "02"
)
(vvPair
variable "module_name"
value "FTU_dna_gen"
)
(vvPair
variable "month"
value "Feb"
)
(vvPair
variable "month_long"
value "Februar"
)
(vvPair
variable "p"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen\\@behavioral.bd"
)
(vvPair
variable "p_logical"
value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FTU_dna_gen\\Behavioral.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\modeltech_6.6a\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "@behavioral"
)
(vvPair
variable "this_file_logical"
value "Behavioral"
)
(vvPair
variable "time"
value "09:15:09"
)
(vvPair
variable "unit"
value "FTU_dna_gen"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "Behavioral"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
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shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
)
xt "-3000,18000,-2000,18000"
pts [
"-3000,18000"
"-2000,18000"
]
)
start &6
end &176
ss 0
es 0
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
isHidden 1
)
xt "-3000,17000,-1700,18000"
st "clk"
blo "-3000,17800"
tm "WireNameMgr"
)
)
on &7
)
*178 (Wire
uid 43,0
shape (OrthoPolyLine
uid 44,0
va (VaSet
vasetType 3
)
xt "6000,-1000,7000,-1000"
pts [
"6000,-1000"
"7000,-1000"
]
)
start &8
end &24
ss 0
sat 32
eat 1
stc 0
st 0
si 0
tg (WTG
uid 47,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 48,0
va (VaSet
isHidden 1
)
xt "6000,-2000,7900,-1000"
st "start"
blo "6000,-1200"
tm "WireNameMgr"
)
)
on &9
)
*179 (Wire
uid 132,0
shape (OrthoPolyLine
uid 133,0
va (VaSet
vasetType 3
)
xt "1000,3000,35000,5000"
pts [
"29750,3000"
"35000,3000"
"35000,5000"
"1000,5000"
"1000,3000"
"7000,3000"
]
)
start &15
end &24
ss 0
sat 32
eat 1
stc 0
st 0
si 0
tg (WTG
uid 136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 137,0
va (VaSet
isHidden 1
)
xt "3000,2000,6300,3000"
st "dout_sig"
blo "3000,2800"
tm "WireNameMgr"
)
)
on &1
)
*180 (Wire
uid 138,0
shape (OrthoPolyLine
uid 139,0
va (VaSet
vasetType 3
)
xt "19000,2000,21250,2000"
pts [
"19000,2000"
"21250,2000"
]
)
end &16
sat 16
eat 32
stc 0
st 0
si 0
tg (WTG
uid 142,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 143,0
va (VaSet
isHidden 1
)
xt "17000,1000,18300,2000"
st "clk"
blo "17000,1800"
tm "WireNameMgr"
)
)
on &7
)
*181 (Wire
uid 144,0
shape (OrthoPolyLine
uid 145,0
va (VaSet
vasetType 3
)
xt "19000,1000,21250,1000"
pts [
"19000,1000"
"21250,1000"
]
)
end &18
sat 16
eat 32
stc 0
st 0
si 0
tg (WTG
uid 148,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 149,0
va (VaSet
isHidden 1
)
xt "15000,0,18400,1000"
st "read_sig"
blo "15000,800"
tm "WireNameMgr"
)
)
on &2
)
*182 (Wire
uid 150,0
shape (OrthoPolyLine
uid 151,0
va (VaSet
vasetType 3
)
xt "19000,0,21250,0"
pts [
"19000,0"
"21250,0"
]
)
end &19
sat 16
eat 32
stc 0
st 0
si 0
tg (WTG
uid 154,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 155,0
va (VaSet
isHidden 1
)
xt "15000,-1000,18300,0"
st "shift_sig"
blo "15000,-200"
tm "WireNameMgr"
)
)
on &3
)
*183 (Wire
uid 483,0
shape (OrthoPolyLine
uid 484,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "27000,11000,28000,11000"
pts [
"27000,11000"
"28000,11000"
]
)
start &158
end &10
es 0
sat 2
eat 32
sty 1
stc 0
st 0
si 0
tg (WTG
uid 489,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 490,0
va (VaSet
isHidden 1
)
xt "25000,10000,26600,11000"
st "dna"
blo "25000,10800"
tm "WireNameMgr"
)
)
on &11
)
*184 (Wire
uid 491,0
shape (OrthoPolyLine
uid 492,0
va (VaSet
vasetType 3
)
xt "5000,0,7000,0"
pts [
"5000,0"
"7000,0"
]
)
end &24
sat 16
eat 1
stc 0
st 0
si 0
tg (WTG
uid 497,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 498,0
va (VaSet
isHidden 1
)
xt "3000,-1000,4300,0"
st "clk"
blo "3000,-200"
tm "WireNameMgr"
)
)
on &7
)
*185 (Wire
uid 515,0
shape (OrthoPolyLine
uid 516,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "10000,3000,24000,12000"
pts [
"10000,3000"
"16000,3000"
"16000,12000"
"24000,12000"
]
)
start &24
end &158
sat 4
eat 1
sty 1
stc 0
st 0
si 0
tg (WTG
uid 521,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 522,0
va (VaSet
isHidden 1
)
xt "11000,2000,14100,3000"
st "dna_sig"
blo "11000,2800"
tm "WireNameMgr"
)
)
on &4
)
*186 (Wire
uid 523,0
shape (OrthoPolyLine
uid 524,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "10000,2000,12000,2000"
pts [
"10000,2000"
"12000,2000"
]
)
start &24
sat 4
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 529,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 530,0
va (VaSet
isHidden 1
)
xt "13000,1000,16900,2000"
st "shift_cntr"
blo "13000,1800"
tm "WireNameMgr"
)
)
on &5
)
*187 (Wire
uid 531,0
shape (OrthoPolyLine
uid 532,0
va (VaSet
vasetType 3
)
xt "10000,1000,12000,1000"
pts [
"10000,1000"
"12000,1000"
]
)
start &24
sat 2
eat 16
stc 0
st 0
si 0
tg (WTG
uid 537,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 538,0
va (VaSet
isHidden 1
)
xt "13000,0,16400,1000"
st "read_sig"
blo "13000,800"
tm "WireNameMgr"
)
)
on &2
)
*188 (Wire
uid 539,0
shape (OrthoPolyLine
uid 540,0
va (VaSet
vasetType 3
)
xt "10000,-1000,11000,-1000"
pts [
"10000,-1000"
"11000,-1000"
]
)
start &24
end &12
es 0
sat 2
eat 32
stc 0
st 0
si 0
tg (WTG
uid 545,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 546,0
va (VaSet
isHidden 1
)
xt "9000,-2000,11200,-1000"
st "ready"
blo "9000,-1200"
tm "WireNameMgr"
)
)
on &13
)
*189 (Wire
uid 547,0
shape (OrthoPolyLine
uid 548,0
va (VaSet
vasetType 3
)
xt "10000,0,12000,0"
pts [
"10000,0"
"12000,0"
]
)
start &24
sat 2
eat 16
stc 0
st 0
si 0
tg (WTG
uid 553,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 554,0
va (VaSet
isHidden 1
)
xt "13000,-1000,16300,0"
st "shift_sig"
blo "13000,-200"
tm "WireNameMgr"
)
)
on &3
)
*190 (Wire
uid 593,0
shape (OrthoPolyLine
uid 594,0
va (VaSet
vasetType 3
)
xt "-4000,14000,-2000,14000"
pts [
"-4000,14000"
"-2000,14000"
]
)
end &174
ss 0
sat 16
eat 32
stc 0
st 0
si 0
tg (WTG
uid 597,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 598,0
va (VaSet
isHidden 1
)
xt "-7000,13000,-3600,14000"
st "read_sig"
blo "-7000,13800"
tm "WireNameMgr"
)
)
on &2
)
*191 (Wire
uid 602,0
shape (OrthoPolyLine
uid 603,0
va (VaSet
vasetType 3
)
xt "-4000,16000,-2000,16000"
pts [
"-4000,16000"
"-2000,16000"
]
)
end &175
ss 0
sat 16
eat 32
stc 0
st 0
si 0
tg (WTG
uid 606,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 607,0
va (VaSet
isHidden 1
)
xt "-7000,15000,-3700,16000"
st "shift_sig"
blo "-7000,15800"
tm "WireNameMgr"
)
)
on &3
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *192 (PackageList
uid 617,0
stg "VerticalLayoutStrategy"
textVec [
*193 (Text
uid 618,0
va (VaSet
isHidden 1
font "arial,8,1"
)
xt "0,24000,5400,25000"
st "Package List"
blo "0,24800"
)
*194 (MLText
uid 619,0
va (VaSet
isHidden 1
)
xt "0,25000,10900,28000"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 620,0
stg "VerticalLayoutStrategy"
textVec [
*195 (Text
uid 621,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,24000,28100,25000"
st "Compiler Directives"
blo "20000,24800"
)
*196 (Text
uid 622,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,25000,29600,26000"
st "Pre-module directives:"
blo "20000,25800"
)
*197 (MLText
uid 623,0
va (VaSet
isHidden 1
)
xt "20000,26000,27500,28000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*198 (Text
uid 624,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,28000,30100,29000"
st "Post-module directives:"
blo "20000,28800"
)
*199 (MLText
uid 625,0
va (VaSet
isHidden 1
)
xt "20000,24000,20000,24000"
tm "BdCompilerDirectivesTextMgr"
)
*200 (Text
uid 626,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,29000,29900,30000"
st "End-module directives:"
blo "20000,29800"
)
*201 (MLText
uid 627,0
va (VaSet
isHidden 1
)
xt "20000,30000,20000,30000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "0,0,1015,690"
viewArea "-7300,-3000,100000,29000"
cachedDiagramExtent "0,0,0,0"
pageBreakOrigin "0,0"
lastUid 627,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2000,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*202 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*203 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*204 (Text
va (VaSet
font "Arial,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*205 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
)
*206 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
)
*207 (Text
va (VaSet
font "Arial,8,1"
)
xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*208 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,3500,3800,4500"
st "Library"
blo "900,4300"
tm "BdLibraryNameMgr"
)
*209 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,4500,7100,5500"
st "SaComponent"
blo "900,5300"
tm "CptNameMgr"
)
*210 (Text
va (VaSet
font "Arial,8,1"
)
xt "900,5500,2700,6500"
st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6100,1500,-6100,1500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*211 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,3500,3400,4500"
st "Library"
blo "500,4300"
)
*212 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
)
*213 (Text
va (VaSet
font "Arial,8,1"
)
xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6500,1500,-6500,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-450,0,8450,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*214 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,3500,2950,4500"
st "Library"
blo "50,4300"
)
*215 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,4500,7950,5500"
st "VerilogComponent"
blo "50,5300"
)
*216 (Text
va (VaSet
font "Arial,8,1"
)
xt "50,5500,1850,6500"
st "U_0"
blo "50,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
font "Courier New,8,0"
)
xt "-6950,1500,-6950,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*217 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,4000,4850,5000"
st "eb1"
blo "3150,4800"
tm "HdlTextNameMgr"
)
*218 (Text
va (VaSet
font "Arial,8,1"
)
xt "3150,5000,3950,6000"
st "1"
blo "3150,5800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2000,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
font "Arial,8,1"
)
xt "-500,-500,500,500"
st "G"
blo "-500,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
)
xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12600,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*219 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*220 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7400,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*221 (Text
va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*222 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "13000,24000,18400,25000"
st "Declarations"
blo "13000,24800"
)
portLabel (Text
uid 3,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "13000,25000,15700,26000"
st "Ports:"
blo "13000,25800"
)
preUserLabel (Text
uid 4,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "13000,29200,16800,30200"
st "Pre User:"
blo "13000,30000"
)
preUserText (MLText
uid 5,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "15000,30200,57000,31000"
st "constant DNA_FOR_SIM : bit_vector := X\"01710000E000FAD2\"; -- for simulation only
"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "13000,31000,20100,32000"
st "Diagram Signals:"
blo "13000,31800"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "13000,36000,17700,37000"
st "Post User:"
blo "13000,36800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "13000,24000,13000,24000"
tm "BdDeclarativeTextMgr"
)
)
createCompDecls 0
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 10,0
usingSuid 1
emptyRow *223 (LEmptyRow
)
optionalChildren [
*224 (RefLabelRowHdr
)
*225 (TitleRowHdr
)
*226 (FilterRowHdr
)
*227 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*228 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*229 (GroupColHdr
tm "GroupColHdrMgr"
)
*230 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*231 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*232 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*233 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*234 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*235 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*236 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dout_sig"
t "STD_LOGIC"
o 5
suid 1,0
i "'0'"
)
)
uid 441,0
)
*237 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "read_sig"
t "STD_LOGIC"
o 6
suid 2,0
i "'0'"
)
)
uid 443,0
)
*238 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "shift_sig"
t "STD_LOGIC"
o 7
suid 3,0
i "'0'"
)
)
uid 445,0
)
*239 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dna_sig"
t "STD_LOGIC_VECTOR"
b "(63 downto 0)"
o 8
suid 4,0
i "(others => '0')"
)
)
uid 447,0
)
*240 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "shift_cntr"
t "INTEGER"
b "RANGE 0 to 64"
o 9
suid 6,0
i "0"
)
)
uid 451,0
)
*241 (LeafLogPort
port (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 1
suid 7,0
)
)
uid 453,0
)
*242 (LeafLogPort
port (LogicalPort
decl (Decl
n "start"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 2
suid 8,0
)
)
uid 455,0
)
*243 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "dna"
t "STD_LOGIC_VECTOR"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 3
suid 9,0
i "(others => '0')"
)
)
uid 457,0
)
*244 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "ready"
t "STD_LOGIC"
preAdd 0
posAdd 0
o 4
suid 10,0
i "'0'"
)
)
uid 459,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
optionalChildren [
*245 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *246 (MRCItem
litem &223
pos 3
dimension 20
)
optionalChildren [
*247 (MRCItem
litem &224
pos 0
dimension 20
)
*248 (MRCItem
litem &225
pos 1
dimension 23
)
*249 (MRCItem
litem &226
pos 2
hidden 1
dimension 20
)
*250 (MRCItem
litem &236
pos 4
dimension 20
uid 442,0
)
*251 (MRCItem
litem &237
pos 5
dimension 20
uid 444,0
)
*252 (MRCItem
litem &238
pos 6
dimension 20
uid 446,0
)
*253 (MRCItem
litem &239
pos 7
dimension 20
uid 448,0
)
*254 (MRCItem
litem &240
pos 8
dimension 20
uid 452,0
)
*255 (MRCItem
litem &241
pos 0
dimension 20
uid 454,0
)
*256 (MRCItem
litem &242
pos 1
dimension 20
uid 456,0
)
*257 (MRCItem
litem &243
pos 2
dimension 20
uid 458,0
)
*258 (MRCItem
litem &244
pos 3
dimension 20
uid 460,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
optionalChildren [
*259 (MRCItem
litem &227
pos 0
dimension 20
)
*260 (MRCItem
litem &229
pos 1
dimension 50
)
*261 (MRCItem
litem &230
pos 2
dimension 100
)
*262 (MRCItem
litem &231
pos 3
dimension 50
)
*263 (MRCItem
litem &232
pos 4
dimension 100
)
*264 (MRCItem
litem &233
pos 5
dimension 100
)
*265 (MRCItem
litem &234
pos 6
dimension 50
)
*266 (MRCItem
litem &235
pos 7
dimension 80
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
vaOverrides [
]
)
]
)
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *267 (LEmptyRow
)
optionalChildren [
*268 (RefLabelRowHdr
)
*269 (TitleRowHdr
)
*270 (FilterRowHdr
)
*271 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*272 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*273 (GroupColHdr
tm "GroupColHdrMgr"
)
*274 (NameColHdr
tm "GenericNameColHdrMgr"
)
*275 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*276 (InitColHdr
tm "GenericValueColHdrMgr"
)
*277 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*278 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
optionalChildren [
*279 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *280 (MRCItem
litem &267
pos 3
dimension 20
)
optionalChildren [
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litem &268
pos 0
dimension 20
)
*282 (MRCItem
litem &269
pos 1
dimension 23
)
*283 (MRCItem
litem &270
pos 2
hidden 1
dimension 20
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
optionalChildren [
*284 (MRCItem
litem &271
pos 0
dimension 20
)
*285 (MRCItem
litem &273
pos 1
dimension 50
)
*286 (MRCItem
litem &274
pos 2
dimension 100
)
*287 (MRCItem
litem &275
pos 3
dimension 100
)
*288 (MRCItem
litem &276
pos 4
dimension 50
)
*289 (MRCItem
litem &277
pos 5
dimension 50
)
*290 (MRCItem
litem &278
pos 6
dimension 80
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
vaOverrides [
]
)
]
)
type 1
)
)