DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "IEEE"
unitName "NUMERIC_STD"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
)
]
libraryRefs [
"ieee"
"FACT_FAD_lib"
]
)
version "24.1"
appVersion "2009.1 (Build 12)"
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t "std_logic"
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o 4
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i "'0'"
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)
uid 128,0
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*17 (LogPort
port (LogicalPort
m 1
decl (Decl
n "PSINCDEC"
t "std_logic"
eolc "-- default is 'incrementing'"
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o 5
suid 4,0
i "'1'"
)
)
uid 130,0
)
*18 (LogPort
port (LogicalPort
decl (Decl
n "PSDONE"
t "std_logic"
eolc "-- will pulse once, if phase shifting was done."
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posAdd 0
o 6
suid 5,0
)
)
uid 132,0
)
*19 (LogPort
port (LogicalPort
decl (Decl
n "LOCKED"
t "std_logic"
eolc "-- when is this going high?"
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o 7
suid 6,0
)
)
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)
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port (LogicalPort
decl (Decl
n "shift_phase"
t "std_logic"
prec "-- interface to: w5300_modul.vhd"
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o 8
suid 8,0
)
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uid 138,0
)
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port (LogicalPort
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m 1
decl (Decl
n "shifting"
t "std_logic"
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o 11
suid 10,0
i "'0'"
)
)
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)
*23 (LogPort
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decl (Decl
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i "'0'"
)
)
uid 144,0
)
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port (LogicalPort
m 1
decl (Decl
n "offset"
t "std_logic_vector"
b "(7 DOWNTO 0)"
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o 15
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i "(OTHERS => '0')"
)
)
uid 146,0
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*25 (LogPort
port (LogicalPort
m 1
decl (Decl
n "rst"
t "std_logic"
eolc "--asynch in of DCM"
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suid 15,0
i "'0'"
)
)
uid 286,0
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*26 (LogPort
port (LogicalPort
decl (Decl
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t "std_logic"
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o 10
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)
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*27 (LogPort
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m 1
decl (Decl
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o 13
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port (LogicalPort
m 1
decl (Decl
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t "std_logic"
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dimension 20
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*56 (MRCItem
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fixedCol 4
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name "Ports"
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]
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uid 156,0
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tm "GenericNameColHdrMgr"
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tm "GenericTypeColHdrMgr"
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tm "GenericEolColHdrMgr"
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fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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pos 2
dimension 100
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)
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uid 208,0
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pos 5
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fixedCol 3
fixedRow 2
name "Ports"
uid 199,0
vaOverrides [
]
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uid 185,0
type 1
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VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\phase_shifter\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\phase_shifter\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\phase_shifter"
)
(vvPair
variable "d_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\phase_shifter"
)
(vvPair
variable "date"
value "03.03.2011"
)
(vvPair
variable "day"
value "Do"
)
(vvPair
variable "day_long"
value "Donnerstag"
)
(vvPair
variable "dd"
value "03"
)
(vvPair
variable "entity_name"
value "phase_shifter"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "IHP110"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "03"
)
(vvPair
variable "module_name"
value "phase_shifter"
)
(vvPair
variable "month"
value "Mrz"
)
(vvPair
variable "month_long"
value "März"
)
(vvPair
variable "p"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\phase_shifter\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\phase_shifter\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "D:\\modeltech_6.5e\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "09:46:07"
)
(vvPair
variable "unit"
value "phase_shifter"
)
(vvPair
variable "user"
value "daqct3"
)
(vvPair
variable "version"
value "2009.1 (Build 12)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 155,0
optionalChildren [
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uid 8,0
optionalChildren [
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uid 48,0
ps "OnEdgeStrategy"
shape (Triangle
uid 49,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,8625,50000,9375"
)
tg (CPTG
uid 50,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 51,0
va (VaSet
)
xt "51000,8500,52800,9500"
st "CLK"
blo "51000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 52,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,8000,22000,8800"
st "CLK             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*83 (CptPort
uid 53,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "66000,8625,66750,9375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
)
xt "62200,8500,65000,9500"
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ju 2
blo "65000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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)
xt "2000,9600,31500,11200"
st "-- interface to: clock_generator_variable_PS_struct.vhd
PSCLK           : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
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n "PSCLK"
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preAdd 0
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o 3
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)
)
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ro 90
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fg "0,65535,0"
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xt "66000,10625,66750,11375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
)
xt "62500,10500,65000,11500"
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ju 2
blo "65000,11300"
tm "CptPortNameMgr"
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va (VaSet
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)
xt "2000,11200,35500,12000"
st "PSEN            : OUT    std_logic                     := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "PSEN"
t "std_logic"
preAdd 0
posAdd 0
o 4
suid 3,0
i "'0'"
)
)
)
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uid 63,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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)
xt "66000,12625,66750,13375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
)
xt "60500,12500,65000,13500"
st "PSINCDEC"
ju 2
blo "65000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 67,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,12000,50000,12800"
st "PSINCDEC        : OUT    std_logic                     := '1' ; -- default is 'incrementing'
"
)
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m 1
decl (Decl
n "PSINCDEC"
t "std_logic"
eolc "-- default is 'incrementing'"
preAdd 0
posAdd 0
o 5
suid 4,0
i "'1'"
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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fg "0,65535,0"
)
xt "49250,10625,50000,11375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 71,0
va (VaSet
)
xt "51000,10500,54700,11500"
st "PSDONE"
blo "51000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 72,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,12800,46500,13600"
st "PSDONE          : IN     std_logic  ; -- will pulse once, if phase shifting was done.
"
)
thePort (LogicalPort
decl (Decl
n "PSDONE"
t "std_logic"
eolc "-- will pulse once, if phase shifting was done."
preAdd 0
posAdd 0
o 6
suid 5,0
)
)
)
*87 (CptPort
uid 73,0
ps "OnEdgeStrategy"
shape (Triangle
uid 74,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,12625,50000,13375"
)
tg (CPTG
uid 75,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 76,0
va (VaSet
)
xt "51000,12500,54500,13500"
st "LOCKED"
blo "51000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 77,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,13600,36500,14400"
st "LOCKED          : IN     std_logic  ; -- when is this going high?
"
)
thePort (LogicalPort
decl (Decl
n "LOCKED"
t "std_logic"
eolc "-- when is this going high?"
preAdd 0
posAdd 0
o 7
suid 6,0
)
)
)
*88 (CptPort
uid 83,0
ps "OnEdgeStrategy"
shape (Triangle
uid 84,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,16625,50000,17375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 86,0
va (VaSet
)
xt "51000,16500,56400,17500"
st "shift_phase"
blo "51000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 87,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,14400,22000,16000"
st "-- interface to: w5300_modul.vhd
shift_phase     : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "shift_phase"
t "std_logic"
prec "-- interface to: w5300_modul.vhd"
preAdd 0
posAdd 0
o 8
suid 8,0
)
)
)
*89 (CptPort
uid 88,0
ps "OnEdgeStrategy"
shape (Triangle
uid 89,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,18625,50000,19375"
)
tg (CPTG
uid 90,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 91,0
va (VaSet
)
xt "51000,18500,54700,19500"
st "direction"
blo "51000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 92,0
va (VaSet
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