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(RowExpandColHdr tm "RowExpandColHdrMgr" ) *53 (GroupColHdr tm "GroupColHdrMgr" ) *54 (NameColHdr tm "GenericNameColHdrMgr" ) *55 (TypeColHdr tm "GenericTypeColHdrMgr" ) *56 (InitColHdr tm "GenericValueColHdrMgr" ) *57 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *58 (EolColHdr tm "GenericEolColHdrMgr" ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 94,0 optionalChildren [ *59 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *60 (MRCItem litem &47 pos 0 dimension 20 ) uid 96,0 optionalChildren [ *61 (MRCItem litem &48 pos 0 dimension 20 uid 97,0 ) *62 (MRCItem litem &49 pos 1 dimension 23 uid 98,0 ) *63 (MRCItem litem &50 pos 2 hidden 1 dimension 20 uid 99,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" 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) (vvPair variable "SourceDir" value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "symbol" ) (vvPair variable "config" value "%(unit)_config" ) (vvPair variable "d" value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit" ) (vvPair variable "d_logical" value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit" ) (vvPair variable "date" value "30.04.2010" ) (vvPair variable "day" value "Fr" ) (vvPair variable "day_long" value "Freitag" ) (vvPair variable "dd" value "30" ) (vvPair variable "entity_name" value "spi_unit" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "symbol.sb" ) (vvPair variable "f_logical" value "symbol.sb" ) (vvPair variable "f_noext" value "symbol" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "EEPC8" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "FACT_FAD_lib" ) (vvPair variable "library_downstream_ISEPARInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" ) (vvPair variable "library_downstream_ImpactInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" ) (vvPair variable "library_downstream_XSTDataPrep" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" ) (vvPair variable "mm" value "04" ) (vvPair variable "module_name" value "spi_unit" ) (vvPair variable "month" value "Apr" ) (vvPair variable "month_long" value "April" ) (vvPair variable "p" value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit\\symbol.sb" ) (vvPair variable "p_logical" value "D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\spi_unit\\symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "FACT_FAD" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "$HDS_HOME/../Modeltech/win32" ) (vvPair variable "task_NC-SimPath" value "" ) (vvPair variable "task_PrecisionRTLPath" value "$HDS_HOME/../Precision/Mgc_home/bin" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "13:54:34" ) (vvPair variable "unit" value "spi_unit" ) (vvPair variable "user" value "Benjamin Krumm" ) (vvPair variable "version" value "2009.1 (Build 12)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2010" ) (vvPair variable "yy" value "10" ) ] ) LanguageMgr "VhdlLangMgr" uid 51,0 optionalChildren [ *71 (SymbolBody uid 8,0 optionalChildren [ *72 (CptPort uid 126,0 ps "OnEdgeStrategy" shape (Triangle uid 127,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "30000,12625,30750,13375" ) tg (CPTG uid 128,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 129,0 va (VaSet ) xt "27300,12500,29000,13500" st "sclk" ju 2 blo "29000,13300" tm "CptPortNameMgr" ) ) dt (MLText uid 131,0 va (VaSet font "Courier New,8,0" ) xt "44000,6000,62500,6800" st "sclk : OUT std_logic ;" ) thePort (LogicalPort m 1 decl (Decl n "sclk" t "std_logic" o 6 suid 1,0 ) ) ) *73 (CptPort uid 137,0 ps "OnEdgeStrategy" shape (Diamond uid 138,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "30000,13625,30750,14375" ) tg (CPTG uid 139,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 140,0 va (VaSet ) xt "27600,13500,29000,14500" st "sio" ju 2 blo "29000,14300" tm "CptPortNameMgr" ) ) dt (MLText uid 141,0 va (VaSet font "Courier New,8,0" ) xt "44000,9200,61500,10000" st "sio : INOUT std_logic " ) thePort (LogicalPort m 2 decl (Decl n "sio" t "std_logic" preAdd 0 posAdd 0 o 10 suid 3,0 ) ) ) *74 (CptPort uid 197,0 ps "OnEdgeStrategy" shape (Triangle uid 198,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,15625,15000,16375" ) tg (CPTG uid 199,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 200,0 va (VaSet ) xt "16000,15500,19700,16500" st "dac_array" blo "16000,16300" tm "CptPortNameMgr" ) ) dt (MLText uid 201,0 va (VaSet font "Courier New,8,0" ) xt "44000,3600,65000,4400" st "dac_array : IN dac_array_type ;" ) thePort (LogicalPort decl (Decl n "dac_array" t "dac_array_type" o 3 suid 10,0 ) ) ) *75 (CptPort uid 321,0 ps "OnEdgeStrategy" shape (Triangle uid 377,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,21625,15000,22375" ) tg (CPTG uid 323,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 324,0 va (VaSet ) xt "16000,21500,21100,22500" st "config_ready" blo "16000,22300" tm "CptPortNameMgr" ) ) dt (MLText uid 325,0 va (VaSet font "Courier New,8,0" ) xt "44000,4400,62500,5200" st "config_ready : OUT std_logic ;" ) thePort (LogicalPort m 1 decl (Decl n "config_ready" t "std_logic" o 4 suid 11,0 ) ) ) *76 (CptPort uid 326,0 ps "OnEdgeStrategy" shape (Triangle uid 327,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,20625,15000,21375" ) tg (CPTG uid 328,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 329,0 va (VaSet ) xt "16000,20500,20800,21500" st "config_start" blo "16000,21300" tm "CptPortNameMgr" ) ) dt (MLText uid 330,0 va (VaSet font "Courier New,8,0" ) xt "44000,2800,62500,3600" st "config_start : IN std_logic ;" ) thePort (LogicalPort decl (Decl n "config_start" t "std_logic" o 2 suid 12,0 ) ) ) *77 (CptPort uid 819,0 ps "OnEdgeStrategy" shape (Triangle uid 820,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,16625,15000,17375" ) tg (CPTG uid 821,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 822,0 va (VaSet ) xt "16000,16500,21200,17500" st "sensor_array" blo "16000,17300" tm "CptPortNameMgr" ) ) dt (MLText uid 823,0 va (VaSet font "Courier New,8,0" ) xt "44000,6800,67000,7600" st "sensor_array : OUT sensor_array_type ;" ) thePort (LogicalPort m 1 decl (Decl n "sensor_array" t "sensor_array_type" o 7 suid 13,0 ) ) ) *78 (CptPort uid 824,0 ps "OnEdgeStrategy" shape (Triangle uid 825,0 ro 270 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,22625,15000,23375" ) tg (CPTG uid 826,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 827,0 va (VaSet ) xt "16000,22500,21300,23500" st "sensor_ready" blo "16000,23300" tm "CptPortNameMgr" ) ) dt (MLText uid 828,0 va (VaSet font "Courier New,8,0" ) xt "44000,8400,62500,9200" st "sensor_ready : OUT std_logic ;" ) thePort (LogicalPort m 1 decl (Decl n "sensor_ready" t "std_logic" o 9 suid 14,0 ) ) ) *79 (CptPort uid 1017,0 ps "OnEdgeStrategy" shape (Triangle uid 1018,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "30000,15625,30750,16375" ) tg (CPTG uid 1019,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1020,0 va (VaSet ) xt "26200,15500,29000,16500" st "dac_cs" ju 2 blo "29000,16300" tm "CptPortNameMgr" ) ) dt (MLText uid 1021,0 va (VaSet font "Courier New,8,0" ) xt "44000,5200,62500,6000" st "dac_cs : OUT std_logic ;" ) thePort (LogicalPort m 1 decl (Decl n "dac_cs" t "std_logic" o 5 suid 15,0 ) ) ) *80 (CptPort uid 1022,0 ps "OnEdgeStrategy" shape (Triangle uid 1023,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "30000,16625,30750,17375" ) tg (CPTG uid 1024,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1025,0 va (VaSet ) xt "22500,16500,29000,17500" st "sensor_cs : (3:0)" ju 2 blo "29000,17300" tm "CptPortNameMgr" ) ) dt (MLText uid 1026,0 va (VaSet font "Courier New,8,0" ) xt "44000,7600,72500,8400" st "sensor_cs : OUT std_logic_vector (3 DOWNTO 0) ;" ) thePort (LogicalPort m 1 decl (Decl n "sensor_cs" t "std_logic_vector" b "(3 DOWNTO 0)" o 8 suid 16,0 ) ) ) *81 (CptPort uid 1121,0 ps "OnEdgeStrategy" shape (Triangle uid 1122,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "14250,12625,15000,13375" ) tg (CPTG uid 1123,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 1124,0 va (VaSet ) xt "16000,12500,20200,13500" st "clk_50MHz" blo "16000,13300" tm "CptPortNameMgr" ) ) dt (MLText uid 1125,0 va (VaSet font "Courier New,8,0" ) xt "44000,2000,62500,2800" st "clk_50MHz : IN std_logic ;" ) thePort (LogicalPort decl (Decl n "clk_50MHz" t "std_logic" preAdd 0 posAdd 0 o 1 suid 17,0 ) ) ) ] shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,12000,30000,26000" ) biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet font "Arial,8,1" ) xt "15200,26000,21400,27000" st "FACT_FAD_lib" blo "15200,26800" ) second (Text uid 12,0 va (VaSet font "Arial,8,1" ) xt "15200,27000,18600,28000" st "spi_unit" blo "15200,27800" ) ) gi *82 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" matrix (Matrix uid 14,0 text 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