source: firmware/FAD/FACT_FAD_lib/hds/w5300_modul/symbol.sb@ 18752

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_1164"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
itemName "ALL"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_UNSIGNED"
itemName "ALL"
)
(DmPackageRef
library "FACT_FAD_lib"
unitName "fad_definitions"
itemName "ALL"
)
]
libraryRefs [
"IEEE"
"FACT_FAD_lib"
]
)
version "24.1"
appVersion "2009.1 (Build 12)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 77,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
uid 175,0
optionalChildren [
*2 (RefLabelRowHdr
)
*3 (TitleRowHdr
)
*4 (FilterRowHdr
)
*5 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*6 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*7 (GroupColHdr
tm "GroupColHdrMgr"
)
*8 (NameColHdr
tm "NameColHdrMgr"
)
*9 (ModeColHdr
tm "ModeColHdrMgr"
)
*10 (TypeColHdr
tm "TypeColHdrMgr"
)
*11 (BoundsColHdr
tm "BoundsColHdrMgr"
)
*12 (InitColHdr
tm "InitColHdrMgr"
)
*13 (EolColHdr
tm "EolColHdrMgr"
)
*14 (LogPort
port (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 7
suid 1,0
)
)
uid 136,0
)
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 2,0
i "'1'"
)
)
uid 138,0
)
*16 (LogPort
port (LogicalPort
m 1
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 9
suid 3,0
)
)
uid 140,0
)
*17 (LogPort
port (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 10
suid 4,0
)
)
uid 142,0
)
*18 (LogPort
port (LogicalPort
m 1
decl (Decl
n "cs"
t "std_logic"
preAdd 0
posAdd 0
o 11
suid 5,0
i "'1'"
)
)
uid 144,0
)
*19 (LogPort
port (LogicalPort
m 1
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 6,0
i "'1'"
)
)
uid 146,0
)
*20 (LogPort
port (LogicalPort
m 1
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 8,0
i "'1'"
)
)
uid 150,0
)
*21 (LogPort
port (LogicalPort
decl (Decl
n "int"
t "std_logic"
preAdd 0
posAdd 0
o 15
suid 9,0
)
)
uid 152,0
)
*22 (LogPort
port (LogicalPort
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
preAdd 0
posAdd 0
o 16
suid 10,0
)
)
uid 154,0
)
*23 (LogPort
port (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 11,0
)
)
uid 156,0
)
*24 (LogPort
port (LogicalPort
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 18
suid 12,0
)
)
uid 158,0
)
*25 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 19
suid 13,0
)
)
uid 160,0
)
*26 (LogPort
port (LogicalPort
decl (Decl
n "data_valid"
t "std_logic"
preAdd 0
posAdd 0
o 20
suid 14,0
)
)
uid 162,0
)
*27 (LogPort
port (LogicalPort
m 1
decl (Decl
n "busy"
t "std_logic"
preAdd 0
posAdd 0
o 22
suid 15,0
i "'1'"
)
)
uid 164,0
)
*28 (LogPort
port (LogicalPort
decl (Decl
n "write_end_flag"
t "std_logic"
o 24
suid 18,0
)
)
uid 358,0
)
*29 (LogPort
port (LogicalPort
decl (Decl
n "write_header_flag"
t "std_logic"
o 23
suid 19,0
)
)
uid 360,0
)
*30 (LogPort
port (LogicalPort
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 25
suid 20,0
)
)
uid 390,0
)
*31 (LogPort
port (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 13
suid 22,0
i "(OTHERS => '0')"
)
)
uid 496,0
)
*32 (LogPort
port (LogicalPort
m 1
decl (Decl
n "s_trigger"
t "std_logic"
prec "-- softtrigger:"
preAdd 0
o 26
suid 23,0
i "'0'"
)
)
uid 526,0
)
*33 (LogPort
port (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override."
preAdd 0
posAdd 0
o 42
suid 31,0
i "'0'"
)
)
uid 675,0
)
*34 (LogPort
port (LogicalPort
m 1
decl (Decl
n "dwrite_enable"
t "std_logic"
eolc "-- default DWRITE low."
preAdd 0
posAdd 0
o 43
suid 32,0
i "'1'"
)
)
uid 728,0
)
*35 (LogPort
port (LogicalPort
m 1
decl (Decl
n "data_valid_ack"
t "std_logic"
o 21
suid 34,0
i "'0'"
)
)
uid 890,0
)
*36 (LogPort
port (LogicalPort
m 1
decl (Decl
n "sclk_enable"
t "std_logic"
eolc "-- default DWRITE HIGH."
posAdd 0
o 44
suid 35,0
i "'1'"
)
)
uid 922,0
)
*37 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ps_direction"
t "std_logic"
prec "------------------------------------------------------------------------------

-- ADC CLK generator, is able to shift phase with respect to X_50M
-- these signals control the behavior of the digital clock manager (DCM)
------------------------------------------------------------------------------"
eolc "-- default phase shift upwards"
preAdd 0
posAdd 0
o 49
suid 36,0
i "'1'"
)
)
uid 959,0
)
*38 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 50
suid 37,0
i "'0'"
)
)
uid 961,0
)
*39 (LogPort
port (LogicalPort
m 1
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 51
suid 38,0
i "'0'"
)
)
uid 993,0
)
*40 (LogPort
port (LogicalPort
m 1
decl (Decl
n "srclk_enable"
t "std_logic"
eolc "-- default SRCLK on."
posAdd 0
o 45
suid 39,0
i "'1'"
)
)
uid 1025,0
)
*41 (LogPort
port (LogicalPort
m 1
decl (Decl
n "socks_connected"
t "std_logic"
posc "------------------------------------------------------------------------------"
posAdd 0
o 54
suid 42,0
)
)
uid 1101,0
)
*42 (LogPort
port (LogicalPort
m 1
decl (Decl
n "socks_waiting"
t "std_logic"
prec "------------------------------------------------------------------------------

-- signals used to control FAD LED bahavior:
-- one of the three LEDs is used for com-status info
------------------------------------------------------------------------------"
preAdd 0
o 53
suid 43,0
)
)
uid 1103,0
)
*43 (LogPort
port (LogicalPort
m 1
decl (Decl
n "trigger_enable"
t "std_logic"
prec "------------------------------------------------------------------------------

-- user controllable enable signals
------------------------------------------------------------------------------"
preAdd 0
posAdd 0
o 41
suid 44,0
)
)
uid 1135,0
)
*44 (LogPort
port (LogicalPort
m 1
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 27
suid 45,0
i "'0'"
)
)
uid 1197,0
)
*45 (LogPort
port (LogicalPort
m 1
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
eolc "--subject to changes"
posAdd 0
o 28
suid 46,0
i "conv_std_logic_vector(0 ,16)"
)
)
uid 1199,0
)
*46 (LogPort
port (LogicalPort
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 downto 0)"
prec "------------------------------------------------------------------------------

-- MAC/IP calculation signals:
------------------------------------------------------------------------------"
preAdd 0
o 38
suid 48,0
)
)
uid 1288,0
)
*47 (LogPort
port (LogicalPort
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 downto 0)"
o 39
suid 49,0
)
)
uid 1325,0
)
*48 (LogPort
port (LogicalPort
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 downto 0)"
posAdd 0
o 40
suid 50,0
)
)
uid 1327,0
)
*49 (LogPort
port (LogicalPort
m 1
decl (Decl
n "dac_setting"
t "dac_array_type"
prec "--data_generator_config_start_o   : out std_logic := '0';
--data_generator_config_valid_i : in std_logic;"
eolc "--<<-- default defined in fad_definitions.vhd"
preAdd 0
posAdd 0
o 33
suid 54,0
i "DEFAULT_DAC"
)
)
uid 1605,0
)
*50 (LogPort
port (LogicalPort
m 1
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
prec "-- FAD configuration signals:
------------------------------------------------------------------------------"
preAdd 0
o 29
suid 59,0
i "'0'"
)
)
uid 1615,0
)
*51 (LogPort
port (LogicalPort
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 30
suid 60,0
)
)
uid 1617,0
)
*52 (LogPort
port (LogicalPort
m 1
decl (Decl
n "roi_setting"
t "roi_array_type"
eolc "--<<-- default defined in fad_definitions.vhd"
preAdd 0
posAdd 0
o 34
suid 61,0
i "DEFAULT_ROI"
)
)
uid 1619,0
)
*53 (LogPort
port (LogicalPort
m 1
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 31
suid 63,0
i "'0'"
)
)
uid 1623,0
)
*54 (LogPort
port (LogicalPort
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
posAdd 0
o 32
suid 64,0
)
)
uid 1625,0
)
*55 (LogPort
port (LogicalPort
decl (Decl
n "data_ram_empty"
t "std_logic"
preAdd 0
o 37
suid 65,0
)
)
uid 1807,0
)
*56 (LogPort
port (LogicalPort
decl (Decl
n "ps_ready"
t "std_logic"
o 52
suid 66,0
)
)
uid 1839,0
)
*57 (LogPort
port (LogicalPort
m 1
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 35
suid 67,0
i "conv_std_logic_vector(0 ,32)"
)
)
uid 1896,0
)
*58 (LogPort
port (LogicalPort
m 1
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 36
suid 68,0
i "'0'"
)
)
uid 1928,0
)
*59 (LogPort
port (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 1
suid 69,0
)
)
uid 1960,0
)
*60 (LogPort
port (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 2
suid 70,0
)
)
uid 2022,0
)
*61 (LogPort
port (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 3
suid 71,0
)
)
uid 2024,0
)
*62 (LogPort
port (LogicalPort
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 4
suid 72,0
)
)
uid 2056,0
)
*63 (LogPort
port (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 6
suid 73,0
)
)
uid 2138,0
)
*64 (LogPort
port (LogicalPort
m 1
decl (Decl
n "busy_enable"
t "std_logic"
o 46
suid 74,0
i "'0'"
)
)
uid 2175,0
)
*65 (LogPort
port (LogicalPort
m 1
decl (Decl
n "socket_send_mode_out"
t "std_logic"
o 47
suid 75,0
)
)
uid 2177,0
)
*66 (LogPort
port (LogicalPort
m 1
decl (Decl
n "busy_manual"
t "std_logic"
o 48
suid 76,0
i "'0'"
)
)
uid 2239,0
)
*67 (LogPort
port (LogicalPort
decl (Decl
n "data_ram_not_full"
t "std_logic"
o 5
suid 77,0
)
)
uid 2241,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 188,0
optionalChildren [
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sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *69 (MRCItem
litem &1
pos 3
dimension 20
)
uid 190,0
optionalChildren [
*70 (MRCItem
litem &2
pos 0
dimension 20
uid 191,0
)
*71 (MRCItem
litem &3
pos 1
dimension 23
uid 192,0
)
*72 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 193,0
)
*73 (MRCItem
litem &14
pos 0
dimension 20
uid 137,0
)
*74 (MRCItem
litem &15
pos 1
dimension 20
uid 139,0
)
*75 (MRCItem
litem &16
pos 2
dimension 20
uid 141,0
)
*76 (MRCItem
litem &17
pos 3
dimension 20
uid 143,0
)
*77 (MRCItem
litem &18
pos 4
dimension 20
uid 145,0
)
*78 (MRCItem
litem &19
pos 5
dimension 20
uid 147,0
)
*79 (MRCItem
litem &20
pos 6
dimension 20
uid 151,0
)
*80 (MRCItem
litem &21
pos 7
dimension 20
uid 153,0
)
*81 (MRCItem
litem &22
pos 8
dimension 20
uid 155,0
)
*82 (MRCItem
litem &23
pos 9
dimension 20
uid 157,0
)
*83 (MRCItem
litem &24
pos 10
dimension 20
uid 159,0
)
*84 (MRCItem
litem &25
pos 11
dimension 20
uid 161,0
)
*85 (MRCItem
litem &26
pos 12
dimension 20
uid 163,0
)
*86 (MRCItem
litem &27
pos 13
dimension 20
uid 165,0
)
*87 (MRCItem
litem &28
pos 14
dimension 20
uid 359,0
)
*88 (MRCItem
litem &29
pos 15
dimension 20
uid 361,0
)
*89 (MRCItem
litem &30
pos 16
dimension 20
uid 391,0
)
*90 (MRCItem
litem &31
pos 17
dimension 20
uid 497,0
)
*91 (MRCItem
litem &32
pos 18
dimension 20
uid 527,0
)
*92 (MRCItem
litem &33
pos 19
dimension 20
uid 676,0
)
*93 (MRCItem
litem &34
pos 20
dimension 20
uid 729,0
)
*94 (MRCItem
litem &35
pos 21
dimension 20
uid 891,0
)
*95 (MRCItem
litem &36
pos 22
dimension 20
uid 923,0
)
*96 (MRCItem
litem &37
pos 23
dimension 20
uid 960,0
)
*97 (MRCItem
litem &38
pos 24
dimension 20
uid 962,0
)
*98 (MRCItem
litem &39
pos 25
dimension 20
uid 994,0
)
*99 (MRCItem
litem &40
pos 26
dimension 20
uid 1026,0
)
*100 (MRCItem
litem &41
pos 27
dimension 20
uid 1102,0
)
*101 (MRCItem
litem &42
pos 28
dimension 20
uid 1104,0
)
*102 (MRCItem
litem &43
pos 29
dimension 20
uid 1136,0
)
*103 (MRCItem
litem &44
pos 30
dimension 20
uid 1198,0
)
*104 (MRCItem
litem &45
pos 31
dimension 20
uid 1200,0
)
*105 (MRCItem
litem &46
pos 32
dimension 20
uid 1289,0
)
*106 (MRCItem
litem &47
pos 33
dimension 20
uid 1326,0
)
*107 (MRCItem
litem &48
pos 34
dimension 20
uid 1328,0
)
*108 (MRCItem
litem &49
pos 35
dimension 20
uid 1606,0
)
*109 (MRCItem
litem &50
pos 36
dimension 20
uid 1616,0
)
*110 (MRCItem
litem &51
pos 37
dimension 20
uid 1618,0
)
*111 (MRCItem
litem &52
pos 38
dimension 20
uid 1620,0
)
*112 (MRCItem
litem &53
pos 39
dimension 20
uid 1624,0
)
*113 (MRCItem
litem &54
pos 40
dimension 20
uid 1626,0
)
*114 (MRCItem
litem &55
pos 41
dimension 20
uid 1808,0
)
*115 (MRCItem
litem &56
pos 42
dimension 20
uid 1840,0
)
*116 (MRCItem
litem &57
pos 43
dimension 20
uid 1897,0
)
*117 (MRCItem
litem &58
pos 44
dimension 20
uid 1929,0
)
*118 (MRCItem
litem &59
pos 45
dimension 20
uid 1961,0
)
*119 (MRCItem
litem &60
pos 46
dimension 20
uid 2023,0
)
*120 (MRCItem
litem &61
pos 47
dimension 20
uid 2025,0
)
*121 (MRCItem
litem &62
pos 48
dimension 20
uid 2057,0
)
*122 (MRCItem
litem &63
pos 49
dimension 20
uid 2139,0
)
*123 (MRCItem
litem &64
pos 50
dimension 20
uid 2176,0
)
*124 (MRCItem
litem &65
pos 51
dimension 20
uid 2178,0
)
*125 (MRCItem
litem &66
pos 52
dimension 20
uid 2240,0
)
*126 (MRCItem
litem &67
pos 53
dimension 20
uid 2242,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 194,0
optionalChildren [
*127 (MRCItem
litem &5
pos 0
dimension 20
uid 195,0
)
*128 (MRCItem
litem &7
pos 1
dimension 50
uid 196,0
)
*129 (MRCItem
litem &8
pos 2
dimension 100
uid 197,0
)
*130 (MRCItem
litem &9
pos 3
dimension 50
uid 198,0
)
*131 (MRCItem
litem &10
pos 4
dimension 100
uid 199,0
)
*132 (MRCItem
litem &11
pos 5
dimension 100
uid 200,0
)
*133 (MRCItem
litem &12
pos 6
dimension 50
uid 201,0
)
*134 (MRCItem
litem &13
pos 7
dimension 80
uid 202,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 189,0
vaOverrides [
]
)
]
)
uid 174,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *135 (LEmptyRow
)
uid 204,0
optionalChildren [
*136 (RefLabelRowHdr
)
*137 (TitleRowHdr
)
*138 (FilterRowHdr
)
*139 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*140 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*141 (GroupColHdr
tm "GroupColHdrMgr"
)
*142 (NameColHdr
tm "GenericNameColHdrMgr"
)
*143 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*144 (InitColHdr
tm "GenericValueColHdrMgr"
)
*145 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*146 (EolColHdr
tm "GenericEolColHdrMgr"
)
*147 (LogGeneric
generic (GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "14"
)
uid 2293,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 216,0
optionalChildren [
*148 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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emptyMRCItem *149 (MRCItem
litem &135
pos 3
dimension 20
)
uid 218,0
optionalChildren [
*150 (MRCItem
litem &136
pos 0
dimension 20
uid 219,0
)
*151 (MRCItem
litem &137
pos 1
dimension 23
uid 220,0
)
*152 (MRCItem
litem &138
pos 2
hidden 1
dimension 20
uid 221,0
)
*153 (MRCItem
litem &147
pos 0
dimension 20
uid 2294,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 222,0
optionalChildren [
*154 (MRCItem
litem &139
pos 0
dimension 20
uid 223,0
)
*155 (MRCItem
litem &141
pos 1
dimension 50
uid 224,0
)
*156 (MRCItem
litem &142
pos 2
dimension 100
uid 225,0
)
*157 (MRCItem
litem &143
pos 3
dimension 100
uid 226,0
)
*158 (MRCItem
litem &144
pos 4
dimension 50
uid 227,0
)
*159 (MRCItem
litem &145
pos 5
dimension 50
uid 228,0
)
*160 (MRCItem
litem &146
pos 6
dimension 80
uid 229,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 217,0
vaOverrides [
]
)
]
)
uid 203,0
type 1
)
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "symbol"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul"
)
(vvPair
variable "d_logical"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul"
)
(vvPair
variable "date"
value "27.07.2011"
)
(vvPair
variable "day"
value "Mi"
)
(vvPair
variable "day_long"
value "Mittwoch"
)
(vvPair
variable "dd"
value "27"
)
(vvPair
variable "entity_name"
value "w5300_modul"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "symbol.sb"
)
(vvPair
variable "f_logical"
value "symbol.sb"
)
(vvPair
variable "f_noext"
value "symbol"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "IHP110"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "07"
)
(vvPair
variable "module_name"
value "w5300_modul"
)
(vvPair
variable "month"
value "Jul"
)
(vvPair
variable "month_long"
value "Juli"
)
(vvPair
variable "p"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
)
(vvPair
variable "p_logical"
value "D:\\juli26\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\w5300_modul\\symbol.sb"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "D:\\modeltech_6.5e\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "sb"
)
(vvPair
variable "this_file"
value "symbol"
)
(vvPair
variable "this_file_logical"
value "symbol"
)
(vvPair
variable "time"
value "23:14:11"
)
(vvPair
variable "unit"
value "w5300_modul"
)
(vvPair
variable "user"
value "daqct3"
)
(vvPair
variable "version"
value "2009.1 (Build 12)"
)
(vvPair
variable "view"
value "symbol"
)
(vvPair
variable "year"
value "2011"
)
(vvPair
variable "yy"
value "11"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 173,0
optionalChildren [
*161 (SymbolBody
uid 8,0
optionalChildren [
*162 (CptPort
uid 48,0
ps "OnEdgeStrategy"
shape (Triangle
uid 49,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,3625,43000,4375"
)
tg (CPTG
uid 50,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 51,0
va (VaSet
)
xt "44000,3500,45500,4500"
st "clk"
blo "44000,4300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 52,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20800,29500,21600"
st "clk                           : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 7
suid 1,0
)
)
)
*163 (CptPort
uid 53,0
ps "OnEdgeStrategy"
shape (Triangle
uid 54,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,3625,77750,4375"
)
tg (CPTG
uid 55,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 56,0
va (VaSet
)
xt "71800,3500,76000,4500"
st "wiz_reset"
ju 2
blo "76000,4300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 57,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,21600,43000,22400"
st "wiz_reset                     : OUT    std_logic                      := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 2,0
i "'1'"
)
)
)
*164 (CptPort
uid 58,0
ps "OnEdgeStrategy"
shape (Triangle
uid 59,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,5625,77750,6375"
)
tg (CPTG
uid 60,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 61,0
va (VaSet
)
xt "73800,5500,76000,6500"
st "addr"
ju 2
blo "76000,6300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 62,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,22400,39000,23200"
st "addr                          : OUT    std_logic_vector (9 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 9
suid 3,0
)
)
)
*165 (CptPort
uid 63,0
ps "OnEdgeStrategy"
shape (Diamond
uid 64,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,7625,77750,8375"
)
tg (CPTG
uid 65,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 66,0
va (VaSet
)
xt "73900,7500,76000,8500"
st "data"
ju 2
blo "76000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 67,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,23200,39500,24000"
st "data                          : INOUT  std_logic_vector (15 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 10
suid 4,0
)
)
)
*166 (CptPort
uid 68,0
ps "OnEdgeStrategy"
shape (Triangle
uid 69,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,9625,77750,10375"
)
tg (CPTG
uid 70,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 71,0
va (VaSet
)
xt "74800,9500,76000,10500"
st "cs"
ju 2
blo "76000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 72,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24000,43000,24800"
st "cs                            : OUT    std_logic                      := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "cs"
t "std_logic"
preAdd 0
posAdd 0
o 11
suid 5,0
i "'1'"
)
)
)
*167 (CptPort
uid 73,0
ps "OnEdgeStrategy"
shape (Triangle
uid 74,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,11625,77750,12375"
)
tg (CPTG
uid 75,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 76,0
va (VaSet
)
xt "74600,11500,76000,12500"
st "wr"
ju 2
blo "76000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 77,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24800,43000,25600"
st "wr                            : OUT    std_logic                      := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 6,0
i "'1'"
)
)
)
*168 (CptPort
uid 83,0
ps "OnEdgeStrategy"
shape (Triangle
uid 84,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,15625,77750,16375"
)
tg (CPTG
uid 85,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 86,0
va (VaSet
)
xt "74700,15500,76000,16500"
st "rd"
ju 2
blo "76000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 87,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,26400,43000,27200"
st "rd                            : OUT    std_logic                      := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 8,0
i "'1'"
)
)
)
*169 (CptPort
uid 88,0
ps "OnEdgeStrategy"
shape (Triangle
uid 89,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,5625,43000,6375"
)
tg (CPTG
uid 90,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 91,0
va (VaSet
)
xt "44000,5500,45400,6500"
st "int"
blo "44000,6300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 92,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,27200,29500,28000"
st "int                           : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "int"
t "std_logic"
preAdd 0
posAdd 0
o 15
suid 9,0
)
)
)
*170 (CptPort
uid 93,0
ps "OnEdgeStrategy"
shape (Triangle
uid 94,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,7625,43000,8375"
)
tg (CPTG
uid 95,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 96,0
va (VaSet
)
xt "44000,7500,49700,8500"
st "write_length"
blo "44000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 97,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28000,39500,28800"
st "write_length                  : IN     std_logic_vector (16 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
preAdd 0
posAdd 0
o 16
suid 10,0
)
)
)
*171 (CptPort
uid 98,0
ps "OnEdgeStrategy"
shape (Triangle
uid 99,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,9625,43000,10375"
)
tg (CPTG
uid 100,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 101,0
va (VaSet
)
xt "44000,9500,51100,10500"
st "ram_start_addr"
blo "44000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 102,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,28800,46500,29600"
st "ram_start_addr                : IN     std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 17
suid 11,0
)
)
)
*172 (CptPort
uid 103,0
ps "OnEdgeStrategy"
shape (Triangle
uid 104,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,11625,43000,12375"
)
tg (CPTG
uid 105,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 106,0
va (VaSet
)
xt "44000,11500,48000,12500"
st "ram_data"
blo "44000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 107,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,29600,39500,30400"
st "ram_data                      : IN     std_logic_vector (15 DOWNTO 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 18
suid 12,0
)
)
)
*173 (CptPort
uid 108,0
ps "OnEdgeStrategy"
shape (Triangle
uid 109,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,17625,77750,18375"
)
tg (CPTG
uid 110,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 111,0
va (VaSet
)
xt "71900,17500,76000,18500"
st "ram_addr"
ju 2
blo "76000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 112,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,30400,46500,31200"
st "ram_addr                      : OUT    std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 19
suid 13,0
)
)
)
*174 (CptPort
uid 113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 114,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,13625,43000,14375"
)
tg (CPTG
uid 115,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 116,0
va (VaSet
)
xt "44000,13500,48800,14500"
st "data_valid"
blo "44000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 117,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,31200,29500,32000"
st "data_valid                    : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "data_valid"
t "std_logic"
preAdd 0
posAdd 0
o 20
suid 14,0
)
)
)
*175 (CptPort
uid 118,0
ps "OnEdgeStrategy"
shape (Triangle
uid 119,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,19625,77750,20375"
)
tg (CPTG
uid 120,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 121,0
va (VaSet
)
xt "73900,19500,76000,20500"
st "busy"
ju 2
blo "76000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 122,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32800,43000,33600"
st "busy                          : OUT    std_logic                      := '1' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "busy"
t "std_logic"
preAdd 0
posAdd 0
o 22
suid 15,0
i "'1'"
)
)
)
*176 (CommentText
uid 299,0
ps "EdgeToEdgeStrategy"
shape (Rectangle
uid 300,0
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,30800,15000,35800"
)
oxt "0,0,15000,5000"
text (MLText
uid 301,0
va (VaSet
fg "0,0,32768"
)
xt "200,31000,13900,35000"
st "

"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
included 1
excludeCommentLeader 1
)
*177 (CptPort
uid 348,0
ps "OnEdgeStrategy"
shape (Triangle
uid 349,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,14625,43000,15375"
)
tg (CPTG
uid 350,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 351,0
va (VaSet
)
xt "44000,14500,50600,15500"
st "write_end_flag"
blo "44000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 352,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,34400,29500,35200"
st "write_end_flag                : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "write_end_flag"
t "std_logic"
o 24
suid 18,0
)
)
)
*178 (CptPort
uid 353,0
ps "OnEdgeStrategy"
shape (Triangle
uid 354,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,15625,43000,16375"
)
tg (CPTG
uid 355,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 356,0
va (VaSet
)
xt "44000,15500,51900,16500"
st "write_header_flag"
blo "44000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 357,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,33600,29500,34400"
st "write_header_flag             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "write_header_flag"
t "std_logic"
o 23
suid 19,0
)
)
)
*179 (CptPort
uid 385,0
ps "OnEdgeStrategy"
shape (Triangle
uid 386,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,16625,43000,17375"
)
tg (CPTG
uid 387,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 388,0
va (VaSet
)
xt "44000,16500,49900,17500"
st "fifo_channels"
blo "44000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 389,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,35200,39000,36000"
st "fifo_channels                 : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 downto 0)"
posAdd 0
o 25
suid 20,0
)
)
)
*180 (CptPort
uid 491,0
ps "OnEdgeStrategy"
shape (Triangle
uid 492,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,20625,77750,21375"
)
tg (CPTG
uid 493,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 494,0
va (VaSet
)
xt "74500,20500,76000,21500"
st "led"
ju 2
blo "76000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 495,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25600,49000,26400"
st "led                           : OUT    std_logic_vector (7 DOWNTO 0)  := (OTHERS => '0') ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 13
suid 22,0
i "(OTHERS => '0')"
)
)
)
*181 (CptPort
uid 521,0
ps "OnEdgeStrategy"
shape (Triangle
uid 522,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,21625,77750,22375"
)
tg (CPTG
uid 523,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 524,0
va (VaSet
)
xt "72100,21500,76000,22500"
st "s_trigger"
ju 2
blo "76000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 525,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,36000,43000,37600"
st "-- softtrigger:
s_trigger                     : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "s_trigger"
t "std_logic"
prec "-- softtrigger:"
preAdd 0
o 26
suid 23,0
i "'0'"
)
)
)
*182 (CptPort
uid 670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,27625,77750,28375"
)
tg (CPTG
uid 672,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 673,0
va (VaSet
)
xt "72800,27500,76000,28500"
st "denable"
ju 2
blo "76000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 674,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,59200,87500,60000"
st "denable                       : OUT    std_logic                      := '0' ; -- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override.
"
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave on. ... in case if REFCLK error ... REFCLK counter will override."
preAdd 0
posAdd 0
o 42
suid 31,0
i "'0'"
)
)
)
*183 (CptPort
uid 723,0
ps "OnEdgeStrategy"
shape (Triangle
uid 724,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,28625,77750,29375"
)
tg (CPTG
uid 725,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 726,0
va (VaSet
)
xt "69800,28500,76000,29500"
st "dwrite_enable"
ju 2
blo "76000,29300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 727,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,60000,54500,60800"
st "dwrite_enable                 : OUT    std_logic                      := '1' ; -- default DWRITE low.
"
)
thePort (LogicalPort
m 1
decl (Decl
n "dwrite_enable"
t "std_logic"
eolc "-- default DWRITE low."
preAdd 0
posAdd 0
o 43
suid 32,0
i "'1'"
)
)
)
*184 (CptPort
uid 885,0
ps "OnEdgeStrategy"
shape (Triangle
uid 886,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,29625,77750,30375"
)
tg (CPTG
uid 887,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 888,0
va (VaSet
)
xt "69400,29500,76000,30500"
st "data_valid_ack"
ju 2
blo "76000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 889,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,32000,43000,32800"
st "data_valid_ack                : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid_ack"
t "std_logic"
o 21
suid 34,0
i "'0'"
)
)
)
*185 (CptPort
uid 917,0
ps "OnEdgeStrategy"
shape (Triangle
uid 918,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,30625,77750,31375"
)
tg (CPTG
uid 919,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 920,0
va (VaSet
)
xt "70800,30500,76000,31500"
st "sclk_enable"
ju 2
blo "76000,31300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 921,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,60800,55000,61600"
st "sclk_enable                   : OUT    std_logic                      := '1' ; -- default DWRITE HIGH.
"
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk_enable"
t "std_logic"
eolc "-- default DWRITE HIGH."
posAdd 0
o 44
suid 35,0
i "'1'"
)
)
)
*186 (CptPort
uid 949,0
ps "OnEdgeStrategy"
shape (Triangle
uid 950,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,31625,77750,32375"
)
tg (CPTG
uid 951,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 952,0
va (VaSet
)
xt "70500,31500,76000,32500"
st "ps_direction"
ju 2
blo "76000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 953,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,64800,58500,69600"
st "------------------------------------------------------------------------------

-- ADC CLK generator, is able to shift phase with respect to X_50M
-- these signals control the behavior of the digital clock manager (DCM)
------------------------------------------------------------------------------
ps_direction                  : OUT    std_logic                      := '1' ; -- default phase shift upwards
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_direction"
t "std_logic"
prec "------------------------------------------------------------------------------

-- ADC CLK generator, is able to shift phase with respect to X_50M
-- these signals control the behavior of the digital clock manager (DCM)
------------------------------------------------------------------------------"
eolc "-- default phase shift upwards"
preAdd 0
posAdd 0
o 49
suid 36,0
i "'1'"
)
)
)
*187 (CptPort
uid 954,0
ps "OnEdgeStrategy"
shape (Triangle
uid 955,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,32625,77750,33375"
)
tg (CPTG
uid 956,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 957,0
va (VaSet
)
xt "67900,32500,76000,33500"
st "ps_do_phase_shift"
ju 2
blo "76000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 958,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,69600,59500,70400"
st "ps_do_phase_shift             : OUT    std_logic                      := '0' ; --pulse this to phase shift once
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_do_phase_shift"
t "std_logic"
eolc "--pulse this to phase shift once"
preAdd 0
posAdd 0
o 50
suid 37,0
i "'0'"
)
)
)
*188 (CptPort
uid 988,0
ps "OnEdgeStrategy"
shape (Triangle
uid 989,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,33625,77750,34375"
)
tg (CPTG
uid 990,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 991,0
va (VaSet
)
xt "72300,33500,76000,34500"
st "ps_reset"
ju 2
blo "76000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 992,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,70400,67000,71200"
st "ps_reset                      : OUT    std_logic                      := '0' ; -- pulse this to reset the variable phase shift
"
)
thePort (LogicalPort
m 1
decl (Decl
n "ps_reset"
t "std_logic"
eolc "-- pulse this to reset the variable phase shift"
posAdd 0
o 51
suid 38,0
i "'0'"
)
)
)
*189 (CptPort
uid 1020,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1021,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,34625,77750,35375"
)
tg (CPTG
uid 1022,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1023,0
va (VaSet
)
xt "70400,34500,76000,35500"
st "srclk_enable"
ju 2
blo "76000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1024,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,61600,53500,62400"
st "srclk_enable                  : OUT    std_logic                      := '1' ; -- default SRCLK on.
"
)
thePort (LogicalPort
m 1
decl (Decl
n "srclk_enable"
t "std_logic"
eolc "-- default SRCLK on."
posAdd 0
o 45
suid 39,0
i "'1'"
)
)
)
*190 (CptPort
uid 1091,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1092,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,35625,77750,36375"
)
tg (CPTG
uid 1093,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1094,0
va (VaSet
)
xt "68800,35500,76000,36500"
st "socks_connected"
ju 2
blo "76000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1095,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,76800,43000,78400"
st "socks_connected               : OUT    std_logic 
------------------------------------------------------------------------------
"
)
thePort (LogicalPort
m 1
decl (Decl
n "socks_connected"
t "std_logic"
posc "------------------------------------------------------------------------------"
posAdd 0
o 54
suid 42,0
)
)
)
*191 (CptPort
uid 1096,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1097,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,36625,77750,37375"
)
tg (CPTG
uid 1098,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1099,0
va (VaSet
)
xt "69900,36500,76000,37500"
st "socks_waiting"
ju 2
blo "76000,37300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1100,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,72000,43000,76800"
st "------------------------------------------------------------------------------

-- signals used to control FAD LED bahavior:
-- one of the three LEDs is used for com-status info
------------------------------------------------------------------------------
socks_waiting                 : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "socks_waiting"
t "std_logic"
prec "------------------------------------------------------------------------------

-- signals used to control FAD LED bahavior:
-- one of the three LEDs is used for com-status info
------------------------------------------------------------------------------"
preAdd 0
o 53
suid 43,0
)
)
)
*192 (CptPort
uid 1130,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1131,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,37625,77750,38375"
)
tg (CPTG
uid 1132,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1133,0
va (VaSet
)
xt "69700,37500,76000,38500"
st "trigger_enable"
ju 2
blo "76000,38300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1134,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,55200,43000,59200"
st "------------------------------------------------------------------------------

-- user controllable enable signals
------------------------------------------------------------------------------
trigger_enable                : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "trigger_enable"
t "std_logic"
prec "------------------------------------------------------------------------------

-- user controllable enable signals
------------------------------------------------------------------------------"
preAdd 0
posAdd 0
o 41
suid 44,0
)
)
)
*193 (CptPort
uid 1187,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1188,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,38625,77750,39375"
)
tg (CPTG
uid 1189,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1190,0
va (VaSet
)
xt "68800,38500,76000,39500"
st "c_trigger_enable"
ju 2
blo "76000,39300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1191,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,37600,43000,38400"
st "c_trigger_enable              : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "c_trigger_enable"
t "std_logic"
o 27
suid 45,0
i "'0'"
)
)
)
*194 (CptPort
uid 1192,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1193,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,39625,77750,40375"
)
tg (CPTG
uid 1194,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1195,0
va (VaSet
)
xt "69500,39500,76000,40500"
st "c_trigger_mult"
ju 2
blo "76000,40300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1196,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,38400,66000,39200"
st "c_trigger_mult                : OUT    std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16) ; --subject to changes
"
)
thePort (LogicalPort
m 1
decl (Decl
n "c_trigger_mult"
t "std_logic_vector"
b "(15 DOWNTO 0)"
eolc "--subject to changes"
posAdd 0
o 28
suid 46,0
i "conv_std_logic_vector(0 ,16)"
)
)
)
*195 (CptPort
uid 1283,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1284,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,21625,43000,22375"
)
tg (CPTG
uid 1285,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1286,0
va (VaSet
)
xt "44000,21500,49700,22500"
st "MAC_jumper"
blo "44000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1287,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,49600,43000,53600"
st "------------------------------------------------------------------------------

-- MAC/IP calculation signals:
------------------------------------------------------------------------------
MAC_jumper                    : IN     std_logic_vector (1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "MAC_jumper"
t "std_logic_vector"
b "(1 downto 0)"
prec "------------------------------------------------------------------------------

-- MAC/IP calculation signals:
------------------------------------------------------------------------------"
preAdd 0
o 38
suid 48,0
)
)
)
*196 (CptPort
uid 1315,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1316,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,22625,43000,23375"
)
tg (CPTG
uid 1317,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1318,0
va (VaSet
)
xt "44000,22500,47600,23500"
st "BoardID"
blo "44000,23300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1319,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,53600,39000,54400"
st "BoardID                       : IN     std_logic_vector (3 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "BoardID"
t "std_logic_vector"
b "(3 downto 0)"
o 39
suid 49,0
)
)
)
*197 (CptPort
uid 1320,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1321,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,23625,43000,24375"
)
tg (CPTG
uid 1322,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1323,0
va (VaSet
)
xt "44000,23500,47500,24500"
st "CrateID"
blo "44000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1324,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,54400,39000,55200"
st "CrateID                       : IN     std_logic_vector (1 downto 0) ;
"
)
thePort (LogicalPort
decl (Decl
n "CrateID"
t "std_logic_vector"
b "(1 downto 0)"
posAdd 0
o 40
suid 50,0
)
)
)
*198 (CptPort
uid 1550,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1551,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,41625,77750,42375"
)
tg (CPTG
uid 1552,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1553,0
va (VaSet
)
xt "70700,41500,76000,42500"
st "dac_setting"
ju 2
blo "76000,42300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1554,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,44000,70000,46400"
st "--data_generator_config_start_o   : out std_logic := '0';
--data_generator_config_valid_i   : in std_logic;
dac_setting                   : OUT    dac_array_type                 := DEFAULT_DAC ; --<<-- default defined in fad_definitions.vhd
"
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_setting"
t "dac_array_type"
prec "--data_generator_config_start_o   : out std_logic := '0';
--data_generator_config_valid_i : in std_logic;"
eolc "--<<-- default defined in fad_definitions.vhd"
preAdd 0
posAdd 0
o 33
suid 54,0
i "DEFAULT_DAC"
)
)
)
*199 (CptPort
uid 1575,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1576,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,43625,77750,44375"
)
tg (CPTG
uid 1577,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1578,0
va (VaSet
)
xt "62200,43500,76000,44500"
st "memory_manager_config_start_o"
ju 2
blo "76000,44300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1579,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,39200,43000,41600"
st "-- FAD configuration signals:
------------------------------------------------------------------------------
memory_manager_config_start_o : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "memory_manager_config_start_o"
t "std_logic"
prec "-- FAD configuration signals:
------------------------------------------------------------------------------"
preAdd 0
o 29
suid 59,0
i "'0'"
)
)
)
*200 (CptPort
uid 1580,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1581,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,29625,43000,30375"
)
tg (CPTG
uid 1582,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1583,0
va (VaSet
)
xt "44000,29500,57300,30500"
st "memory_manager_config_valid_i"
blo "44000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1584,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,41600,29500,42400"
st "memory_manager_config_valid_i : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "memory_manager_config_valid_i"
t "std_logic"
o 30
suid 60,0
)
)
)
*201 (CptPort
uid 1585,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1586,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,44625,77750,45375"
)
tg (CPTG
uid 1587,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1588,0
va (VaSet
)
xt "71000,44500,76000,45500"
st "roi_setting"
ju 2
blo "76000,45300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1589,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,46400,70000,47200"
st "roi_setting                   : OUT    roi_array_type                 := DEFAULT_ROI ; --<<-- default defined in fad_definitions.vhd
"
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_setting"
t "roi_array_type"
eolc "--<<-- default defined in fad_definitions.vhd"
preAdd 0
posAdd 0
o 34
suid 61,0
i "DEFAULT_ROI"
)
)
)
*202 (CptPort
uid 1595,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1596,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,45625,77750,46375"
)
tg (CPTG
uid 1597,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1598,0
va (VaSet
)
xt "63600,45500,76000,46500"
st "spi_interface_config_start_o"
ju 2
blo "76000,46300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1599,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,42400,43000,43200"
st "spi_interface_config_start_o  : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "spi_interface_config_start_o"
t "std_logic"
o 31
suid 63,0
i "'0'"
)
)
)
*203 (CptPort
uid 1600,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1601,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,31625,43000,32375"
)
tg (CPTG
uid 1602,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1603,0
va (VaSet
)
xt "44000,31500,55900,32500"
st "spi_interface_config_valid_i"
blo "44000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1604,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,43200,29500,44000"
st "spi_interface_config_valid_i  : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "spi_interface_config_valid_i"
t "std_logic"
posAdd 0
o 32
suid 64,0
)
)
)
*204 (CptPort
uid 1802,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1803,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,32625,43000,33375"
)
tg (CPTG
uid 1804,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1805,0
va (VaSet
)
xt "44000,32500,51200,33500"
st "data_ram_empty"
blo "44000,33300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1806,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,48800,29500,49600"
st "data_ram_empty                : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "data_ram_empty"
t "std_logic"
preAdd 0
o 37
suid 65,0
)
)
)
*205 (CptPort
uid 1834,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1835,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,33625,43000,34375"
)
tg (CPTG
uid 1836,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1837,0
va (VaSet
)
xt "44000,33500,47800,34500"
st "ps_ready"
blo "44000,34300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1838,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,71200,29500,72000"
st "ps_ready                      : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "ps_ready"
t "std_logic"
o 52
suid 66,0
)
)
)
*206 (CptPort
uid 1891,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1892,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,46625,77750,47375"
)
tg (CPTG
uid 1893,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1894,0
va (VaSet
)
xt "71700,46500,76000,47500"
st "runnumber"
ju 2
blo "76000,47300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1895,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,47200,55500,48000"
st "runnumber                     : OUT    std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,32) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "runnumber"
t "std_logic_vector"
b "(31 DOWNTO 0)"
o 35
suid 67,0
i "conv_std_logic_vector(0 ,32)"
)
)
)
*207 (CptPort
uid 1923,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1924,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,47625,77750,48375"
)
tg (CPTG
uid 1925,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1926,0
va (VaSet
)
xt "68800,47500,76000,48500"
st "reset_trigger_id"
ju 2
blo "76000,48300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1927,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,48000,43000,48800"
st "reset_trigger_id              : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "reset_trigger_id"
t "std_logic"
o 36
suid 68,0
i "'0'"
)
)
)
*208 (CptPort
uid 1955,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1956,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,48625,77750,49375"
)
tg (CPTG
uid 1957,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1958,0
va (VaSet
)
xt "73600,48500,76000,49500"
st "state"
ju 2
blo "76000,49300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1959,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16000,64500,16800"
st "state                         : OUT    std_logic_vector (7 DOWNTO 0) ; -- state is encoded here ... useful for debugging.
"
)
thePort (LogicalPort
m 1
decl (Decl
n "state"
t "std_logic_vector"
b "(7 DOWNTO 0)"
eolc "-- state is encoded here ... useful for debugging."
posAdd 0
o 1
suid 69,0
)
)
)
*209 (CptPort
uid 2012,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2013,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,49625,77750,50375"
)
tg (CPTG
uid 2014,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2015,0
va (VaSet
)
xt "65600,49500,76000,50500"
st "debug_data_ram_empty"
ju 2
blo "76000,50300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2016,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16800,29500,17600"
st "debug_data_ram_empty          : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_ram_empty"
t "std_logic"
o 2
suid 70,0
)
)
)
*210 (CptPort
uid 2017,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2018,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,50625,77750,51375"
)
tg (CPTG
uid 2019,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2020,0
va (VaSet
)
xt "68500,50500,76000,51500"
st "debug_data_valid"
ju 2
blo "76000,51300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2021,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,17600,29500,18400"
st "debug_data_valid              : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "debug_data_valid"
t "std_logic"
o 3
suid 71,0
)
)
)
*211 (CptPort
uid 2051,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2052,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,34625,43000,35375"
)
tg (CPTG
uid 2053,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2054,0
va (VaSet
)
xt "44000,34500,53700,35500"
st "data_generator_idle_i"
blo "44000,35300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2055,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,18400,29500,19200"
st "data_generator_idle_i         : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "data_generator_idle_i"
t "std_logic"
o 4
suid 72,0
)
)
)
*212 (CptPort
uid 2133,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2134,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,51625,77750,52375"
)
tg (CPTG
uid 2135,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2136,0
va (VaSet
)
xt "67400,51500,76000,52500"
st "socket_tx_free_out"
ju 2
blo "76000,52300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2137,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20000,54500,20800"
st "socket_tx_free_out            : OUT    std_logic_vector (16 DOWNTO 0) ; -- 17bit value .. that's true
"
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_tx_free_out"
t "std_logic_vector"
b "(16 DOWNTO 0)"
eolc "-- 17bit value .. that's true"
posAdd 0
o 6
suid 73,0
)
)
)
*213 (CptPort
uid 2165,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2166,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,52625,77750,53375"
)
tg (CPTG
uid 2167,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2168,0
va (VaSet
)
xt "70600,52500,76000,53500"
st "busy_enable"
ju 2
blo "76000,53300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2169,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,62400,43000,63200"
st "busy_enable                   : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "busy_enable"
t "std_logic"
o 46
suid 74,0
i "'0'"
)
)
)
*214 (CptPort
uid 2170,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2171,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,53625,77750,54375"
)
tg (CPTG
uid 2172,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2173,0
va (VaSet
)
xt "65800,53500,76000,54500"
st "socket_send_mode_out"
ju 2
blo "76000,54300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2174,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,63200,29500,64000"
st "socket_send_mode_out          : OUT    std_logic  ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "socket_send_mode_out"
t "std_logic"
o 47
suid 75,0
)
)
)
*215 (CptPort
uid 2229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2230,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77000,54625,77750,55375"
)
tg (CPTG
uid 2231,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2232,0
va (VaSet
)
xt "70500,54500,76000,55500"
st "busy_manual"
ju 2
blo "76000,55300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2233,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,64000,43000,64800"
st "busy_manual                   : OUT    std_logic                      := '0' ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "busy_manual"
t "std_logic"
o 48
suid 76,0
i "'0'"
)
)
)
*216 (CptPort
uid 2234,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2235,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "42250,35625,43000,36375"
)
tg (CPTG
uid 2236,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2237,0
va (VaSet
)
xt "44000,35500,51900,36500"
st "data_ram_not_full"
blo "44000,36300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 2238,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,19200,29500,20000"
st "data_ram_not_full             : IN     std_logic  ;
"
)
thePort (LogicalPort
decl (Decl
n "data_ram_not_full"
t "std_logic"
o 5
suid 77,0
)
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "43000,2000,77000,56000"
)
oxt "43000,2000,56000,22000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "47700,11000,53900,12000"
st "FACT_FAD_lib"
blo "47700,11800"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "47700,12000,53400,13000"
st "w5300_modul"
blo "47700,12800"
)
)
gi *217 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
font "Courier New,8,0"
)
xt "43000,200,58000,2600"
st "Generic Declarations

RAM_ADDR_WIDTH integer 14  
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)
header "Generic Declarations"
showHdrWhenContentsEmpty 1
)
elements [
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name "RAM_ADDR_WIDTH"
type "integer"
value "14"
)
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sIVOD 1
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
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uid 16,0
optionalChildren [
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vasetType 1
fg "65280,65280,46080"
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xt "47000,30000,64000,31000"
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oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "47200,30000,57900,31000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
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position 1
ignorePrefs 1
titleBlock 1
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uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "64000,26000,68000,27000"
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oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "64200,26000,67500,27000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
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position 1
ignorePrefs 1
titleBlock 1
)
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uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "47000,28000,64000,29000"
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oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "47200,28000,58100,29000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
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position 1
ignorePrefs 1
titleBlock 1
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shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "43000,28000,47000,29000"
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oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "43200,28000,45500,29000"
st "
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tm "CommentText"
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position 1
ignorePrefs 1
titleBlock 1
)
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shape (Rectangle
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fg "65280,65280,46080"
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xt "64000,27000,84000,31000"
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oxt "35000,67000,55000,71000"
text (MLText
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va (VaSet
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bg "0,0,32768"
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xt "64200,27200,74000,28200"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
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ignorePrefs 1
titleBlock 1
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shape (Rectangle
uid 34,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "68000,26000,84000,27000"
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oxt "39000,66000,55000,67000"
text (MLText
uid 35,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "68200,26000,72900,27000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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position 1
ignorePrefs 1
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shape (Rectangle
uid 37,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "43000,26000,64000,28000"
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oxt "14000,66000,35000,68000"
text (MLText
uid 38,0
va (VaSet
fg "32768,0,0"
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xt "50200,26500,56800,27500"
st "
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ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
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position 1
ignorePrefs 1
titleBlock 1
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shape (Rectangle
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va (VaSet
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xt "43000,29000,47000,30000"
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oxt "14000,69000,18000,70000"
text (MLText
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xt "43200,29000,45500,30000"
st "
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tm "CommentText"
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xt "43000,30000,47000,31000"
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text (MLText
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xt "43200,30000,46300,31000"
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tm "CommentText"
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text (MLText
uid 47,0
va (VaSet
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bg "0,0,32768"
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xt "47200,29000,62800,30000"
st "
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tm "CommentText"
wrapOption 3
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position 1
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shape (GroupingShape
uid 17,0
va (VaSet
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fg "65535,65535,65535"
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xt "43000,26000,84000,31000"
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xt "200,-5800,32200,-600"
st "
Created using Mentor Graphics HDL2Graphics(TM) Technology
on - 10:21:37 04.02.2010
from - D:\\E5b\\E5b_09_189\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl\\w5300_modul.vhd

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tm "CommentText"
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st "library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library FACT_FAD_lib;
use FACT_FAD_lib.fad_definitions.ALL;"
tm "PackageList"
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