1 | -- VHDL Entity FACT_FAD_lib.clock_generator_var_ps.symbol
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2 | --
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3 | -- Created:
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4 | -- by - dneise.UNKNOWN (E5B-LABOR6)
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5 | -- at - 10:49:24 30.08.2010
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6 | --
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7 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
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8 | --
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9 | LIBRARY ieee;
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10 | USE ieee.std_logic_1164.all;
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11 | USE ieee.std_logic_arith.all;
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12 |
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13 | ENTITY clock_generator_var_ps IS
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14 | PORT(
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15 | CLK : IN std_logic;
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16 | RST_IN : IN std_logic;
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17 | direction : IN std_logic;
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18 | do_shift : IN std_logic;
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19 | CLK_25 : OUT std_logic;
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20 | CLK_25_PS : OUT std_logic;
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21 | CLK_50 : OUT std_logic;
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22 | DCM_locked : OUT std_logic;
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23 | LOCKED_extraOUT : OUT std_logic;
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24 | PSCLK_OUT : OUT std_logic;
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25 | PSDONE_extraOUT : OUT std_logic;
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26 | PSEN_OUT : OUT std_logic;
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27 | PSINCDEC_OUT : OUT std_logic;
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28 | offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
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29 | ready : OUT std_logic := '0';
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30 | -- status:
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31 | shifting : OUT std_logic := '0'
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32 | );
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33 |
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34 | -- Declarations
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35 |
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36 | END clock_generator_var_ps ;
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37 |
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38 | --
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39 | -- VHDL Architecture FACT_FAD_lib.clock_generator_var_ps.struct
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40 | --
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41 | -- Created:
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42 | -- by - dneise.UNKNOWN (E5B-LABOR6)
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43 | -- at - 10:49:25 30.08.2010
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44 | --
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45 | -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
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46 | --
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47 | LIBRARY ieee;
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48 | USE ieee.std_logic_1164.all;
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49 | USE ieee.std_logic_arith.all;
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50 | USE ieee.numeric_std.all;
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51 | LIBRARY UNISIM;
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52 | USE UNISIM.Vcomponents.all;
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53 |
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54 | LIBRARY FACT_FAD_lib;
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55 |
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56 | ARCHITECTURE struct OF clock_generator_var_ps IS
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57 |
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58 | -- Architecture declarations
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59 |
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60 | -- Internal signal declarations
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61 | SIGNAL CLK0_OUT : std_logic;
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62 | SIGNAL LOCKED_OUT : std_logic;
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63 | SIGNAL PSCLK_IN : std_logic;
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64 | SIGNAL PSDONE_OUT : std_logic;
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65 | SIGNAL PSEN_IN : std_logic;
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66 | SIGNAL PSINCDEC_IN : std_logic;
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67 |
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68 | -- Implicit buffer signal declarations
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69 | SIGNAL CLK_25_internal : std_logic;
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70 |
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71 |
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72 | -- Component Declarations
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73 | COMPONENT dcm_50_to_25
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74 | PORT (
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75 | CLKIN_IN : IN std_logic;
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76 | CLK0_OUT : OUT std_logic;
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77 | CLKFX_OUT : OUT std_logic;
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78 | CLKIN_IBUFG_OUT : OUT std_logic
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79 | );
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80 | END COMPONENT;
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81 | COMPONENT dcm_ps_38ns
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82 | PORT (
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83 | CLKIN_IN : IN std_logic;
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84 | CLK0_OUT : OUT std_logic
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85 | );
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86 | END COMPONENT;
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87 | COMPONENT dcm_var_ps_38ns
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88 | PORT (
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89 | CLKIN_IN : IN std_logic;
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90 | PSCLK_IN : IN std_logic;
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91 | PSEN_IN : IN std_logic;
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92 | PSINCDEC_IN : IN std_logic;
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93 | RST_IN : IN std_logic;
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94 | CLK0_OUT : OUT std_logic;
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95 | LOCKED_OUT : OUT std_logic;
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96 | PSDONE_OUT : OUT std_logic
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97 | );
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98 | END COMPONENT;
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99 | COMPONENT phase_shifter
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100 | PORT (
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101 | CLK : IN std_logic ;
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102 | -- interface to: clock_generator_variable_PS_struct.vhd
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103 | PSCLK : OUT std_logic ;
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104 | PSEN : OUT std_logic := '0';
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105 | PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing'
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106 | PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done.
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107 | LOCKED : IN std_logic ;
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108 | -- interface to: w5300_modul.vhd
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109 | shift_phase : IN std_logic ;
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110 | direction : IN std_logic ; -- corresponds TO 'PSINCDEC'
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111 | -- status:
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112 | shifting : OUT std_logic := '0';
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113 | ready : OUT std_logic := '0';
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114 | offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
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115 | DCM_locked : OUT std_logic
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116 | );
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117 | END COMPONENT;
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118 |
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119 | -- Optional embedded configurations
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120 | -- pragma synthesis_off
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121 | FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25;
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122 | FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns;
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123 | FOR ALL : dcm_var_ps_38ns USE ENTITY FACT_FAD_lib.dcm_var_ps_38ns;
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124 | FOR ALL : phase_shifter USE ENTITY FACT_FAD_lib.phase_shifter;
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125 | -- pragma synthesis_on
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126 |
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127 |
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128 | BEGIN
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129 |
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130 | -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
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131 | PSCLK_OUT <= PSCLK_IN;
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132 |
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133 | -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
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134 | PSEN_OUT <= PSEN_IN;
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135 |
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136 | -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
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137 | PSINCDEC_OUT <= PSINCDEC_IN;
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138 |
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139 | -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
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140 | PSDONE_extraOUT <= PSDONE_OUT;
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141 |
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142 | -- ModuleWare code(v1.9) for instance 'U_9' of 'assignment'
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143 | LOCKED_extraOUT <= LOCKED_OUT;
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144 |
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145 | -- Instance port mappings.
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146 | U_0 : dcm_50_to_25
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147 | PORT MAP (
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148 | CLKIN_IN => CLK,
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149 | CLKFX_OUT => CLK_25_internal,
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150 | CLKIN_IBUFG_OUT => OPEN,
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151 | CLK0_OUT => CLK_50
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152 | );
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153 | U_1 : dcm_ps_38ns
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154 | PORT MAP (
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155 | CLKIN_IN => CLK_25_internal,
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156 | CLK0_OUT => CLK0_OUT
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157 | );
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158 | U_2 : dcm_var_ps_38ns
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159 | PORT MAP (
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160 | CLKIN_IN => CLK0_OUT,
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161 | PSCLK_IN => PSCLK_IN,
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162 | PSEN_IN => PSEN_IN,
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163 | PSINCDEC_IN => PSINCDEC_IN,
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164 | RST_IN => RST_IN,
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165 | CLK0_OUT => CLK_25_PS,
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166 | LOCKED_OUT => LOCKED_OUT,
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167 | PSDONE_OUT => PSDONE_OUT
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168 | );
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169 | U_4 : phase_shifter
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170 | PORT MAP (
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171 | CLK => CLK0_OUT,
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172 | PSCLK => PSCLK_IN,
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173 | PSEN => PSEN_IN,
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174 | PSINCDEC => PSINCDEC_IN,
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175 | PSDONE => PSDONE_OUT,
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176 | LOCKED => LOCKED_OUT,
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177 | shift_phase => do_shift,
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178 | direction => direction,
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179 | shifting => shifting,
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180 | ready => ready,
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181 | offset => offset,
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182 | DCM_locked => DCM_locked
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183 | );
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184 |
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185 | -- Implicit buffered output assignments
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186 | CLK_25 <= CLK_25_internal;
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187 |
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188 | END struct;
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