source: firmware/FAD/FAD_svn_revision_number/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd@ 9914

Last change on this file since 9914 was 9914, checked in by neise, 15 years ago
initial commit of version with svn revision as event package type
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1-- VHDL Entity FACT_FAD_lib.clock_generator_var_ps.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 10:49:24 30.08.2010
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY clock_generator_var_ps IS
14 PORT(
15 CLK : IN std_logic;
16 RST_IN : IN std_logic;
17 direction : IN std_logic;
18 do_shift : IN std_logic;
19 CLK_25 : OUT std_logic;
20 CLK_25_PS : OUT std_logic;
21 CLK_50 : OUT std_logic;
22 DCM_locked : OUT std_logic;
23 LOCKED_extraOUT : OUT std_logic;
24 PSCLK_OUT : OUT std_logic;
25 PSDONE_extraOUT : OUT std_logic;
26 PSEN_OUT : OUT std_logic;
27 PSINCDEC_OUT : OUT std_logic;
28 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
29 ready : OUT std_logic := '0';
30 -- status:
31 shifting : OUT std_logic := '0'
32 );
33
34-- Declarations
35
36END clock_generator_var_ps ;
37
38--
39-- VHDL Architecture FACT_FAD_lib.clock_generator_var_ps.struct
40--
41-- Created:
42-- by - dneise.UNKNOWN (E5B-LABOR6)
43-- at - 10:49:25 30.08.2010
44--
45-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
46--
47LIBRARY ieee;
48USE ieee.std_logic_1164.all;
49USE ieee.std_logic_arith.all;
50USE ieee.numeric_std.all;
51LIBRARY UNISIM;
52USE UNISIM.Vcomponents.all;
53
54LIBRARY FACT_FAD_lib;
55
56ARCHITECTURE struct OF clock_generator_var_ps IS
57
58 -- Architecture declarations
59
60 -- Internal signal declarations
61 SIGNAL CLK0_OUT : std_logic;
62 SIGNAL LOCKED_OUT : std_logic;
63 SIGNAL PSCLK_IN : std_logic;
64 SIGNAL PSDONE_OUT : std_logic;
65 SIGNAL PSEN_IN : std_logic;
66 SIGNAL PSINCDEC_IN : std_logic;
67
68 -- Implicit buffer signal declarations
69 SIGNAL CLK_25_internal : std_logic;
70
71
72 -- Component Declarations
73 COMPONENT dcm_50_to_25
74 PORT (
75 CLKIN_IN : IN std_logic;
76 CLK0_OUT : OUT std_logic;
77 CLKFX_OUT : OUT std_logic;
78 CLKIN_IBUFG_OUT : OUT std_logic
79 );
80 END COMPONENT;
81 COMPONENT dcm_ps_38ns
82 PORT (
83 CLKIN_IN : IN std_logic;
84 CLK0_OUT : OUT std_logic
85 );
86 END COMPONENT;
87 COMPONENT dcm_var_ps_38ns
88 PORT (
89 CLKIN_IN : IN std_logic;
90 PSCLK_IN : IN std_logic;
91 PSEN_IN : IN std_logic;
92 PSINCDEC_IN : IN std_logic;
93 RST_IN : IN std_logic;
94 CLK0_OUT : OUT std_logic;
95 LOCKED_OUT : OUT std_logic;
96 PSDONE_OUT : OUT std_logic
97 );
98 END COMPONENT;
99 COMPONENT phase_shifter
100 PORT (
101 CLK : IN std_logic ;
102 -- interface to: clock_generator_variable_PS_struct.vhd
103 PSCLK : OUT std_logic ;
104 PSEN : OUT std_logic := '0';
105 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing'
106 PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done.
107 LOCKED : IN std_logic ;
108 -- interface to: w5300_modul.vhd
109 shift_phase : IN std_logic ;
110 direction : IN std_logic ; -- corresponds TO 'PSINCDEC'
111 -- status:
112 shifting : OUT std_logic := '0';
113 ready : OUT std_logic := '0';
114 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
115 DCM_locked : OUT std_logic
116 );
117 END COMPONENT;
118
119 -- Optional embedded configurations
120 -- pragma synthesis_off
121 FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25;
122 FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns;
123 FOR ALL : dcm_var_ps_38ns USE ENTITY FACT_FAD_lib.dcm_var_ps_38ns;
124 FOR ALL : phase_shifter USE ENTITY FACT_FAD_lib.phase_shifter;
125 -- pragma synthesis_on
126
127
128BEGIN
129
130 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
131 PSCLK_OUT <= PSCLK_IN;
132
133 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
134 PSEN_OUT <= PSEN_IN;
135
136 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
137 PSINCDEC_OUT <= PSINCDEC_IN;
138
139 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
140 PSDONE_extraOUT <= PSDONE_OUT;
141
142 -- ModuleWare code(v1.9) for instance 'U_9' of 'assignment'
143 LOCKED_extraOUT <= LOCKED_OUT;
144
145 -- Instance port mappings.
146 U_0 : dcm_50_to_25
147 PORT MAP (
148 CLKIN_IN => CLK,
149 CLKFX_OUT => CLK_25_internal,
150 CLKIN_IBUFG_OUT => OPEN,
151 CLK0_OUT => CLK_50
152 );
153 U_1 : dcm_ps_38ns
154 PORT MAP (
155 CLKIN_IN => CLK_25_internal,
156 CLK0_OUT => CLK0_OUT
157 );
158 U_2 : dcm_var_ps_38ns
159 PORT MAP (
160 CLKIN_IN => CLK0_OUT,
161 PSCLK_IN => PSCLK_IN,
162 PSEN_IN => PSEN_IN,
163 PSINCDEC_IN => PSINCDEC_IN,
164 RST_IN => RST_IN,
165 CLK0_OUT => CLK_25_PS,
166 LOCKED_OUT => LOCKED_OUT,
167 PSDONE_OUT => PSDONE_OUT
168 );
169 U_4 : phase_shifter
170 PORT MAP (
171 CLK => CLK0_OUT,
172 PSCLK => PSCLK_IN,
173 PSEN => PSEN_IN,
174 PSINCDEC => PSINCDEC_IN,
175 PSDONE => PSDONE_OUT,
176 LOCKED => LOCKED_OUT,
177 shift_phase => do_shift,
178 direction => direction,
179 shifting => shifting,
180 ready => ready,
181 offset => offset,
182 DCM_locked => DCM_locked
183 );
184
185 -- Implicit buffered output assignments
186 CLK_25 <= CLK_25_internal;
187
188END struct;
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