source: firmware/FAD/FAD_svn_revision_number/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 9916

Last change on this file since 9916 was 9916, checked in by neise, 16 years ago
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1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - dneise.UNKNOWN (E5B-LABOR6)
5-- at - 12:45:57 31.08.2010
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 GENERIC(
17 RAMADDRWIDTH64b : integer := 12
18 );
19 PORT(
20 CLK : IN std_logic;
21 SROUT_in_0 : IN std_logic;
22 SROUT_in_1 : IN std_logic;
23 SROUT_in_2 : IN std_logic;
24 SROUT_in_3 : IN std_logic;
25 adc_data_array : IN adc_data_array_type;
26 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
27 board_id : IN std_logic_vector (3 DOWNTO 0);
28 crate_id : IN std_logic_vector (1 DOWNTO 0);
29 trigger : IN std_logic;
30 wiz_int : IN std_logic;
31 CLK25_OUT : OUT std_logic;
32 CLK25_PSOUT : OUT std_logic;
33 CLK50_OUT : OUT std_logic;
34 CLK_25_PS : OUT std_logic;
35 CLK_50 : OUT std_logic;
36 DCM_locked : OUT std_logic;
37 LOCKED_extraOUT : OUT std_logic;
38 PSCLK_OUT : OUT std_logic;
39 PSDONE_extraOUT : OUT std_logic;
40 PSEN_OUT : OUT std_logic;
41 PSINCDEC_OUT : OUT std_logic;
42 PS_DIR_IN : OUT std_logic;
43 PS_DO_IN : OUT std_logic;
44 RSRLOAD : OUT std_logic := '0';
45 SRCLK : OUT std_logic := '0';
46 adc_clk_en : OUT std_logic := '0';
47 adc_oeb : OUT std_logic := '1';
48 dac_cs : OUT std_logic;
49 denable : OUT std_logic := '0'; -- default domino wave off
50 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
51 drs_dwrite : OUT std_logic := '1';
52 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
53 mosi : OUT std_logic := '0';
54 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
55 ready : OUT std_logic := '0';
56 sclk : OUT std_logic;
57 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
58 -- status:
59 shifting : OUT std_logic := '0';
60 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
61 wiz_cs : OUT std_logic := '1';
62 wiz_rd : OUT std_logic := '1';
63 wiz_reset : OUT std_logic := '1';
64 wiz_wr : OUT std_logic := '1';
65 sio : INOUT std_logic;
66 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
67 );
68
69-- Declarations
70
71END FAD_main ;
72
73--
74-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
75--
76-- Created:
77-- by - dneise.UNKNOWN (E5B-LABOR6)
78-- at - 12:45:58 31.08.2010
79--
80-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
81--
82library ieee;
83use ieee.std_logic_1164.all;
84use IEEE.STD_LOGIC_ARITH.all;
85use ieee.STD_LOGIC_UNSIGNED.all;
86
87library fact_fad_lib;
88use fact_fad_lib.fad_definitions.all;
89
90library UNISIM;
91use UNISIM.VComponents.all;
92USE IEEE.NUMERIC_STD.all;
93USE IEEE.std_logic_signed.all;
94
95LIBRARY FACT_FAD_lib;
96
97ARCHITECTURE struct OF FAD_main IS
98
99 -- Architecture declarations
100
101 -- Internal signal declarations
102 SIGNAL CLK_25 : std_logic;
103 SIGNAL SRCLK1 : std_logic := '0';
104 SIGNAL adc_data_array_int : adc_data_array_type;
105 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
106 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
107 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);
108 SIGNAL config_busy : std_logic;
109 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);
110 SIGNAL config_data_valid : std_logic;
111 SIGNAL config_rd_en : std_logic;
112 SIGNAL config_ready : std_logic;
113 SIGNAL config_ready_cm : std_logic;
114 SIGNAL config_ready_spi : std_logic;
115 SIGNAL config_start : std_logic := '0';
116 SIGNAL config_start_cm : std_logic;
117 SIGNAL config_start_spi : std_logic := '0';
118 SIGNAL config_started : std_logic;
119 SIGNAL config_started_cu : std_logic := '0';
120 SIGNAL config_started_mm : std_logic;
121 SIGNAL config_started_spi : std_logic := '0';
122 SIGNAL config_wr_en : std_logic;
123 SIGNAL dac_array : dac_array_type;
124 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
125 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0');
126 SIGNAL drs_address_mode : std_logic;
127 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0');
128 SIGNAL drs_clk_en : std_logic := '0';
129 SIGNAL drs_read_s_cell : std_logic := '0';
130 SIGNAL drs_read_s_cell_ready : std_logic;
131 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
132 SIGNAL dwrite : std_logic := '1';
133 SIGNAL dwrite_enable : std_logic := '1';
134 SIGNAL new_config : std_logic := '0';
135 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
136 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards
137 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once
138 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift
139 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0);
140 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
141 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0);
142 SIGNAL ram_write_ea : std_logic;
143 SIGNAL ram_write_ready : std_logic := '0';
144 SIGNAL roi_array : roi_array_type;
145 SIGNAL roi_max : roi_max_type;
146 SIGNAL s_trigger : std_logic := '0';
147 SIGNAL sclk1 : std_logic;
148 SIGNAL sclk_enable : std_logic;
149 SIGNAL sensor_array : sensor_array_type;
150 SIGNAL sensor_ready : std_logic;
151 SIGNAL srclk_enable : std_logic := '0';
152 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);
153 SIGNAL wiz_ack : std_logic;
154 SIGNAL wiz_busy : std_logic;
155 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
156 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0');
157 SIGNAL wiz_write_ea : std_logic := '0';
158 SIGNAL wiz_write_end : std_logic := '0';
159 SIGNAL wiz_write_header : std_logic := '0';
160 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
161 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
162
163 -- Implicit buffer signal declarations
164 SIGNAL CLK_25_PS_internal : std_logic;
165 SIGNAL CLK_50_internal : std_logic;
166
167
168 -- Component Declarations
169 COMPONENT adc_buffer
170 PORT (
171 adc_data_array : IN adc_data_array_type;
172 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
173 clk_ps : IN std_logic;
174 adc_data_array_int : OUT adc_data_array_type;
175 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
176 );
177 END COMPONENT;
178 COMPONENT clock_generator_var_ps
179 PORT (
180 CLK : IN std_logic ;
181 RST_IN : IN std_logic ;
182 direction : IN std_logic ;
183 do_shift : IN std_logic ;
184 CLK_25 : OUT std_logic ;
185 CLK_25_PS : OUT std_logic ;
186 CLK_50 : OUT std_logic ;
187 DCM_locked : OUT std_logic ;
188 LOCKED_extraOUT : OUT std_logic ;
189 PSCLK_OUT : OUT std_logic ;
190 PSDONE_extraOUT : OUT std_logic ;
191 PSEN_OUT : OUT std_logic ;
192 PSINCDEC_OUT : OUT std_logic ;
193 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
194 ready : OUT std_logic := '0';
195 -- status:
196 shifting : OUT std_logic := '0'
197 );
198 END COMPONENT;
199 COMPONENT control_unit
200 PORT (
201 clk : IN STD_LOGIC ;
202 config_addr : IN std_logic_vector (7 DOWNTO 0);
203 config_rd_en : IN std_logic ;
204 config_start : IN std_logic ;
205 config_wr_en : IN std_logic ;
206 config_busy : OUT std_logic ;
207 config_data_valid : OUT std_logic ;
208 config_ready : OUT std_logic ;
209 config_started : OUT std_logic := '0';
210 dac_array : OUT dac_array_type ;
211 drs_address : OUT std_logic_vector (3 DOWNTO 0);
212 drs_address_mode : OUT std_logic ;
213 roi_array : OUT roi_array_type ;
214 config_data : INOUT std_logic_vector (15 DOWNTO 0)
215 );
216 END COMPONENT;
217 COMPONENT dataRAM_64b_16b_width14_5
218 PORT (
219 clka : IN std_logic ;
220 dina : IN std_logic_VECTOR (63 DOWNTO 0);
221 addra : IN std_logic_VECTOR (14 DOWNTO 0);
222 wea : IN std_logic_VECTOR (0 DOWNTO 0);
223 clkb : IN std_logic ;
224 addrb : IN std_logic_VECTOR (16 DOWNTO 0);
225 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
226 );
227 END COMPONENT;
228 COMPONENT data_generator
229 GENERIC (
230 RAM_ADDR_WIDTH : integer := 12
231 );
232 PORT (
233 clk : IN std_logic ;
234 data_out : OUT std_logic_vector (63 DOWNTO 0);
235 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
236 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";
237 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
238 ram_write_ea : IN std_logic ;
239 ram_write_ready : OUT std_logic := '0';
240 config_start_mm : OUT std_logic := '0';
241 config_start_cm : OUT std_logic := '0';
242 config_start_spi : OUT std_logic := '0';
243 config_ready_mm : IN std_logic ;
244 config_ready_cm : IN std_logic ;
245 config_ready_spi : IN std_logic ;
246 config_started_mm : IN std_logic ;
247 config_started_cm : IN std_logic ;
248 config_started_spi : IN std_logic ;
249 roi_array : IN roi_array_type ;
250 roi_max : IN roi_max_type ;
251 sensor_array : IN sensor_array_type ;
252 sensor_ready : IN std_logic ;
253 dac_array : IN dac_array_type ;
254 package_length : IN std_logic_vector (15 DOWNTO 0);
255 board_id : IN std_logic_vector (3 DOWNTO 0);
256 crate_id : IN std_logic_vector (1 DOWNTO 0);
257 trigger_id : IN std_logic_vector (47 DOWNTO 0);
258 trigger : IN std_logic ;
259 s_trigger : IN std_logic ;
260 new_config : IN std_logic ;
261 config_started : OUT std_logic := '0';
262 adc_data_array : IN adc_data_array_type ;
263 adc_oeb : OUT std_logic := '1';
264 adc_clk_en : OUT std_logic := '0';
265 adc_otr : IN std_logic_vector (3 DOWNTO 0);
266 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
267 drs_dwrite : OUT std_logic := '1';
268 drs_clk_en : OUT std_logic := '0';
269 drs_read_s_cell : OUT std_logic := '0';
270 drs_read_s_cell_ready : IN std_logic ;
271 drs_s_cell_array : IN drs_s_cell_array_type
272 );
273 END COMPONENT;
274 COMPONENT drs_pulser
275 PORT (
276 CLK : IN std_logic;
277 SROUT_in_0 : IN std_logic;
278 SROUT_in_1 : IN std_logic;
279 SROUT_in_2 : IN std_logic;
280 SROUT_in_3 : IN std_logic;
281 start_endless_mode : IN std_logic;
282 start_read_stop_pos_mode : IN std_logic;
283 RSRLOAD : OUT std_logic := '0';
284 SRCLK : OUT std_logic := '0';
285 stop_pos : OUT drs_s_cell_array_type;
286 stop_pos_valid : OUT std_logic := '0'
287 );
288 END COMPONENT;
289 COMPONENT memory_manager
290 GENERIC (
291 RAM_ADDR_WIDTH_64B : integer := 12;
292 RAM_ADDR_WIDTH_16B : integer := 14
293 );
294 PORT (
295 clk : IN std_logic ;
296 config_start : IN std_logic ;
297 ram_write_ready : IN std_logic ;
298 roi_array : IN roi_array_type ;
299 ram_write_ea : OUT std_logic := '0';
300 config_ready : OUT std_logic := '0';
301 config_started : OUT std_logic := '0';
302 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
303 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
304 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0');
305 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
306 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
307 wiz_write_ea : OUT std_logic := '0';
308 wiz_write_header : OUT std_logic := '0';
309 wiz_write_end : OUT std_logic := '0';
310 wiz_busy : IN std_logic ;
311 wiz_ack : IN std_logic ;
312 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
313 );
314 END COMPONENT;
315 COMPONENT spi_interface
316 PORT (
317 clk_50MHz : IN std_logic ;
318 config_start : IN std_logic ;
319 dac_array : IN dac_array_type ;
320 config_ready : OUT std_logic ;
321 config_started : OUT std_logic := '0';
322 dac_cs : OUT std_logic ;
323 mosi : OUT std_logic := '0';
324 sclk : OUT std_logic ;
325 sensor_array : OUT sensor_array_type ;
326 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
327 sensor_ready : OUT std_logic ;
328 miso : INOUT std_logic
329 );
330 END COMPONENT;
331 COMPONENT trigger_counter
332 PORT (
333 trigger_id : OUT std_logic_vector (47 DOWNTO 0);
334 trigger : IN std_logic ;
335 clk : IN std_logic
336 );
337 END COMPONENT;
338 COMPONENT w5300_modul
339 GENERIC (
340 RAM_ADDR_WIDTH : integer := 14
341 );
342 PORT (
343 clk : IN std_logic ;
344 wiz_reset : OUT std_logic := '1';
345 addr : OUT std_logic_vector (9 DOWNTO 0);
346 data : INOUT std_logic_vector (15 DOWNTO 0);
347 cs : OUT std_logic := '1';
348 wr : OUT std_logic := '1';
349 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
350 rd : OUT std_logic := '1';
351 int : IN std_logic ;
352 write_length : IN std_logic_vector (16 DOWNTO 0);
353 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
354 ram_data : IN std_logic_vector (15 DOWNTO 0);
355 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
356 data_valid : IN std_logic ;
357 data_valid_ack : OUT std_logic := '0';
358 busy : OUT std_logic := '1';
359 write_header_flag : IN std_logic ;
360 write_end_flag : IN std_logic ;
361 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
362 s_trigger : OUT std_logic := '0';
363 new_config : OUT std_logic := '0';
364 config_started : IN std_logic ;
365 config_addr : OUT std_logic_vector (7 DOWNTO 0);
366 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
367 config_wr_en : OUT std_logic := '0';
368 config_rd_en : OUT std_logic := '0';
369 config_busy : IN std_logic ;
370 denable : OUT std_logic := '0'; -- default domino wave off
371 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low.
372 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH.
373 ps_direction : OUT std_logic := '1'; -- default phase shift upwards
374 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once
375 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift
376 srclk_enable : OUT std_logic := '1' -- default SRCLK on.
377 );
378 END COMPONENT;
379
380 -- Optional embedded configurations
381 -- pragma synthesis_off
382 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
383 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
384 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
385 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5;
386 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
387 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser;
388 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
389 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
390 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter;
391 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
392 -- pragma synthesis_on
393
394
395BEGIN
396
397 -- ModuleWare code(v1.9) for instance 'I5' of 'and'
398 drs_dwrite <= dwrite AND dwrite_enable;
399
400 -- ModuleWare code(v1.9) for instance 'I6' of 'and'
401 SRCLK <= SRCLK1 AND srclk_enable;
402
403 -- ModuleWare code(v1.9) for instance 'U_1' of 'and'
404 sclk <= sclk_enable AND sclk1;
405
406 -- ModuleWare code(v1.9) for instance 'U_3' of 'assignment'
407 PS_DO_IN <= ps_do_phase_shift;
408
409 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment'
410 PS_DIR_IN <= ps_direction;
411
412 -- ModuleWare code(v1.9) for instance 'U_6' of 'assignment'
413 CLK50_OUT <= CLK_50_internal;
414
415 -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment'
416 CLK25_OUT <= CLK_25;
417
418 -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment'
419 CLK25_PSOUT <= CLK_25_PS_internal;
420
421 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
422 u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
423 drs_address_mode)
424 BEGIN
425 CASE drs_address_mode IS
426 WHEN '0' => drs_channel_id <= drs_channel_internal;
427 WHEN '1' => drs_channel_id <= drs_address;
428 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
429 END CASE;
430 END PROCESS u_0combo_proc;
431
432 -- Instance port mappings.
433 I_main_adc_buffer : adc_buffer
434 PORT MAP (
435 clk_ps => CLK_25_PS_internal,
436 adc_data_array => adc_data_array,
437 adc_otr_array => adc_otr_array,
438 adc_data_array_int => adc_data_array_int,
439 adc_otr => adc_otr
440 );
441 U_2 : clock_generator_var_ps
442 PORT MAP (
443 CLK => CLK,
444 RST_IN => ps_reset,
445 direction => ps_direction,
446 do_shift => ps_do_phase_shift,
447 CLK_25 => CLK_25,
448 CLK_25_PS => CLK_25_PS_internal,
449 CLK_50 => CLK_50_internal,
450 DCM_locked => DCM_locked,
451 LOCKED_extraOUT => LOCKED_extraOUT,
452 PSCLK_OUT => PSCLK_OUT,
453 PSDONE_extraOUT => PSDONE_extraOUT,
454 PSEN_OUT => PSEN_OUT,
455 PSINCDEC_OUT => PSINCDEC_OUT,
456 offset => offset,
457 ready => ready,
458 shifting => shifting
459 );
460 I_main_control_unit : control_unit
461 PORT MAP (
462 clk => CLK_50_internal,
463 config_addr => config_addr,
464 config_rd_en => config_rd_en,
465 config_start => config_start_cm,
466 config_wr_en => config_wr_en,
467 config_busy => config_busy,
468 config_data_valid => config_data_valid,
469 config_ready => config_ready_cm,
470 config_started => config_started_cu,
471 dac_array => dac_array,
472 drs_address => drs_address,
473 drs_address_mode => drs_address_mode,
474 roi_array => roi_array,
475 config_data => config_data
476 );
477 U_4 : dataRAM_64b_16b_width14_5
478 PORT MAP (
479 clka => CLK_25,
480 dina => data_out,
481 addra => addr_out,
482 wea => write_ea,
483 clkb => CLK_50_internal,
484 addrb => ram_addr,
485 doutb => ram_data
486 );
487 I_main_data_generator : data_generator
488 GENERIC MAP (
489 RAM_ADDR_WIDTH => RAMADDRWIDTH64b
490 )
491 PORT MAP (
492 clk => CLK_25,
493 data_out => data_out,
494 addr_out => addr_out,
495 write_ea => write_ea,
496 ram_start_addr => ram_start_addr,
497 ram_write_ea => ram_write_ea,
498 ram_write_ready => ram_write_ready,
499 config_start_mm => config_start,
500 config_start_cm => config_start_cm,
501 config_start_spi => config_start_spi,
502 config_ready_mm => config_ready,
503 config_ready_cm => config_ready_cm,
504 config_ready_spi => config_ready_spi,
505 config_started_mm => config_started_mm,
506 config_started_cm => config_started_cu,
507 config_started_spi => config_started_spi,
508 roi_array => roi_array,
509 roi_max => roi_max,
510 sensor_array => sensor_array,
511 sensor_ready => sensor_ready,
512 dac_array => dac_array,
513 package_length => package_length,
514 board_id => board_id,
515 crate_id => crate_id,
516 trigger_id => trigger_id,
517 trigger => trigger,
518 s_trigger => s_trigger,
519 new_config => new_config,
520 config_started => config_started,
521 adc_data_array => adc_data_array_int,
522 adc_oeb => adc_oeb,
523 adc_clk_en => adc_clk_en,
524 adc_otr => adc_otr,
525 drs_channel_id => drs_channel_internal,
526 drs_dwrite => dwrite,
527 drs_clk_en => drs_clk_en,
528 drs_read_s_cell => drs_read_s_cell,
529 drs_read_s_cell_ready => drs_read_s_cell_ready,
530 drs_s_cell_array => drs_s_cell_array
531 );
532 I_main_drs_pulser : drs_pulser
533 PORT MAP (
534 CLK => CLK_25,
535 start_endless_mode => drs_clk_en,
536 start_read_stop_pos_mode => drs_read_s_cell,
537 SROUT_in_0 => SROUT_in_0,
538 SROUT_in_1 => SROUT_in_1,
539 SROUT_in_2 => SROUT_in_2,
540 SROUT_in_3 => SROUT_in_3,
541 stop_pos => drs_s_cell_array,
542 stop_pos_valid => drs_read_s_cell_ready,
543 RSRLOAD => RSRLOAD,
544 SRCLK => SRCLK1
545 );
546 I_main_memory_manager : memory_manager
547 GENERIC MAP (
548 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b,
549 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2
550 )
551 PORT MAP (
552 clk => CLK_25,
553 config_start => config_start,
554 ram_write_ready => ram_write_ready,
555 roi_array => roi_array,
556 ram_write_ea => ram_write_ea,
557 config_ready => config_ready,
558 config_started => config_started_mm,
559 roi_max => roi_max,
560 package_length => package_length,
561 wiz_ram_start_addr => wiz_ram_start_addr,
562 wiz_write_length => wiz_write_length,
563 wiz_number_of_channels => wiz_number_of_channels,
564 wiz_write_ea => wiz_write_ea,
565 wiz_write_header => wiz_write_header,
566 wiz_write_end => wiz_write_end,
567 wiz_busy => wiz_busy,
568 wiz_ack => wiz_ack,
569 ram_start_addr => ram_start_addr
570 );
571 I_main_SPI_interface : spi_interface
572 PORT MAP (
573 clk_50MHz => CLK_50_internal,
574 config_start => config_start_spi,
575 dac_array => dac_array,
576 config_ready => config_ready_spi,
577 config_started => config_started_spi,
578 dac_cs => dac_cs,
579 mosi => mosi,
580 sclk => sclk1,
581 sensor_array => sensor_array,
582 sensor_cs => sensor_cs,
583 sensor_ready => sensor_ready,
584 miso => sio
585 );
586 I_main_ext_trigger : trigger_counter
587 PORT MAP (
588 trigger_id => trigger_id,
589 trigger => trigger,
590 clk => CLK_25_PS_internal
591 );
592 I_main_ethernet : w5300_modul
593 GENERIC MAP (
594 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2
595 )
596 PORT MAP (
597 clk => CLK_50_internal,
598 wiz_reset => wiz_reset,
599 addr => wiz_addr,
600 data => wiz_data,
601 cs => wiz_cs,
602 wr => wiz_wr,
603 led => led,
604 rd => wiz_rd,
605 int => wiz_int,
606 write_length => wiz_write_length,
607 ram_start_addr => wiz_ram_start_addr,
608 ram_data => ram_data,
609 ram_addr => ram_addr,
610 data_valid => wiz_write_ea,
611 data_valid_ack => wiz_ack,
612 busy => wiz_busy,
613 write_header_flag => wiz_write_header,
614 write_end_flag => wiz_write_end,
615 fifo_channels => wiz_number_of_channels,
616 s_trigger => s_trigger,
617 new_config => new_config,
618 config_started => config_started,
619 config_addr => config_addr,
620 config_data => config_data,
621 config_wr_en => config_wr_en,
622 config_rd_en => config_rd_en,
623 config_busy => config_busy,
624 denable => denable,
625 dwrite_enable => dwrite_enable,
626 sclk_enable => sclk_enable,
627 ps_direction => ps_direction,
628 ps_do_phase_shift => ps_do_phase_shift,
629 ps_reset => ps_reset,
630 srclk_enable => srclk_enable
631 );
632
633 -- Implicit buffered output assignments
634 CLK_25_PS <= CLK_25_PS_internal;
635 CLK_50 <= CLK_50_internal;
636
637END struct;
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