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\title{FAD Data Generation}
\author{D. Neise}
\date{08.02.2011}

\begin{document}

\maketitle
\tableofcontents
\newpage


\section{data order in 64bit address space}

When data is input into Data-RAM by the DataGenerator, the data is fed in as words of 64bit.

Each Event constists of an EventHeader, the so called ChannelData, and a small EventFooter.
Figure (\ref{64bitRAM}) shows how the data is stored as 64bit words in the DataRAM.
Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists 100 samples.
\\ \\
%\emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.}


\begin{table}[htbp]
\begin{tabular}{||l||l|l|l|l||l||} 
\hline
address & word 3 & word 2 & word 1 & word 0 & description \\
\hline
0x2000 	& 0x0000 & version	& length & 0xFB01	& Header	\\  
0x2001	& 0x0000 & TRG ID 45	& EVT cntr 10	& EVT cntr 32	& Externl trigger ID\\
0x2002	& 0x0000 & TRG ID 45	& EVT cntr 10	& EVT cntr 32	& Internal trigger ID\\
0x2003	& 0x0000	& 0x0000	& 0x0000	& 0x0(cid)8(bid)	& Board ID 	\\
0x2004	& Temp 3	& Temp 2	& Temp 1	& Temp 0	& Temperatures \\
0x2005	& DAC 3	& DAC 2	& DAC 1	& DAC 0	& DAC values part 1	\\
0x2006	& DAC 7	& DAC 6	& DAC 5	& DAC 4	& DAC values part 2	\\
\hline
0x2007	& 0x0030	& 0x0020	& 0x0010	& 0x0000	& chip-n-channel ID (group 0) \\
0x2008	& trg pos 3	& trg pos 2	& trg pos 1	& trg pos 0	& DRS stop positions \\
0x2009	& ROI 3	& ROI 2	& ROI 1	& ROI 0	& width of region of interest \\
0x200A	& data adc3	& data adc2	& data adc1	& data adc0	& ADC Data start of ROI \\
0x20..  &&&&& ... \\
0x206D	& data adc3	& data adc2	& data adc1	& data adc0	& ADC Data end of ROI \\
\hline
0x206E	& 0x0031	& 0x0021	& 0x0011	& 0x0001	& chip-n-channel ID (group 1) \\
0x206F	& trg pos 3	& trg pos 2	& trg pos 1	& trg pos 0	& DRS stop positions \\
0x2070	& ROI 3	& ROI 2	& ROI 1	& ROI 0	& width of region of interest \\
0x2071	& data adc3	& data adc2	& data adc1	& data adc0	& ADC Data start of ROI \\
0x20..  &&&&& ... \\
0x20D4	& data adc3	& data adc2	& data adc1	& data adc0	& ADC Data end of ROI \\
\hline
0x20..  &&&&& ... \\
\hline
0x233F	& 0x0039	& 0x0029	& 0x0019	& 0x0009	& chip-n-channel ID (group 9) \\
0x2340	& trg pos 3	& trg pos 2	& trg pos 1	& trg pos 0	& DRS stop positions \\
0x2341	& ROI 3	& ROI 2	& ROI 1	& ROI 0	& width of region of interest \\
0x2342	& data adc3	& data adc2	& data adc1	& data adc0	& ADC Data start of ROI \\
0x23..  &&&&& ... \\
0x23A5	& data adc3	& data adc2	& data adc1	& data adc0	& ADC Data end of ROI \\
\hline
0x23A6	& 0x0000	& 0x0000	& 0x04FE	& 0x4242	& FOOTER \\
\hline
\end {tabular}

\caption{word order of event in Data RAM. 64bit addressing. As of 08.02.2011}
\label{64bitRAM}
\end{table}


During DRS readout and data digitzation, the Trigger ID is coming in through RS485 interface from FTM board.
The Trigger ID reciption takes about $40 {\mu}$s. Therefor the 2 words containing Trigger information in the EventHeader are
left empty in the first place. The digitazed analog data is read in as quickly as possible. Only after finishing the Readout,
the Trigger ID is filled into the EventHeader.
Then the EventFooter is added and the Readout is finished.

\newpage
\section{data order in 16bit address space}

After an Event is stored in data RAM, is is ready to be read out by {\tt w5300 modul.vhd}. 
Since the FIFOs of FADs W5300 ethernet controller are of 16bit width, data is read out of the dataRAM 
as 16bit words. Empty 16bit words are left out.

The following table shows how the data is ordered inside data RAM, when accessed in 16bit address space

\begin{table}[htbp]
\begin{tabular}{|l|l|l|}
\hline
address & 16bit word & description \\
\hline
0x8000	& 0xFB01	& Start Flag - fix value \\
0x8001	& 0xllll	& package length in 16bit words \\
0x8002	& 0xvvvv	& version - deduced from SVN revision number \\
0x8004	& EVT cntr 32 & trigger ID upper word \\
0x8005	& EVT cntr 10 & trigger ID lower word \\
0x8006	& 0xAA55 & trigger type and CRC-fake \\
0x8008	& EVT cntr 32 & trigger ID upper word \\
0x8009	& EVT cntr 10 & trigger ID lower word \\
0x800A	& 0xAA55 & trigger type and CRC-fake \\
0x800C	& 0x0(cid)8(bid) & Board ID \\
0x8010	& 0xttt0	& temperature sensor next to DRS 0 \\
0x8011	& 0xttt1	& temperature sensor next to DRS 1 \\
0x8012	& 0xttt2	& temperature sensor next to DRS 2 \\
0x8013	& 0xttt3	& temperature sensor next to DRS 3 \\
0x8014	& 0xdac0	& setting of DAC channel A \\
0x8015	& 0xdac1	& setting of DAC channel B \\
0x8016	& 0xdac2	& setting of DAC channel C \\
0x8017	& 0xdac3	& setting of DAC channel D \\
0x8018	& 0xdac4	& setting of DAC channel E \\
0x8019	& 0xdac5	& setting of DAC channel F \\
0x801A	& 0xdac6	& setting of DAC channel G \\
0x801B	& 0xdac7	& setting of DAC channel H \\
\hline
0x801C	& 0x0000 & DRS 0 - channel 0 \\
0x8020	& trg pos 0	& DRS 0 stop position \\
0x8024	& ROI 00	& ROI width of this channel \\
0x8028	& adc data 0& ADC data start \\
0x8...	& ...		& ...data ... \\
0x81B4	& adc data ROI-1 &	ADC data stop\\
\hline
0x801D	& 0x0010 & DRS 1 - channel 0 \\
0x8021	& trg pos 1	& DRS 1 stop position \\
0x8025	& ROI 10	& ROI width of this channel \\
0x8029	& adc data 0& ADC data start \\
0x8...	& ...		& ...data ... \\
0x81B5	& adc data ROI-1 &	ADC data stop\\
\hline
0x8...	& ...		& ...data ... \\
\hline
0x8CFC	& 0x0039 & DRS 3 - channel 9 \\
0x8D03	& trg pos 3	& DRS 3 stop position \\
0x8D07	& ROI 39	& ROI width of this channel \\
0x8D0B	& adc data 0& ADC data start \\
0x8...	& ...		& ...data ... \\
0x8E97	& adc data ROI-1 &	ADC data stop\\
\hline
0x8E98	& 0x4242		& packet CRC-fake \\
0x8E99	& 0x04FE		& End Flag \\
\hline
\end {tabular}

\caption{word order of event in Data RAM. 16bit addressing. As of 08.02.2011}
\label{16bitRAM}
\end{table}

As one can see, the way of reading out of the RAM changes, from header to data section and again when data section ends.
When reading the header, the addresses are increased by 1 usually and only jumps, when empty words show up in the RAM.
One can picture it as if reading the words in each line from right to left, sometimes jumping over zeroes.
When reading out the data sections, the words are read out as columns, i.e. addresses are incremented by 4 usually. One column is read until the data of a channel is completely read out, then either the next DRS chip is read out, which means to decrease the address or, if one group of channels was finished, the next group starts, which means address is increased by 1 only.
The footer consisting of the CRC-16 (when finally implemented) and the end package flag is again read out by reading each word from right to left.


\newpage
\section{NEW data order}

Some data is going to be added to the Event header changing the data order like this.

\begin{table}[htbp]
\begin{tabular}{||l||l|l|l|l||} 
\hline
address & word 3					& word 2				& word 1			& word 0			\\
\hline
0x2000 	& 12bit status + PLLLOCK 	& version				& length			& 0xFB01			\\
0x2001	& 0xT1T0 					& 0xT3T2 				& 0xT5T4			& 0x00T6 			\\
0x2002	& REFCLK cntr 10 			& REFCLK cntr 32		& EVT cntr 10		& EVT cntr 32		\\
0x2003	& TRG-GEN-DIV				& TRG-GEN-No			& DCM-PS-STATUS 	& 0x0(cid)8(bid)	\\
0x2004	& DNA10						& DNA32					& DNA54				& 0x00DNA6			\\
0x2005	& more status				& more status			& time10			& time32 			\\
0x2006	& Temp 3					& Temp 2				& Temp 1			& Temp 0			\\
0x2007	& DAC 3						& DAC 2					& DAC 1				& DAC 0				\\
0x2008	& DAC 7						& DAC 6					& DAC 5				& DAC 4				\\
\hline			
0x2009	& 0x0030					& 0x0020				& 0x0010			& 0x0000			\\
0x200A	& trg pos 3					& trg pos 2				& trg pos 1			& trg pos 0			\\
0x200B	& ROI 3						& ROI 2					& ROI 1				& ROI 0				\\
0x200C	& -fill- 					& -fill-				& -fill-			& -fill-			\\
0x200D	& data adc3					& data adc2				& data adc1			& data adc0			\\
0x20..  & ...						& ...					& ...				& ... 				\\
0x2070	& data adc3					& data adc2				& data adc1			& data adc0			\\
\hline			
0x20..  & ...						& ...					& ...				& ... 				\\
\hline			
0x23??	& 0x0039					& 0x0029				& 0x0019			& 0x0009			\\
0x23??	& trg pos 3					& trg pos 2				& trg pos 1			& trg pos 0			\\
0x23??	& ROI 3						& ROI 2					& ROI 1				& ROI 0				\\
0x23??	& -fill-					& -fill-				& -fill-			& -fill-			\\
0x23??	& data adc3					& data adc2				& data adc1			& data adc0			\\
0x23..  & ...						& ...					& ...				& ... 				\\
0x23??	& data adc3					& data adc2				& data adc1			& data adc0			\\
\hline			
0x23??	& 0x0000					& 0x0000				& 0x04FE			& 0x4242			\\
\hline
\end {tabular}
\caption{NEW word order of event in Data RAM. 64bit addressing. As of > 08.02.2011}
\label{new64bitRAM}
\end{table}

A detailed description is given after, next table.\\

\newpage
Which in turn changes the the word order in the 16bit address space like this
\begin{table}[htbp]
\begin{tabular}{|l|l|l|}
\hline
address & 16bit word & description \\
\hline
0x8000	& 0xFB01	& Start Flag - fix value: "FB01" \\
0x8001	& 0xllll	& package length in 16bit words \\
0x8002	& 0xvvvv	& version - deduced from SVN revision number \\
0x8003	& 0xsssP	& 12 bits for status - TBD - 4 bit showing PLLLCK status \\  
\hdashline
0x8004	& 0x00T6	& FTM trigger ID byte 6 : CRC \\
0x8005	& 0xT5T4	& ... bytes 5 and 4 : Type 2 and Type 1\\
0x8006	& 0xT3T2	& ... bytes 3 and 2	: TRG number high word \\
0x8007	& 0xT1T0	& ... bytes 1 and 0 : TRG number low word \\ 
\hdashline
0x8008	& 0xev32 	& FAD event counter high word \\
0x8009	& 0xev10 	& FAD event counter low word -- should be equal to T3T2T1T0\\
0x800A	& 0xRC32	& REFCLK counter high word \\
0x800B	& 0xRC10	& REFCLK counter low word \\  
\hdashline
0x800C	& 0x0(cid)8(bid) & Board ID \\
0x800D	& DCM-PS	& status of ADC clock phase shifter , value and locked-bit\\
0x800E	& TRG-GEN-No& Number of Triggers to generare, when 'trigger continous' issued \\
0x800F	& TRG-GEN-DIV& continous trigger generator clock prescaler \\ 
\hdashline
0x8010	& 0x00 DNA6	& MSB of DNA \\
0x8011	& DNA54		& ... DNA ... \\
0x8012	& DNA32		& ... DNA ... \\
0x8013	& DNA10		& LSB of DNA \\
\hdashline
0x8014	& timer32	& timer high word \\
0x8015	& timer10	& timer low word \\
0x8016	& more status1 & reserved for status info; high word \\
0x8017	& more status0 & reserved for status info; low word \\ 
\hdashline
0x8018	& 0xttt0	& temperature sensor next to DRS 0 \\
0x8019	& 0xttt1	& temperature sensor next to DRS 1 \\
0x801A	& 0xttt2	& temperature sensor next to DRS 2 \\
0x801B	& 0xttt3	& temperature sensor next to DRS 3 \\ 
\hdashline
0x801C	& 0xdac0	& setting of DAC channel A \\
0x801D	& 0xdac1	& setting of DAC channel B \\
0x801E	& 0xdac2	& setting of DAC channel C \\
0x801F	& 0xdac3	& setting of DAC channel D \\  
\hdashline
0x8020	& 0xdac4	& setting of DAC channel E \\
0x8021	& 0xdac5	& setting of DAC channel F \\
0x8022	& 0xdac6	& setting of DAC channel G \\
0x8023	& 0xdac7	& setting of DAC channel H \\ 
\hline
0x8...	& ...		& ...data ... \\
\hline

\end {tabular}
\caption{word order of event in Data RAM. 16bit addressing. As of > 08.02.2011}
\label{16bitRAM}
\end{table}
This new order has several advantages apart from the additional information included.
All data may be treated as 64bit aligned. And the data readout process does not need jump over words during data sending.


\newpage
\subsection{new {\tt FADFormat.h}}

\begin{verbatim}
typedef struct {
	// ------------------------------
	unsigned short start_package_flag;
	unsigned short package_length;
	unsigned short version_no;
	unsinged short PLLLCK;
	// ------------------------------
	unsigned short trigger_crc;
	unsigned short tigger_type;
	unsigned long trigger_id;
	// ------------------------------
	unsigned long fad_evt_counter;
	unsigned long REFCLK_frequency;
	// ------------------------------
	unsigned short board_id;
	unsigned short adc_clock_phase_shift;
	unsgined short number_of_triggers_to_generate;
	unsigned short trigger_generator_prescaler;
	// ------------------------------
	unsigned char reserved;
	unsigned char DNA[7];	// '1' & 55 unique bits of Xilinx DNA   
	// ------------------------------
	unsigned long time;
	unsigned long fad_status;
	// ------------------------------
	short drs_temperature[NTemp];
	// ------------------------------	
	unsigned short dac[NDAC];
	// ------------------------------
}  __attribute__((__packed__)) PEVNT_HEADER;

typedef struct {
	unsigned short id;
	unsigned short start_cell;
	unsigned short roi;
	unsigned short filling;
	unsigned short adc_data[];
}  __attribute__((__packed__)) PCHANNEL;

typedef struct {
	unsigned short package_crc;
	unsigned short end_package_flag;
}  __attribute__((__packed__)) PEVNT_FOOTER;
\end{verbatim} 

\subsection{mem manager calculations}

Memory manager knows the size of FADs internal data RAM. This is implemented as VHDL-Generics called {\tt RAM_ADD_WIDTH_64B}
and {\tt RAM_ADD_WIDTH_16B}. Since word width is 64bit on the input side and 16bit on the outpt two generics are used.
Currently the values are:
\begin{table}[htbp]
\begin{tabular}{ll} 
RAM_ADD_WIDTH_64B & 12 \\
RAM_ADD_WIDTH_16B & 14 \\
\end {tabular}
\caption{values of RAM width}
\label{RAM_GENERICS}
\end{table}

Which results in 
\begin{equation}
\mathtt{RAM size} = 2^{12} \cdot 8 byte= 2^14 * 2 byte = 32768 byte .
\end{equation}

Now the memory manager is able to calculate the number of Events, fitting into this RAM.

The number of samples of each channel beeing digitized is called region of interest(ROI). Since the ROI of each of the 36 input channel may be defined independently, but the RAM is organized in 64bit words on the input side, the memory manager needs to calculate the effective ROI of each channel first. The DRS Chips are digitized in a parallel manner, but their 9 channels are digitized serially. So first each DRS is ordered to output its channel 0 data, until as many samples are digitized as the maximum of all channel 0 ROIs is.

In the states called MAX_ROI0..2 the array containing the maxima of each group of channels is calculated.
In addition the so called channel size array is calculated. This is the number of 16bit words which is needed to store a group of 
channels in the W5300 FIFO. The header is included into the group of channels 0, while the package footer is included into group of channels 9.

\subsubsection{state: MM CONFIG}
Here all local variables are reset to zero. Let me shortly explain the meaning of each of them:
\begin{table}[htbp]
\begin{tabular}{lll} 
	roi\_max\_array 		& array (0 to 8) of integer range 0 to 1024 					& maximum for each channel group\\
	channel\_size			& array (0 to 8) of integer range 0 to W5300\_TX\_FIFO\_SIZE 	& size of each channel group in 16b words \\
	fifo\_write\_length		& array (0 to 8) of integer range 0 to W5300\_TX\_FIFO\_SIZE	& similar ??? \\
	fifo\_channels\_array	& array (0 to 8) of integer range 0 to 9						& ??? \\
	\hline \\
	event_size				& integer range 0 to RAM\_SIZE\_16B								& ???\\
	event_size_ram			& integer range 0 to RAM\_SIZE\_16B								& ???\\
	event_size_ram_64b		& integer range 0 to RAM\_SIZE\_64B								& ??? \\
\end {tabular}
\caption{ -no caption- -no label-}
%\label{}
\end{table}

The input is only:
\begin{table}[htbp]
\begin{tabular}{lll} 
	roi\_array		 		& array (0 to 35) of integer range 0 to 1024 					& ROI of each channel\\
\end {tabular}
\caption{ -no caption- -no label-}
%\label{}
\end{table}

\subsubsection{states: MAX ROI\bf{n} and state: FIFO\_CALC} 
\begin{itemize}
\item find maxium in roi\_array for each channel and store it as the maximum roi of each channel group inside roi\_max\_array.
\item calculate channel\_size(n) as $sum_{drs=0}^{3} \left( roi_{drs,n} + CHANNEL\_HEADER\_SIZE \right)$. 
For $n=0$ the size of the package header is added and for $n=8$ the size of the package footer is added to the channel\_size.
So channel\_size(n) stores the number of 16bit words, which will be transmitted over ethernet for this particular group of channels n. \\
Note: this is not the number of 16bit words, which will be stored inside the internal data RAM, since this number is defined by the maximum roi of each channel group.
\item calculate into how many pieces the package need to be devided. fifo\_write\_length(m) contains a certain sum of channel\_sizes. So again
fifo\_write\_length is a size measures in 16bit words, which will actually be transmitted over ethernet. 
\end{itemize}


\subsubsection{states: RAM\_CALC\bf{n}}
Here we need to know how many of these packages will fit into our data RAM. 
There 		

\end{document}
