source: firmware/FAD/doc/memory_manager.tex @ 10139

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1\documentclass[a4paper,twoside]{article}
2
3\setlength{\topmargin}{0mm}  %1 inch is always there!
4\setlength{\oddsidemargin}{0mm}  %1 inch is always there!
5\setlength{\evensidemargin}{0mm}  %1 inch is always there!
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7\setlength{\textwidth}{16cm} 
8
9% keine Kopfzeile?
10\setlength{\headheight}{0mm} 
11\setlength{\headsep}{0mm}
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13 
14%um die deutschen Umlaute eingeben zu können
15% müssen diese 3 Pakete eingebunden werden.
16% welches der Pakete was macht, weiss ich nicht.
17\usepackage[T1]{fontenc}
18\usepackage[latin1]{inputenc}
19%\usepackage{ngerman}                                   % nur wenn z.B. 'Inhaltsverzeichnis' auch deutsch sein soll.
20
21\usepackage{graphicx} % for pictures
22\usepackage{float} % for figures with english descriptions
23
24\restylefloat{figure}
25\restylefloat{table}
26
27\begin{document}
28
29%\maketitle
30
31%\tableofcontents
32%\listoffigures
33%\listoftables
34
35\section{\tt memory manager.vhd}
36
37The Memory Manager is used to calculate:
38\begin{itemize}
39\item
40\end{itemize}
41
42\subsection{data order in 64bit address space}
43
44When data is input into Data-RAM by the DataGenerator, the data is fed in as words of 64bit,
45because the 13bits of each of the four ADCs is processed in a parallel manner.
46
47Each Event constists of an EventHeader, the so called ChannelData, and a small EventFooter.
48Figure (\ref{64bitRAM}) shows how the data is stored as 64bit words in the DataRAM.
49Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists of 100 samples.
50
51Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.
52
53
54\begin{table}[htbp]
55
56\begin{tabular}{||l||l|l|l|l||l||} %6 linkbuendige spalten
57\hline
58address & word 3 & word 2 & word 1 & word 0 & mnemonic \\
59\hline
600x2000  & 0x0000 & Version      & 0xLLLL & 0xFB01       & Header        \\ 
610x2001  & 0x0000 & TRG-ID 4,5   & TRG-ID 1,0    & TRG-ID 3,2    & Externl trigger ID    \\
620x2002  & 0x0000 & TRG-ID 4,5   & TRG-ID 1,0    & TRG-ID 3,2    & Internal trigger ID   (now just a copy\\
630x2003  & 0x0000        & 0x0000        & 0x0000        & 0x0(cid)8(bid)        & Board ID      \\
640x2004  & Temp 3        & Temp 2        & Temp 1        & Temp 0        & Temperatures \\
650x2005  & DAC 3 & DAC 2 & DAC 1 & DAC 0 & DAC values part 1     \\
660x2006  & DAC 7 & DAC 6 & DAC 5 & DAC 4 & DAC values part 2     \\
67\hline
680x2007  & 0x0030        & 0x0020        & 0x0010        & 0x0000        & chip-n-channel ID (channel group 0) \\
690x2008  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
700x2009  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
710x200A  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
720x20..  &&&&& ... \\
730x206D  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
74\hline
750x206E  & 0x0031        & 0x0021        & 0x0011        & 0x0001        & chip-n-channel ID (channel group 1) \\
760x206F  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
770x2070  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
780x2071  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
790x20..  &&&&& ... \\
800x20D4  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
81\hline
820x20..  &&&&& ... \\
83\hline
840x233F  & 0x0039        & 0x0029        & 0x0019        & 0x0009        & chip-n-channel ID (channel group 9) \\
850x2340  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
860x2341  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
870x2342  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
880x23..  &&&&& ... \\
890x23A5  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
90\hline
910x23A6  & ??    & ??    & ??    & ??    & FOOTER \\
92\hline
93\end {tabular}
94
95\caption{word order of event in Data RAM. 64bit addressing.}
96\label{64bitRAM}
97\end{table}
98
99
100During DRS readout and data digitzation, the Trigger ID is coming in through RS485 interface from FTM board.
101The Trigger ID reciption takes about $40 {\mu}$s. Therefor the 2 words containing Trigger information in the EventHeader are
102left empty in the first place. The digitazed analog data is read in as quickly as possible. Only after finishing the Readout,
103the Trigger ID is filled into the EventHeader.
104Then the EventFooter is added and the Readout is finished.
105
106\subsection{role of memory manager for DataGenerator}
107After FAD-configuration memory manager informs data generator, whether additional Data may be read out or not.
108{\tt ram write ea } is used to inform DataGenerator.\\
109
110DataGenerator needs to know how many samples to read out of each channel.
111{\tt roi max} is carriing this information. \\
112
113
114\appendix
115
116
117\end{document}
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