source: firmware/FAD/doc/memory_manager.tex @ 10140

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1\documentclass[a4paper,twoside]{article}
2
3\setlength{\topmargin}{0mm}  %1 inch is always there!
4\setlength{\oddsidemargin}{0mm}  %1 inch is always there!
5\setlength{\evensidemargin}{0mm}  %1 inch is always there!
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7\setlength{\textwidth}{16cm} 
8
9\setlength{\headheight}{0mm} 
10\setlength{\headsep}{0mm}
11 
12\usepackage[T1]{fontenc}
13\usepackage[utf8]{inputenc}
14
15\usepackage{graphicx} % for pictures
16\usepackage{float} % for figures (english)
17\restylefloat{figure}
18\restylefloat{table}
19
20\title{FAD Data Generation}
21\author{D. Neise}
22\date{08.02.2011}
23
24\begin{document}
25
26\maketitle
27\tableofcontents
28\newpage
29
30\section{\tt memory manager.vhd}
31
32The Memory Manager is used to calculate:
33\begin{itemize}
34\item
35\end{itemize}
36
37\subsection{data order in 64bit address space}
38
39When data is input into Data-RAM by the DataGenerator, the data is fed in as words of 64bit,
40because the 13bits of each of the four ADCs is processed in a parallel manner.
41
42Each Event constists of an EventHeader, the so called ChannelData, and a small EventFooter.
43Figure (\ref{64bitRAM}) shows how the data is stored as 64bit words in the DataRAM.
44Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists 100 samples.
45\\ \\
46\emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.}
47
48
49\begin{table}[htbp]
50
51\begin{tabular}{||l||l|l|l|l||l||} %6 linkbuendige spalten
52\hline
53address & word 3 & word 2 & word 1 & word 0 & mnemonic \\
54\hline
550x2000  & 0x0000 & Version      & 0xLLLL & 0xFB01       & Header        \\ 
560x2001  & 0x0000 & TRG-ID 4,5   & TRG-ID 1,0    & TRG-ID 3,2    & Externl trigger ID    \\
570x2002  & 0x0000 & TRG-ID 4,5   & TRG-ID 1,0    & TRG-ID 3,2    & Internal trigger ID   (now just a copy\\
580x2003  & 0x0000        & 0x0000        & 0x0000        & 0x0(cid)8(bid)        & Board ID      \\
590x2004  & Temp 3        & Temp 2        & Temp 1        & Temp 0        & Temperatures \\
600x2005  & DAC 3 & DAC 2 & DAC 1 & DAC 0 & DAC values part 1     \\
610x2006  & DAC 7 & DAC 6 & DAC 5 & DAC 4 & DAC values part 2     \\
62\hline
630x2007  & 0x0030        & 0x0020        & 0x0010        & 0x0000        & chip-n-channel ID (channel group 0) \\
640x2008  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
650x2009  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
660x200A  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
670x20..  &&&&& ... \\
680x206D  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
69\hline
700x206E  & 0x0031        & 0x0021        & 0x0011        & 0x0001        & chip-n-channel ID (channel group 1) \\
710x206F  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
720x2070  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
730x2071  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
740x20..  &&&&& ... \\
750x20D4  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
76\hline
770x20..  &&&&& ... \\
78\hline
790x233F  & 0x0039        & 0x0029        & 0x0019        & 0x0009        & chip-n-channel ID (channel group 9) \\
800x2340  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
810x2341  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
820x2342  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
830x23..  &&&&& ... \\
840x23A5  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
85\hline
860x23A6  & ??    & ??    & ??    & ??    & FOOTER \\
87\hline
88\end {tabular}
89
90\caption{word order of event in Data RAM. 64bit addressing.}
91\label{64bitRAM}
92\end{table}
93
94
95During DRS readout and data digitzation, the Trigger ID is coming in through RS485 interface from FTM board.
96The Trigger ID reciption takes about $40 {\mu}$s. Therefor the 2 words containing Trigger information in the EventHeader are
97left empty in the first place. The digitazed analog data is read in as quickly as possible. Only after finishing the Readout,
98the Trigger ID is filled into the EventHeader.
99Then the EventFooter is added and the Readout is finished.
100
101\subsection{role of memory manager for DataGenerator}
102After FAD-configuration memory manager informs data generator, whether additional Data may be read out or not.
103{\tt ram write ea } is used to inform DataGenerator.\\
104
105DataGenerator needs to know how many samples to read out of each channel.
106{\tt roi max} is carriing this information. \\
107
108
109\appendix
110
111
112\end{document}
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