source: firmware/FAD/doc/memory_manager.tex @ 10743

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1\documentclass[a4paper,twoside]{article}
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14\usepackage[T1]{fontenc}
15\usepackage[utf8]{inputenc}
16
17\usepackage{graphicx} % for pictures
18\usepackage{float} % for figures (english)
19\restylefloat{figure}
20\restylefloat{table}
21
22\usepackage{arydshln}
23
24\title{FAD Data Generation}
25\author{D. Neise}
26\date{08.02.2011}
27
28\begin{document}
29
30\maketitle
31\tableofcontents
32\newpage
33
34
35\section{data order in 64bit address space}
36
37When data is input into Data-RAM by the DataGenerator, the data is fed in as words of 64bit.
38
39Each Event constists of an EventHeader, the so called ChannelData, and a small EventFooter.
40Figure (\ref{64bitRAM}) shows how the data is stored as 64bit words in the DataRAM.
41Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists 100 samples.
42\\ \\
43%\emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.}
44
45
46\begin{table}[htbp]
47\begin{tabular}{||l||l|l|l|l||l||} 
48\hline
49address & word 3 & word 2 & word 1 & word 0 & description \\
50\hline
510x2000  & 0x0000 & version      & length & 0xFB01       & Header        \\ 
520x2001  & 0x0000 & TRG ID 45    & EVT cntr 10   & EVT cntr 32   & Externl trigger ID\\
530x2002  & 0x0000 & TRG ID 45    & EVT cntr 10   & EVT cntr 32   & Internal trigger ID\\
540x2003  & 0x0000        & 0x0000        & 0x0000        & 0x0(cid)8(bid)        & Board ID      \\
550x2004  & Temp 3        & Temp 2        & Temp 1        & Temp 0        & Temperatures \\
560x2005  & DAC 3 & DAC 2 & DAC 1 & DAC 0 & DAC values part 1     \\
570x2006  & DAC 7 & DAC 6 & DAC 5 & DAC 4 & DAC values part 2     \\
58\hline
590x2007  & 0x0030        & 0x0020        & 0x0010        & 0x0000        & chip-n-channel ID (group 0) \\
600x2008  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
610x2009  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
620x200A  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
630x20..  &&&&& ... \\
640x206D  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
65\hline
660x206E  & 0x0031        & 0x0021        & 0x0011        & 0x0001        & chip-n-channel ID (group 1) \\
670x206F  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
680x2070  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
690x2071  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
700x20..  &&&&& ... \\
710x20D4  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
72\hline
730x20..  &&&&& ... \\
74\hline
750x233F  & 0x0039        & 0x0029        & 0x0019        & 0x0009        & chip-n-channel ID (group 9) \\
760x2340  & trg pos 3     & trg pos 2     & trg pos 1     & trg pos 0     & DRS stop positions \\
770x2341  & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\
780x2342  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data start of ROI \\
790x23..  &&&&& ... \\
800x23A5  & data adc3     & data adc2     & data adc1     & data adc0     & ADC Data end of ROI \\
81\hline
820x23A6  & 0x0000        & 0x0000        & 0x04FE        & 0x4242        & FOOTER \\
83\hline
84\end {tabular}
85
86\caption{word order of event in Data RAM. 64bit addressing. As of 08.02.2011}
87\label{64bitRAM}
88\end{table}
89
90
91During DRS readout and data digitzation, the Trigger ID is coming in through RS485 interface from FTM board.
92The Trigger ID reciption takes about $40 {\mu}$s. Therefor the 2 words containing Trigger information in the EventHeader are
93left empty in the first place. The digitazed analog data is read in as quickly as possible. Only after finishing the Readout,
94the Trigger ID is filled into the EventHeader.
95Then the EventFooter is added and the Readout is finished.
96
97\newpage
98\section{data order in 16bit address space}
99
100After an Event is stored in data RAM, is is ready to be read out by {\tt w5300 modul.vhd}.
101Since the FIFOs of FADs W5300 ethernet controller are of 16bit width, data is read out of the dataRAM
102as 16bit words. Empty 16bit words are left out.
103
104The following table shows how the data is ordered inside data RAM, when accessed in 16bit address space
105
106\begin{table}[htbp]
107\begin{tabular}{|l|l|l|}
108\hline
109address & 16bit word & description \\
110\hline
1110x8000  & 0xFB01        & Start Flag - fix value \\
1120x8001  & 0xllll        & package length in 16bit words \\
1130x8002  & 0xvvvv        & version - deduced from SVN revision number \\
1140x8004  & EVT cntr 32 & trigger ID upper word \\
1150x8005  & EVT cntr 10 & trigger ID lower word \\
1160x8006  & 0xAA55 & trigger type and CRC-fake \\
1170x8008  & EVT cntr 32 & trigger ID upper word \\
1180x8009  & EVT cntr 10 & trigger ID lower word \\
1190x800A  & 0xAA55 & trigger type and CRC-fake \\
1200x800C  & 0x0(cid)8(bid) & Board ID \\
1210x8010  & 0xttt0        & temperature sensor next to DRS 0 \\
1220x8011  & 0xttt1        & temperature sensor next to DRS 1 \\
1230x8012  & 0xttt2        & temperature sensor next to DRS 2 \\
1240x8013  & 0xttt3        & temperature sensor next to DRS 3 \\
1250x8014  & 0xdac0        & setting of DAC channel A \\
1260x8015  & 0xdac1        & setting of DAC channel B \\
1270x8016  & 0xdac2        & setting of DAC channel C \\
1280x8017  & 0xdac3        & setting of DAC channel D \\
1290x8018  & 0xdac4        & setting of DAC channel E \\
1300x8019  & 0xdac5        & setting of DAC channel F \\
1310x801A  & 0xdac6        & setting of DAC channel G \\
1320x801B  & 0xdac7        & setting of DAC channel H \\
133\hline
1340x801C  & 0x0000 & DRS 0 - channel 0 \\
1350x8020  & trg pos 0     & DRS 0 stop position \\
1360x8024  & ROI 00        & ROI width of this channel \\
1370x8028  & adc data 0& ADC data start \\
1380x8...  & ...           & ...data ... \\
1390x81B4  & adc data ROI-1 &      ADC data stop\\
140\hline
1410x801D  & 0x0010 & DRS 1 - channel 0 \\
1420x8021  & trg pos 1     & DRS 1 stop position \\
1430x8025  & ROI 10        & ROI width of this channel \\
1440x8029  & adc data 0& ADC data start \\
1450x8...  & ...           & ...data ... \\
1460x81B5  & adc data ROI-1 &      ADC data stop\\
147\hline
1480x8...  & ...           & ...data ... \\
149\hline
1500x8CFC  & 0x0039 & DRS 3 - channel 9 \\
1510x8D03  & trg pos 3     & DRS 3 stop position \\
1520x8D07  & ROI 39        & ROI width of this channel \\
1530x8D0B  & adc data 0& ADC data start \\
1540x8...  & ...           & ...data ... \\
1550x8E97  & adc data ROI-1 &      ADC data stop\\
156\hline
1570x8E98  & 0x4242                & packet CRC-fake \\
1580x8E99  & 0x04FE                & End Flag \\
159\hline
160\end {tabular}
161
162\caption{word order of event in Data RAM. 16bit addressing. As of 08.02.2011}
163\label{16bitRAM}
164\end{table}
165
166As one can see, the way of reading out of the RAM changes, from header to data section and again when data section ends.
167When reading the header, the addresses are increased by 1 usually and only jumps, when empty words show up in the RAM.
168One can picture it as if reading the words in each line from right to left, sometimes jumping over zeroes.
169When reading out the data sections, the words are read out as columns, i.e. addresses are incremented by 4 usually. One column is read until the data of a channel is completely read out, then either the next DRS chip is read out, which means to decrease the address or, if one group of channels was finished, the next group starts, which means address is increased by 1 only.
170The footer consisting of the CRC-16 (when finally implemented) and the end package flag is again read out by reading each word from right to left.
171
172
173\newpage
174\section{NEW data order}
175
176Some data is going to be added to the Event header changing the data order like this.
177
178\begin{table}[htbp]
179\begin{tabular}{||l||l|l|l|l||} 
180\hline
181address & word 3                                        & word 2                                & word 1                        & word 0                        \\
182\hline
1830x2000  & 12bit status + PLLLOCK        & version                               & length                        & 0xFB01                        \\
1840x2001  & 0xT1T0                                        & 0xT3T2                                & 0xT5T4                        & 0x00T6                        \\
1850x2002  & REFCLK cntr 10                        & REFCLK cntr 32                & EVT cntr 10           & EVT cntr 32           \\
1860x2003  & TRG-GEN-DIV                           & TRG-GEN-No                    & DCM-PS-STATUS         & 0x0(cid)8(bid)        \\
1870x2004  & DNA10                                         & DNA32                                 & DNA54                         & 0x00DNA6                      \\
1880x2005  & more status                           & more status                   & time10                        & time32                        \\
1890x2006  & Temp 3                                        & Temp 2                                & Temp 1                        & Temp 0                        \\
1900x2007  & DAC 3                                         & DAC 2                                 & DAC 1                         & DAC 0                         \\
1910x2008  & DAC 7                                         & DAC 6                                 & DAC 5                         & DAC 4                         \\
192\hline                 
1930x2009  & 0x0030                                        & 0x0020                                & 0x0010                        & 0x0000                        \\
1940x200A  & trg pos 3                                     & trg pos 2                             & trg pos 1                     & trg pos 0                     \\
1950x200B  & ROI 3                                         & ROI 2                                 & ROI 1                         & ROI 0                         \\
1960x200C  & -fill-                                        & -fill-                                & -fill-                        & -fill-                        \\
1970x200D  & data adc3                                     & data adc2                             & data adc1                     & data adc0                     \\
1980x20..  & ...                                           & ...                                   & ...                           & ...                           \\
1990x2070  & data adc3                                     & data adc2                             & data adc1                     & data adc0                     \\
200\hline                 
2010x20..  & ...                                           & ...                                   & ...                           & ...                           \\
202\hline                 
2030x23??  & 0x0039                                        & 0x0029                                & 0x0019                        & 0x0009                        \\
2040x23??  & trg pos 3                                     & trg pos 2                             & trg pos 1                     & trg pos 0                     \\
2050x23??  & ROI 3                                         & ROI 2                                 & ROI 1                         & ROI 0                         \\
2060x23??  & -fill-                                        & -fill-                                & -fill-                        & -fill-                        \\
2070x23??  & data adc3                                     & data adc2                             & data adc1                     & data adc0                     \\
2080x23..  & ...                                           & ...                                   & ...                           & ...                           \\
2090x23??  & data adc3                                     & data adc2                             & data adc1                     & data adc0                     \\
210\hline                 
2110x23??  & 0x0000                                        & 0x0000                                & 0x04FE                        & 0x4242                        \\
212\hline
213\end {tabular}
214\caption{NEW word order of event in Data RAM. 64bit addressing. As of > 08.02.2011}
215\label{new64bitRAM}
216\end{table}
217
218A detailed description is given after, next table.\\
219
220\newpage
221Which in turn changes the the word order in the 16bit address space like this
222\begin{table}[htbp]
223\begin{tabular}{|l|l|l|}
224\hline
225address & 16bit word & description \\
226\hline
2270x8000  & 0xFB01        & Start Flag - fix value: "FB01" \\
2280x8001  & 0xllll        & package length in 16bit words  - unsigned short - network byte order\\
2290x8002  & 0xvvvv        & version - high byte:version - low byte: subversion - network byte order \\
2300x8003  & 0xsssP        & 12 bits for status - TBD - 4 bit showing PLLLCK status unsigned short - network byte order - see \ref{subsec_explain_regs} \\ 
231\hdashline
2320x8004  & 0x00T6        & FTM trigger ID byte 6 : CRC ----------see FTM specifications ... this is just a copy\\
2330x8005  & 0xT5T4        & ... bytes 5 and 4 : Type 2 and Type 1\\
2340x8006  & 0xT3T2        & ... bytes 3 and 2     : TRG number high word \\
2350x8007  & 0xT1T0        & ... bytes 1 and 0 : TRG number low word \\ 
236\hdashline
2370x8008  & 0xev32        & FAD event counter high word \\
2380x8009  & 0xev10        & FAD event counter low word -- should be equal to T3T2T1T0\\
2390x800A  & 0xRC32        & REFCLK counter high word \\
2400x800B  & 0xRC10        & REFCLK counter low word \\ 
241\hdashline
2420x800C  & 0x0(cid)8(bid) & Board ID \\
2430x800D  & DCM-PS        & status of ADC clock phase shifter , value and locked-bit\\
2440x800E  & TRG-GEN-No& Number of Triggers to generare, when 'trigger continous' issued -- not implemented\\
2450x800F  & TRG-GEN-DIV& continous trigger generator clock prescaler \\ 
246\hdashline
2470x8010  & 0x00 DNA6     & MSB of DNA \\
2480x8011  & DNA54         & ... DNA ... \\
2490x8012  & DNA32         & ... DNA ... \\
2500x8013  & DNA10         & LSB of DNA \\
251\hdashline
2520x8014  & timer32       & timer high word -- in units of ??? \\
2530x8015  & timer10       & timer low word \\
2540x8016  & more status1 & reserved for status info; high word \\
2550x8017  & more status0 & reserved for status info; low word \\ 
256\hdashline
2570x8018  & 0xttt0        & temperature sensor next to DRS 0 \\
2580x8019  & 0xttt1        & temperature sensor next to DRS 1 \\
2590x801A  & 0xttt2        & temperature sensor next to DRS 2 \\
2600x801B  & 0xttt3        & temperature sensor next to DRS 3 \\ 
261\hdashline
2620x801C  & 0xdac0        & setting of DAC channel A \\
2630x801D  & 0xdac1        & setting of DAC channel B \\
2640x801E  & 0xdac2        & setting of DAC channel C \\
2650x801F  & 0xdac3        & setting of DAC channel D \\ 
266\hdashline
2670x8020  & 0xdac4        & setting of DAC channel E \\
2680x8021  & 0xdac5        & setting of DAC channel F \\
2690x8022  & 0xdac6        & setting of DAC channel G \\
2700x8023  & 0xdac7        & setting of DAC channel H \\ 
271\hline
2720x8...  & ...           & ...data ... \\
273\hline
274
275\end {tabular}
276\caption{word order of event in Data RAM. 16bit addressing. As of > 08.02.2011}
277\label{16bitRAM}
278\end{table}
279This new order has several advantages apart from the additional information included.
280All data may be treated as 64bit aligned. And the data readout process does not need jump over words during data sending.
281
282\newpage
283\subsection{meaning of registers ... shit title}
284\label{subsec_explain_regs}
285
286\newpage
287\subsection{new {\tt FADFormat.h}}
288
289\begin{verbatim}
290typedef struct {
291        // ------------------------------
292        unsigned short start_package_flag;
293        unsigned short package_length;
294        unsigned short version_no;
295        unsinged short PLLLCK;
296        // ------------------------------
297        unsigned short trigger_crc;
298        unsigned short tigger_type;
299        unsigned long trigger_id;
300        // ------------------------------
301        unsigned long fad_evt_counter;
302        unsigned long REFCLK_frequency;
303        // ------------------------------
304        unsigned short board_id;
305        unsigned short adc_clock_phase_shift;
306        unsgined short number_of_triggers_to_generate;
307        unsigned short trigger_generator_prescaler;
308        // ------------------------------
309        unsigned char reserved;
310        unsigned char DNA[7];   // '1' & 55 unique bits of Xilinx DNA   
311        // ------------------------------
312        unsigned long time;
313        unsigned long fad_status;
314        // ------------------------------
315        short drs_temperature[NTemp];
316        // ------------------------------       
317        unsigned short dac[NDAC];
318        // ------------------------------
319}  __attribute__((__packed__)) PEVNT_HEADER;
320
321typedef struct {
322        unsigned short id;
323        unsigned short start_cell;
324        unsigned short roi;
325        unsigned short filling;
326        unsigned short adc_data[];
327}  __attribute__((__packed__)) PCHANNEL;
328
329typedef struct {
330        unsigned short package_crc;
331        unsigned short end_package_flag;
332}  __attribute__((__packed__)) PEVNT_FOOTER;
333\end{verbatim} 
334
335\subsection{mem manager calculations}
336
337Memory manager knows the size of FADs internal data RAM. This is implemented as VHDL-Generics called RAM\_ADD\_WIDTH\_64B
338and RAM\_ADD\_WIDTH\_16B. Since word width is 64bit on the input side and 16bit on the outpt two generics are used.
339Currently the values are:
340\begin{table}[htbp]
341\begin{tabular}{ll} 
342RAM\_ADD\_WIDTH\_64B & 12 \\
343RAM\_ADD\_WIDTH\_16B & 14 \\
344\end {tabular}
345\caption{values of RAM width}
346\label{RAM_GENERICS}
347\end{table}
348
349Which results in
350\begin{equation}
351\mathtt{RAM size} = 2^{12} \cdot 8 byte= 2^14 * 2 byte = 32768 byte .
352\end{equation}
353
354Now the memory manager is able to calculate the number of Events, fitting into this RAM.
355
356The number of samples of each channel beeing digitized is called region of interest(ROI). Since the ROI of each of the 36 input channel may be defined independently, but the RAM is organized in 64bit words on the input side, the memory manager needs to calculate the effective ROI of each channel first. The DRS Chips are digitized in a parallel manner, but their 9 channels are digitized serially. So first each DRS is ordered to output its channel 0 data, until as many samples are digitized as the maximum of all channel 0 ROIs is.
357
358In the states called MAX\_ROI0..2 the array containing the maxima of each group of channels is calculated.
359In addition the so called channel size array is calculated. This is the number of 16bit words which is needed to store a group of
360channels in the W5300 FIFO. The header is included into the group of channels 0, while the package footer is included into group of channels 9.
361
362\subsubsection{state: MM CONFIG}
363Here all local variables are reset to zero. Let me shortly explain the meaning of each of them:
364\begin{table}[htbp]
365\begin{tabular}{lll} 
366        roi\_max\_array                 & array (0 to 8) of integer range 0 to 1024                                     & maximum for each channel group\\
367        channel\_size                   & array (0 to 8) of integer range 0 to W5300\_TX\_FIFO\_SIZE    & size of each channel group in 16b words \\
368        fifo\_write\_length             & array (0 to 8) of integer range 0 to W5300\_TX\_FIFO\_SIZE    & similar ??? \\
369        fifo\_channels\_array   & array (0 to 8) of integer range 0 to 9                                                & ??? \\
370        \hline \\
371        event\_size                             & integer range 0 to RAM\_SIZE\_16B                                                             & ???\\
372        event\_size\_ram                        & integer range 0 to RAM\_SIZE\_16B                                                             & ???\\
373        event\_size\_ram\_64b           & integer range 0 to RAM\_SIZE\_64B                                                             & ??? \\
374\end {tabular}
375\caption{ -no caption- -no label-}
376%\label{}
377\end{table}
378
379The input is only:
380\begin{table}[htbp]
381\begin{tabular}{lll} 
382        roi\_array                              & array (0 to 35) of integer range 0 to 1024                                    & ROI of each channel\\
383\end {tabular}
384\caption{ -no caption- -no label-}
385%\label{}
386\end{table}
387
388\subsubsection{states: MAX ROI\bf{n} and state: FIFO\_CALC} 
389\begin{itemize}
390\item find maxium in roi\_array for each channel and store it as the maximum roi of each channel group inside roi\_max\_array.
391\item calculate channel\_size(n) as $sum_{drs=0}^{3} \left( roi_{drs,n} + CHANNEL\_HEADER\_SIZE \right)$.
392For $n=0$ the size of the package header is added and for $n=8$ the size of the package footer is added to the channel\_size.
393So channel\_size(n) stores the number of 16bit words, which will be transmitted over ethernet for this particular group of channels n. \\
394Note: this is not the number of 16bit words, which will be stored inside the internal data RAM, since this number is defined by the maximum roi of each channel group.
395\item calculate into how many pieces the package need to be devided. fifo\_write\_length(m) contains a certain sum of channel\_sizes. So again
396fifo\_write\_length is a size measures in 16bit words, which will actually be transmitted over ethernet.
397\end{itemize}
398
399
400\subsubsection{states: RAM\_CALC\bf{n}}
401Here we need to know how many of these packages will fit into our data RAM.
402There           
403
404\end{document}
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