| 1 | //-----------------------------------------------------------------------------
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| 2 |
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| 3 | #include "ad7719_adc.h"
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| 4 | #include "spi_master.h"
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| 5 |
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| 6 | //-----------------------------------------------------------------------------
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| 7 |
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| 8 | void adc_init(void)
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| 9 | {
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| 10 |
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| 11 | SET_BIT(ADC_DDR,DDD4); // ADC_RST is uP Output
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| 12 | CLR_BIT(ADC_PRT,ADC_RST); // Reset ADC (active low)
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| 13 | SET_BIT(ADC_PRT,ADC_RST); // Stop Reset ADC
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| 14 |
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| 15 |
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| 16 | //Init Configure and Initialize AD7719
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| 17 | //http://designtools.analog.com/dt/adc/codegen/ad7719.html
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| 18 |
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| 19 | U8 IOCON1 = 0xC3; // power switches P1 and P2 switch to PWRGND. I-sources I1 and I2 are switched on.
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| 20 | U8 IOCON2 = 0x08; // 0x08 makes no sense... P4 is set HIGH, but is no output.
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| 21 | // U8 FILTER = 0x45; //0x45 global use 50Hz = -66dB and 60Hz = -117dB Rejectjon
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| 22 | U8 FILTER = 0x52; //0x52 euro use 50Hz = -171dB and 60Hz = -58dB Rejectjon Updaterate = 4Hz
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| 23 |
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| 24 | U8 AD1CON = 0x51;
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| 25 | // ARN bit is set->AUS ADC range is: +-REFIN2
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| 26 | // ACHo and ACH2 are set --> not defined. ???
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| 27 | // AD1EN is not set. so aux ADC is not enabled anyway.
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| 28 |
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| 29 | U8 AD0CON = 0x8E;
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| 30 | // AD0EN is set. main ADC operates according to content of mode register
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| 31 | // U/#B is set. unipolar encoding. zero is 0x000000. both full scales will be 0xFFFFFF
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| 32 | // RN2..0 = 1 ,1 ,0 --> multiplication factor 8, maybe ??
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| 33 |
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| 34 | U8 MODE = 0x02; // single conversion
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| 35 |
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| 36 | // ADC communiaction works like this:
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| 37 | // a write operation to the COM register takes place - telling the device what up next.
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| 38 | // a write or read operation to another register takes place
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| 39 | // COM register bits have the following meaning:
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| 40 | //
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| 41 | // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| 42 | // |#WEN |R/#W | zero| zero| A3 | A2 | A1 | A0 |
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| 43 | //
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| 44 | // #WEN (inversed write enable) must be zero inorder to clock more bits into the SPI interface.
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| 45 | // R/#W (read / not write) must be zero if the next operation will be a WRITE. one if the next is READ.
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| 46 | // A3-A0 denote the address of the next register.
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| 47 |
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| 48 | const U8 WR_TO_IOCON = 0x07;
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| 49 | const U8 WR_TO_FILTER = 0x04;
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| 50 | const U8 WR_TO_AD1CON = 0x03;
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| 51 | const U8 WR_TO_AD0CON = 0x02;
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| 52 | const U8 WR_TO_MODE = 0x01;
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| 53 |
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| 54 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 55 | spi_transfer_byte(WR_TO_IOCON); // Next Operation is write to IOCON1 and IOCON2 Start SPI
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| 56 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 57 |
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| 58 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 59 | spi_transfer_byte(IOCON1); // Write to IOCON1
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| 60 | spi_transfer_byte(IOCON2); // Write to IOCON2
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| 61 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 62 |
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| 63 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 64 | spi_transfer_byte(WR_TO_FILTER); // Next Operation is write to FILTER Start SPI
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| 65 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 66 |
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| 67 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 68 | spi_transfer_byte(FILTER); // Write to FILTER
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| 69 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 70 |
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| 71 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 72 | spi_transfer_byte(WR_TO_AD1CON); // Next Operation is write to AD1CON Start SPI
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| 73 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 74 |
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| 75 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 76 | spi_transfer_byte(AD1CON); // Write to AD1CON
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| 77 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 78 |
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| 79 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 80 | spi_transfer_byte(WR_TO_AD0CON); // Next Operation is write to AD0CON Start SPI
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| 81 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 82 |
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| 83 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 84 | spi_transfer_byte(AD0CON); // Write to AD0CON
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| 85 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 86 |
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| 87 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 88 | spi_transfer_byte(WR_TO_MODE); // Next Operation is write to MODE Start SPI
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| 89 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 90 |
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| 91 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 92 | spi_transfer_byte(MODE); // Write to MODE
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| 93 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 94 | }
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| 95 |
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| 96 | void startconv(void)
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| 97 | {
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| 98 | U8 COM = 0x01;
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| 99 | U8 SERIAL = 0x02;
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| 100 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 101 | spi_transfer_byte(COM); // Next Operation is write to Mode Register
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| 102 | spi_transfer_byte(SERIAL); // Start new A/D conversion
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| 103 | SET_BIT(PORTD,SPI_AD_CS);
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| 104 | COM = 0x45;
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| 105 | CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 106 | spi_transfer_byte(COM); // Next Operation is read from Main ADC Data Register
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| 107 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 108 | }
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| 109 |
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| 110 | U32 read_adc(void)
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| 111 | { CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
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| 112 | U32 value=0; // actually a 24bit value is returned
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| 113 | value |= spi_transfer_byte(0) ;
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| 114 | value =value<<8;
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| 115 | value |= spi_transfer_byte(0) ;
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| 116 | value =value<<8;
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| 117 | value |= spi_transfer_byte(0) ;
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| 118 | SET_BIT(PORTD,SPI_AD_CS); // Set CS high
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| 119 | return value;
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| 120 | }
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| 121 |
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| 122 |
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