source: firmware/FSC/src/ad7719_adc.c@ 10106

Last change on this file since 10106 was 10106, checked in by neise, 12 years ago
Niculin changed something in the presentation of the data
File size: 5.0 KB
Line 
1//-----------------------------------------------------------------------------
2
3#include "ad7719_adc.h"
4#include "spi_master.h"
5
6//-----------------------------------------------------------------------------
7
8void adc_init(void)
9{
10
11 SET_BIT(ADC_DDR,DDD4); // ADC_RST is uP Output
12 CLR_BIT(ADC_PRT,ADC_RST); // Reset ADC (active low)
13 SET_BIT(ADC_PRT,ADC_RST); // Stop Reset ADC
14
15
16 //Init Configure and Initialize AD7719
17 //http://designtools.analog.com/dt/adc/codegen/ad7719.html
18
19 U8 IOCON1 = 0xC3; // power switches P1 and P2 switch to PWRGND. I-sources I1 and I2 are switched on.
20 U8 IOCON2 = 0x08; // 0x08 makes no sense... P4 is set HIGH, but is no output.
21// U8 FILTER = 0x45; //0x45 global use 50Hz = -66dB and 60Hz = -117dB Rejectjon
22 U8 FILTER = 0x52; //0x52 euro use 50Hz = -171dB and 60Hz = -58dB Rejectjon Updaterate = 4Hz
23
24 U8 AD1CON = 0x51;
25 // ARN bit is set->AUS ADC range is: +-REFIN2
26 // ACHo and ACH2 are set --> not defined. ???
27 // AD1EN is not set. so aux ADC is not enabled anyway.
28
29 U8 AD0CON = 0x8E;
30 // AD0EN is set. main ADC operates according to content of mode register
31 // U/#B is set. unipolar encoding. zero is 0x000000. both full scales will be 0xFFFFFF
32 // RN2..0 = 1 ,1 ,0 --> multiplication factor 8, maybe ??
33
34 U8 MODE = 0x02; // single conversion
35
36 // ADC communiaction works like this:
37 // a write operation to the COM register takes place - telling the device what up next.
38 // a write or read operation to another register takes place
39 // COM register bits have the following meaning:
40 //
41 // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
42 // |#WEN |R/#W | zero| zero| A3 | A2 | A1 | A0 |
43 //
44 // #WEN (inversed write enable) must be zero inorder to clock more bits into the SPI interface.
45 // R/#W (read / not write) must be zero if the next operation will be a WRITE. one if the next is READ.
46 // A3-A0 denote the address of the next register.
47
48 const U8 WR_TO_IOCON = 0x07;
49 const U8 WR_TO_FILTER = 0x04;
50 const U8 WR_TO_AD1CON = 0x03;
51 const U8 WR_TO_AD0CON = 0x02;
52 const U8 WR_TO_MODE = 0x01;
53 const U8 RD_FROM_FILTER = 0x44;
54
55 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
56 spi_transfer_byte(RD_FROM_FILTER); // Next Operation is write to IOCON1 and IOCON2 Start SPI
57 spi_transfer_byte(0xFF); // Next Operation is write to IOCON1 and IOCON2 Start SPI
58 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
59
60
61
62
63 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
64 spi_transfer_byte(WR_TO_IOCON); // Next Operation is write to IOCON1 and IOCON2 Start SPI
65 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
66
67 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
68 spi_transfer_byte(IOCON1); // Write to IOCON1
69 spi_transfer_byte(IOCON2); // Write to IOCON2
70 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
71
72 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
73 spi_transfer_byte(WR_TO_FILTER); // Next Operation is write to FILTER Start SPI
74 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
75
76 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
77 spi_transfer_byte(FILTER); // Write to FILTER
78 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
79
80 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
81 spi_transfer_byte(WR_TO_AD1CON); // Next Operation is write to AD1CON Start SPI
82 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
83
84 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
85 spi_transfer_byte(AD1CON); // Write to AD1CON
86 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
87
88 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
89 spi_transfer_byte(WR_TO_AD0CON); // Next Operation is write to AD0CON Start SPI
90 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
91
92 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
93 spi_transfer_byte(AD0CON); // Write to AD0CON
94 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
95
96 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
97 spi_transfer_byte(WR_TO_MODE); // Next Operation is write to MODE Start SPI
98 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
99
100 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
101 spi_transfer_byte(MODE); // Write to MODE
102 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
103}
104
105 void startconv(void)
106 {
107 U8 COM = 0x01;
108 U8 SERIAL = 0x02;
109 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
110 spi_transfer_byte(COM); // Next Operation is write to Mode Register
111 spi_transfer_byte(SERIAL); // Start new A/D conversion
112 SET_BIT(PORTD,SPI_AD_CS);
113 COM = 0x45;
114 CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
115 spi_transfer_byte(COM); // Next Operation is read from Main ADC Data Register
116 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
117 }
118
119 U32 read_adc(void)
120 { CLR_BIT(PORTD,SPI_AD_CS); // Set CS low
121 U32 value=0; // actually a 24bit value is returned
122 value |= spi_transfer_byte(0) ;
123 value =value<<8;
124 value |= spi_transfer_byte(0) ;
125 value =value<<8;
126 value |= spi_transfer_byte(0) ;
127 SET_BIT(PORTD,SPI_AD_CS); // Set CS high
128 return value;
129 }
130
131
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