source: firmware/FSC/src/application.c@ 17677

#include "application.h"
#include "w5100_spi_interface.h"
#include <avr/wdt.h>

// ---------------- These are the global variables that represent the registers 
// of the entire FSC, everything is stored here and can thus be sent down ----
FSCRegisterType gReg;
volatile VolatileRegisterType gVolReg;




void app_init(void) {
    gVolReg.app_reset_source = MCUSR; // Save last reset source
    MCUSR = 0x00; // Clear reset source for next reset cycle

    // Dangerous here: I still do not know much about the watchdog.
    // This code is still from Udo Juerss. 
    // The watchdog timer is disabled by default ("startup.asm")
    #ifdef USE_WATCHDOG
        WDTCSR = WDTOE | (1 << WDE); // Enable watchdog reset (~16ms)
    #endif

    // define PORTS
    // USART
    DDRD &= ~(1<<PD0);              // PD0 = RXD is input
    DDRD |= 1<<PD1;                 // PD1 = TXD is output

    // SPARE OUT/-INPUTS
    DDRB |= (1<<PB2);           // set Out1_spare as output
    DDRB |= (1<<PB3);           // set Out2_spare as output
    DDRA &= ~(1<<PA7);          // set In1_spare as input
    DDRC &= ~(1<<PC7);          // set In2_spare as input
    //PORTA |= (1<<PA7);        // swtich on pullup on In1_spare
    //PORTC |= (1<<PC7);        // swtich on pullup on In2_spare

    // ATmega internal ADC input 
    DDRA &= ~(1<<PA6);

    // MUXER ADDRESS OUTs
    DDRA |= 0x3F; // SA-pins -> output
    DDRC |= 0x7F; // SB-pins -> output

    // SPI
    // set all CS's: output
    DDRB |= (1 << SPI_E_CS);
    DDRD |= (1 << SPI_AD_CS);
    DDRD |= (1 << SPI_M_CS);
    DDRD |= (1 << SPI_A_CS);

    // set all Chips selects HIGH
    PORTB |= (1 << SPI_E_CS);
    PORTD |= (1 << SPI_AD_CS);
    PORTD |= (1 << SPI_M_CS);
    PORTD |= (1 << SPI_A_CS);

    // set MOSI and SCK: output & // set MISO: input
    SPI_DDR |= (1 << SPI_MOSI);
    SPI_DDR |= (1 << SPI_SCLK);
    SPI_DDR &= ~(1 << SPI_MISO);

    // set MOSI, SCK: HIGH. MISO leave alone.
    SPI_PRT |= (1 << SPI_MOSI);
    SPI_PRT |= (1 << SPI_SCLK);
    //SPI_PRT |= (1 << SPI_MISO);

    // ADC 
    DDRD &= ~(1<<PD6);      // PD6 is AD_READY input
    DDRD |= 1<<PD7;         // PD7 is AD_RESET output

    // ACCELEROMETER
    DDRD &= ~(1<<PD2);      // PD2 is ACC_READY input

    //MAX6662   <--- not assembled 
    // DDRB &= ~(1<<PB0);   // PB0 is over temperature alert input
    // DDRB &= ~(1<<PB1);   // PB1 is general temperature altert input
}

// Set watchdog prescale
void app_set_watchdog_prescaler(tWDT_PRESCALE wdt_prescale) { 

  U08 sreg_backup = SREG; // Copy status register to variable
  U08 wdtcsr_value = WDE + wdt_prescale; // Set new prescale value to variable

  cli(); // Disable interrups
  wdt_reset(); // Reset watchdog

  WDTCR |= (1 << WDTOE) | (1 << WDE); // Unlock register access, 4 cycles to store new value
  WDTCR = wdtcsr_value; // Set new watchdog prescaler
  SREG = sreg_backup; // Restore status register
}


//U08* en = gReg.adc_enables;
//U08 size = VOLTAGE_CHANNELS;
U08 increase (U08 channel, U08* enables_ptr, U08 size){
    for ( U08 increase = 1 ; increase <= size; increase++) {
        U08 effective_channel = (channel + increase) % size;
        if (enables_ptr[effective_channel/8] & (1<<effective_channel%8)) {
            return effective_channel;
        }
    }
    return channel;
}
U08 increase_ad7719 (U08 channel) {
    return increase( channel, gReg.ad7719_enables, RESISTANCE_CHANNELS);
} 
U08 increase_adc (U08 channel) {
    return increase( channel, gReg.adc_enables, VOLTAGE_CHANNELS);
}


/* Explaination of bit banging:
 * an U08 array containts bitmaps, which encode, which channel is enabled and which is not.
 * a measurement is done, when all (or more) enabled channels were already measured.
 * a similar U08 array contains a bitmap, encoding which channels are already done.
 * note: "or more" above is important, if we check to strictly, 
 * we will never finish, in case a disabled channel get measured by any mistake...
 * 
 * lets assume:
 * enabled  = 1110.0011     1110.0011
 * done     = 1111.0011     0111.0010
 * 
 * and      = 1110.0011     0110.0010
 * nand     = 0001.0011     1001.1101
 * or       = 1111.0011     1111.0011
 * xor      = 0001.0000     1001.0001
 * 
 * (en xor done) and enabled =
 * xor      = 0001.0000     1001.0001
 * enabled  = 1110.0011     1110.0011
 *            ---------     ---------
 *            0000.0000     1000.0001
 * if this statement evaluates to zero, 
 * 
 * 
 * size = VOLTAGE_REGS | RESISTANCE_REGS
 * en = gReg.adc_enables | gReg.ad7719_enables
 * dry = gReg.adc_channels_ready | gReg.ad7719_channels_ready
 */
bool check_if_measurement_done(U08* en, U08*rdy, U08 size) {
    U08 temp = true;
    for ( U08 i=0; i<size; ++i ) {
        if (((en[i]^rdy[i])&en[i]) != 0x00) {
            temp = false;
            break;
        }
    }
    return temp;
}
bool check_if_adc_measurement_done() {  // operates on global gReg
    return gReg.adc_measured_all = check_if_measurement_done(
                                        gReg.adc_enables, 
                                        gReg.adc_channels_ready, 
                                        VOLTAGE_REGS);
}
bool check_if_ad7719_measurement_done() {  // operates on global gReg
    return gReg.ad7719_measured_all = check_if_measurement_done(
                                        gReg.ad7719_enables, 
                                        gReg.ad7719_channels_ready, 
                                        RESISTANCE_REGS);
}
bool check_if_measured_all() {          // operates on global gReg
    return check_if_adc_measurement_done() && check_if_ad7719_measurement_done();
}

void reset_voltage_done(){              // operates on global gReg
    for (U08 i=0; i < (VOLTAGE_REGS); i++){
        gReg.adc_channels_ready[i] = 0;
    }
}
void reset_voltage_values(){            // operates on global gReg
    for (U08 i=0; i < VOLTAGE_CHANNELS; i++){
        gReg.adc_values[i] = 0;
    }
}
void reset_resistance_done(){           // operates on global gReg
    for (U08 i=0; i < (RESISTANCE_REGS); i++){
        gReg.ad7719_channels_ready[i] = 0;
    }
}
void reset_resistance_values(){         // operates on global gReg
    for (U08 i=0; i < RESISTANCE_CHANNELS; i++){
        gReg.ad7719_values[i] = 0;
    }
}
void reset_done(){
    reset_resistance_done();
    reset_voltage_done();
}


void write_status_via_eth() { 
    gReg.ad7719_values_checksum = fletcher16( (U08*)gReg.ad7719_values, RESISTANCE_CHANNELS * sizeof(U32) );
    gReg.adc_values_checksum = fletcher16( (U08*)gReg.adc_values, VOLTAGE_CHANNELS * sizeof(U16) );
    
    U16 bytes_to_be_sent = sizeof(gReg);
    U16 bytes_already_sent = 0;
    U16 bytes_really_sent_away = 0;
    while (bytes_to_be_sent){
        bytes_really_sent_away = w5100_set_TX( (U08*)&gReg+bytes_already_sent, bytes_to_be_sent);
        bytes_to_be_sent -= bytes_really_sent_away;
        bytes_already_sent += bytes_really_sent_away;
    }
    bytes_to_be_sent = sizeof(gVolReg);
    bytes_already_sent = 0;
    bytes_really_sent_away = 0;
    while (bytes_to_be_sent){
        bytes_really_sent_away = w5100_set_TX( (U08*)&gVolReg+bytes_already_sent, bytes_to_be_sent);
        bytes_to_be_sent -= bytes_really_sent_away;
        bytes_already_sent += bytes_really_sent_away;
    }
}


U16 fletcher16( U08 const *data, U16 bytes ) {
    U16 sum1 = 0xff, sum2 = 0xff;

    while (bytes) {
            U16 tlen = bytes > 20 ? 20 : bytes;
            bytes -= tlen;
            do {
                    sum2 += sum1 += *data++;
            } while (--tlen);
            sum1 = (sum1 & 0xff) + (sum1 >> 8);
            sum2 = (sum2 & 0xff) + (sum2 >> 8);
    }
    /* Second reduction step to reduce sums to 8 bits */
    sum1 = (sum1 & 0xff) + (sum1 >> 8);
    sum2 = (sum2 & 0xff) + (sum2 >> 8);
    return sum2 << 8 | sum1;
}