source: firmware/FSC/src/spi_master.c@ 11337

Last change on this file since 11337 was 10697, checked in by neise, 15 years ago
File size: 8.4 KB
Line 
1//-----------------------------------------------------------------------------
2#include "spi_master.h"
3
4//-----------------------------------------------------------------------------
5volatile U08 spi_clock_index;
6volatile U08 spi_cpol;
7volatile U08 spi_cpha;
8volatile U08 spi_dord;
9volatile BOOL spi_ss_active_high;
10volatile U08 spi_read_buffer[SPI_READ_BUFFER_SIZE];
11volatile U08 spi_write_buffer[SPI_WRITE_BUFFER_SIZE];
12
13volatile U08 SPI_DEVICE_SS[4]={SPI_E_CS ,SPI_AD_CS ,SPI_M_CS ,SPI_A_CS };
14volatile BOOL SPI_DEVICE_ACTIVE_HIGH[4]={false ,false ,false ,false };
15//-----------------------------------------------------------------------------
16
17void spi_setup_w5100() {
18 spi_clock_index = 4; // 1Mbps
19 // this is reasonable for W5100 because of slow level shifters on the FSC.
20 // in case the slow level shifters, are improved. this value may go up to 6!
21
22 spi_dord = 0; // Data Order MSB first dord = 0 --> good for all devices
23 spi_cpol = 0; spi_cpha = 0; // SPI mode=0 good for ethernet.
24 spi_setup(); // Setup SPI bits and clock speed
25}
26
27void spi_setup_ad7719() {
28 spi_clock_index = 6; // since AD7719 is not connected via level shifters .. we can go up to 4Mbps
29
30 spi_dord = 0; // Data Order MSB first dord = 0 --> good for all devices
31 spi_cpol = 1; spi_cpha = 1; // SPI mode=3 good for AD7719.
32 spi_setup(); // Setup SPI bits and clock speed
33}
34
35
36
37
38
39void spi_init(void)
40{
41 // there are a total of 4 devices on the SPI bus:
42 // 1.) Ethernet Modul WIZ812MJ
43 // 2.) AD7719 24bit ADC
44 // 3.) LIS3LV accelerometer <---- not used yet.
45 // 4.) MAX6662 temp sensor <---- not assembled!
46
47 // We check if they all can live with the same SPI settings:
48 // 1.) Ethernet modul:
49 // supports spi mode=0 or mode=3 --> eighther cpol=cpha=0 or cpol=cpha=1
50 // THAT IS NOT TRUE!!!!
51 // only mode 0 !!!!!!!!!!!!!!!!!!!!!!!!!!!1
52 // MSB first
53 // SCLK time 70ns minimum --> 14.2MHz maximum
54 //
55 // 2.) AD7719
56 // supports mode=3 --> cpol=cpha=1
57 // MSB first
58 // SCLK time 200ns minimum --> 5MHz maximum
59 //
60 // 3.) LIS3LV
61 // SPI CLK idles high --> cpol=1
62 // data valid at rising edge. --> cpha=1 as well
63 // ==> mode 3 is supported only.
64 // MSB first, but take take at multi byte transfers. LSbyte first
65 // SCLK time - is not mentioned in the datasheet
66 //
67 // 4.) MAX6662 Tempsensor
68 // since it is not assembled, this information is not necessary.
69
70 // fastes SPI CLK frequency can be --> F_CPU/2 = 4MHz
71 // slowest can be --> F_CPU/128 = 62.5KHz
72
73 // Lets try with the fastest!
74 spi_clock_index = 4; // this is reasonable for W5100 because of slow level shifters on the FSC.
75
76 spi_dord = 0; // Data Order MSB first dord = 0 --> good for all devices
77 spi_cpol = 0; spi_cpha = 0; // SPI mode=0 good for ethernet.
78 spi_setup(); // Setup SPI bits and clock speed
79
80}
81//-----------------------------------------------------------------------------
82void spi_setup(void)
83{
84 // Disable SPI, clear all flags
85 SPCR = 0;
86
87 // Set/Clear bits DORD, CPOL and CPHA in SPI Control Register
88 spi_dord & 0x01 ? (SPCR |= (1 << DORD)) : (SPCR &= ~(1 << DORD));
89 spi_cpol & 0x01 ? (SPCR |= (1 << CPOL)) : (SPCR &= ~(1 << CPOL));
90 spi_cpha & 0x01 ? (SPCR |= (1 << CPHA)) : (SPCR &= ~(1 << CPHA));
91
92 switch (spi_clock_index)
93 {
94 case 0:{ // F_CPU / 128
95 SPCR |= (1 << SPR1) | (1 << SPR0);
96 SPSR &= ~(1 <<SPI2X);
97 }
98 break;
99
100 case 1:{ // F_CPU / 64
101 SPCR |= (1 << SPR1);
102 SPSR &= ~(1 << SPI2X);
103 }
104 break;
105
106 case 2:{ // F_CPU / 32
107 SPCR |= (1 << SPR1);
108 SPSR |= (1 << SPI2X);
109 }
110 break;
111
112 case 3:{ // F_CPU / 16
113 SPCR |= (1 << SPR0);
114 SPSR &= ~(1 << SPI2X);
115 }
116 break;
117
118 case 4:{ // F_CPU / 8
119 SPCR |= (1 << SPR0);
120 SPSR |= (1 << SPI2X);
121 }
122 break;
123
124 case 5: // F_CPU / 4
125 SPSR &= ~(1 << SPI2X);
126 break;
127
128 case 6: // F_CPU / 2
129 SPSR |= (1 << SPI2X);
130 break;
131
132 default:{ // F_CPU / 128
133 SPCR |= (1 << SPR1) | (1 << SPR0);
134 SPSR &= ~(1 << SPI2X);
135 }
136 }
137
138 // Enable SPI in Master Mode
139 SPCR |= (1 << SPE) | (1 << MSTR);
140}
141
142//-----------------------------------------------------------------------------
143
144void spi_set_clock_index(U08 clock_index)
145{
146 if (clock_index > SPI_MAX_CLOCK_INDEX)
147 {
148 clock_index = SPI_MAX_CLOCK_INDEX;
149 }
150
151 spi_clock_index = clock_index;
152
153 spi_setup(); // Setup SPI bits and clock speed
154}
155//-----------------------------------------------------------------------------
156
157void spi_set_dord(U08 dord)
158{
159 if (dord > 1)
160 {
161 dord = 1;
162 }
163
164 spi_dord = dord;
165
166 spi_setup(); // Setup SPI bits and clock speed
167}
168//-----------------------------------------------------------------------------
169
170void spi_set_cpol(U08 cpol)
171{
172 if (cpol > 1)
173 {
174 cpol = 1;
175 }
176
177 spi_cpol = cpol;
178
179 spi_setup(); // Setup SPI bits and clock speed
180}
181//-----------------------------------------------------------------------------
182
183void spi_set_cpha(U08 cpha)
184{
185 if (cpha > 1)
186 {
187 cpha = 1;
188 }
189
190 spi_cpha = cpha;
191
192 spi_setup(); // Setup SPI bits and clock speed
193}
194
195//-----------------------------------------------------------------------------
196
197void spi_transfer(U08 bytes, U08 device)
198{
199/*
200#define SPI_E_CS PB4 //device 0
201#define SPI_AD_CS PD3 //device 1
202#define SPI_M_CS PD4 //device 2
203#define SPI_A_CS PD5 //device 3
204*/
205 U08 n;
206 // Transfer requested bytes
207 for (n = 0; n < bytes; n++)
208 {
209 PORTB |= 1<< PB3;
210 // Check for active slave select level
211 if (SPI_DEVICE_ACTIVE_HIGH[device])
212 {
213 if (device == 0) {
214 PORTB |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
215 } else {
216 PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
217 }
218 }
219 else
220 {
221 if (device == 0) {
222 PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
223 } else {
224 PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
225 }
226 }
227
228 PORTB &= ~(1<< PB3);
229 spi_read_buffer[n] = spi_transfer_byte(spi_write_buffer[n]);
230 PORTB |= 1<< PB3;
231
232 // Check for inactive slave select level
233 if (SPI_DEVICE_ACTIVE_HIGH[device])
234 {
235 if (device == 0) {
236 PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
237 } else {
238 PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low
239 }
240 }
241 else
242 {
243 if (device == 0) {
244 PORTB |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
245 } else {
246 PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high
247 }
248 }
249 PORTB &= ~(1<< PB3);
250 }
251}
252//-----------------------------------------------------------------------------
253
254U08 spi_transfer_byte(U08 data)
255{
256 // Start SPI Transfer
257 if (!(SPCR & (1<<MSTR)) )
258 SPCR |= 1<<MSTR;
259 SPDR = data;
260
261 // Wait for transfer completed
262
263 while (!(SPSR & (1 << SPIF)))
264 {
265 }
266
267
268 // Return result of transfer
269 return SPDR;
270}
271
272//-----------------------------------------------------------------------------
273void spi_transfer_string(U08 length, U08* addr, U08 device)
274{
275/*
276#define SPI_E_CS PB4 //device 0
277#define SPI_AD_CS PD3 //device 1
278#define SPI_M_CS PD4 //device 2
279#define SPI_A_CS PD5 //device 3
280*/
281 U08 n;
282
283 // I assume the CS line is in "not enable"-state;
284 if ( device == 0 ){
285 TGL_BIT(PORTB, SPI_DEVICE_SS[device]); // I toggle the line
286 } else {
287 TGL_BIT(PORTD, SPI_DEVICE_SS[device]); // I toggle the line
288 }
289 // now the line is in "enable"-state
290
291
292 // Transfer requested bytes
293 for (n = 0; n < length; n++)
294 {
295 spi_transfer_byte(addr[n]);
296 }
297
298 if ( device == 0 ){
299 TGL_BIT(PORTB, SPI_DEVICE_SS[device]); // I toggle the line
300 } else {
301 TGL_BIT(PORTD, SPI_DEVICE_SS[device]); // I toggle the line
302 }
303
304}
305//-----------------------------------------------------------------------------
306
307
308//-----------------------------------------------------------------------------
309
310void spi_transfer_w5100(U08 bytes)
311{
312
313 U08 n;
314 // Transfer requested bytes
315 SPCR |= 1<<MSTR; // make sure we are still SPI MASTER ... sometimes this bit is cleared by something ... dkw?
316 for (n = 0; n < bytes; n++)
317 {
318 PORTB &= ~(1<< PB4); // SS low
319
320 SPDR = spi_write_buffer[n];
321 while (!(SPSR & (1 << SPIF)))
322 spi_read_buffer[n] = SPDR ;
323
324 PORTB |= (1<< PB4); // SS HIGH
325 }
326
327
328}
329//-----------------------------------------------------------------------------
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