source: firmware/FSC/src/w5100_spi_interface.c@ 10094

Last change on this file since 10094 was 10094, checked in by neise, 12 years ago
initial commit of FSC firmware - use for FSC testing only -
File size: 7.2 KB
Line 
1//-----------------------------------------------------------------------------
2
3#include "w5100_spi_interface.h"
4#include "spi_master.h"
5volatile BOOL sock0_connection_established = false;
6volatile U08 eth_read_buffer[ETH_READ_BUFFER_SIZE];
7volatile U08 eth_write_buffer[ETH_WRITE_BUFFER_SIZE];
8
9//-----------------------------------------------------------------------------
10
11void w5100_write( U16 addr, U08 data)
12{
13
14spi_write_buffer[0]=0xF0;
15spi_write_buffer[1]=(U08)(addr);
16spi_write_buffer[2]=(U08)(addr>>8);
17spi_write_buffer[3]=data;
18
19spi_transfer(4, 0);
20// spi_read_buffer should contain 0x00 0x01 0x02 and 0x03 ... nice check!
21}
22
23U08 w5100_read( U16 addr)
24{
25
26spi_write_buffer[0]=0x0F;
27spi_write_buffer[1]=(U08)(addr);
28spi_write_buffer[2]=(U08)(addr>>8);
29spi_write_buffer[3]=0x00;
30
31spi_transfer(4, 0);
32return spi_read_buffer[3];
33// spi_read_buffer should contain 0x00 0x01 0x02 and data ... nice check!
34}
35
36U08 w5100_init (void)
37{
38U08 sock0_status;
39
40 // set FSCs MAC Address to value defined in w5100_spi_interface.h
41 w5100_write( CM_SHAR0, FSC_MAC_ADDRESS0 );
42 w5100_write( CM_SHAR1, FSC_MAC_ADDRESS1 );
43 w5100_write( CM_SHAR2, FSC_MAC_ADDRESS2 );
44 w5100_write( CM_SHAR3, FSC_MAC_ADDRESS3 );
45 w5100_write( CM_SHAR4, FSC_MAC_ADDRESS4 );
46 w5100_write( CM_SHAR5, FSC_MAC_ADDRESS5 );
47
48 //set IP
49 w5100_write( CM_SIPR0, FSC_IP_ADDRESS0 );
50 w5100_write( CM_SIPR1, FSC_IP_ADDRESS1 );
51 w5100_write( CM_SIPR2, FSC_IP_ADDRESS2 );
52 w5100_write( CM_SIPR3, FSC_IP_ADDRESS3 );
53
54 // set subnet mask
55 w5100_write( CM_SUBR0, FSC_SUBNET_MASK0 );
56 w5100_write( CM_SUBR1, FSC_SUBNET_MASK1 );
57 w5100_write( CM_SUBR2, FSC_SUBNET_MASK2 );
58 w5100_write( CM_SUBR3, FSC_SUBNET_MASK3 );
59
60 // set IP of Gateway used by FSC
61 w5100_write( CM_GAR0, FSC_GATEWAY_ADDRESS0 );
62 w5100_write( CM_GAR1, FSC_GATEWAY_ADDRESS1 );
63 w5100_write( CM_GAR2, FSC_GATEWAY_ADDRESS2 );
64 w5100_write( CM_GAR3, FSC_GATEWAY_ADDRESS3 );
65
66 //set socket read and write fifo sizes
67 w5100_write( CM_RMSR, 0x0A); // --> 4k for socket 0 and 1
68 w5100_write( CM_TMSR, 0x0A); // --> 4k for socket 0 and 1
69
70
71 w5100_write ( S0_MR, 0x01); // set Socket 0 as TCP
72 w5100_write ( S0_PORT0, 0x13 ); // Port 5000 -> 0x1388
73 w5100_write ( S0_PORT1, 0x88 );
74 w5100_write ( S0_CR, CR_OPEN ); // issue Socket open command
75 sock0_status = w5100_read(S0_SR); // request socket 0 status
76 if ( sock0_status != SR_SOCK_INIT)
77 {
78 return sock0_status;
79 }
80
81 w5100_write ( S0_CR, CR_LISTEN ); // issue Socket listen command
82 sock0_status = w5100_read(S0_SR); // request socket 0 status
83 if ( sock0_status != SR_SOCK_LISTEN)
84 {
85 return sock0_status;
86 }
87
88 return sock0_status;
89}
90
91
92BOOL w5100_is_established()
93{
94 if ( w5100_read(S0_SR) == SR_SOCK_ESTABLISHED )
95 {
96 sock0_connection_established = true;
97 }
98 else
99 {
100 sock0_connection_established = false;
101 }
102 return sock0_connection_established;
103
104}
105
106U08 w5100_sock_status()
107{
108 return w5100_read(S0_SR);
109}
110
111
112// getters of TX and RX registers
113// S0_TX_FSR
114U16 get_S0_TX_FSR()
115{
116U16 freesize;
117freesize=w5100_read(S0_TX_FSR1);
118freesize = freesize << 8;
119freesize += w5100_read(S0_TX_FSR0);
120return freesize;
121}
122
123// S0_TX_RD
124U16 get_S0_TX_RD()
125{
126U16 readpointer;
127readpointer=w5100_read(S0_TX_RD1);
128readpointer = readpointer << 8;
129readpointer += w5100_read(S0_TX_RD0);
130return readpointer;
131}
132
133// S0_TX_WR
134U16 get_S0_TX_WR()
135{
136U16 writepointer;
137writepointer=w5100_read(S0_TX_WR1);
138writepointer = writepointer << 8;
139writepointer += w5100_read(S0_TX_WR0);
140return writepointer;
141}
142
143// S0_RX_RSR
144U16 get_S0_RX_RSR()
145{
146U16 received_size;
147received_size=w5100_read(S0_RX_RSR1);
148received_size = received_size << 8;
149received_size += w5100_read(S0_RX_RSR0);
150return received_size;
151}
152
153// S0_RX_RD
154U16 get_S0_RX_RD()
155{
156U16 readpointer;
157readpointer=w5100_read(S0_RX_RD1);
158readpointer = readpointer << 8;
159readpointer += w5100_read(S0_RX_RD0);
160return readpointer;
161}
162
163// setters for some RX and TX registers
164// S0_TX_WR
165void set_S0_TX_WR(U16 value)
166{
167U08 high_byte = (value>>8);
168U08 low_byte = (value<<8)>>8;
169w5100_write(S0_TX_WR1, high_byte);
170w5100_write(S0_TX_WR0, low_byte);
171}
172
173// S0_TX_RD
174void set_S0_RX_RD(U16 value)
175{
176U08 high_byte = (value>>8);
177U08 low_byte = (value<<8)>>8;
178w5100_write(S0_TX_RD1, high_byte);
179w5100_write(S0_TX_RD0, low_byte);
180}
181
182U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK)
183{
184 U16 size = get_S0_RX_RSR();
185 U16 upper_size, lower_size;
186 if (NumBytes > ETH_READ_BUFFER_SIZE)
187 {
188 NumBytes = ETH_READ_BUFFER_SIZE;
189 }
190 if (size == 0)
191 {
192 return 0;
193 }
194 else if ( size < NumBytes )
195 {
196 NumBytes = size;
197 }
198
199 // now calculate the offset address
200 // calculated according to W5100 datasheet page: 43
201 U16 last_RX_read_pointer = get_S0_RX_RD();
202 U16 offset = last_RX_read_pointer & S0_RX_MASK;
203 U16 start_address = S0_RX_BASE + offset;
204
205 if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem
206 {
207 upper_size = (S0_RX_MASK + 1) - offset;
208 lower_size = NumBytes - upper_size;
209 for (U08 i = 0; i < upper_size; ++i)
210 {
211 eth_read_buffer[i] = w5100_read(start_address + i);
212 }
213 for (U08 i = 0; i < lower_size; ++i)
214 {
215 eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i);
216 }
217 }
218 else // if not data turn over in RX-mem
219 {
220 for (U08 i = 0; i < NumBytes; ++i)
221 {
222 eth_read_buffer[i] = w5100_read(start_address + i);
223 }
224 }
225
226 // inform W5100 about how much data was read out.
227 set_S0_RX_RD(last_RX_read_pointer + NumBytes);
228
229 // if user wishes, W5100 may inform peer about receiption.
230 // this should be done quickly, otherwise timeout may occur on
231 // peer side, and peer retransmitts or so ...
232 //
233 // maybe it is necessary to acknowledge receiption very early.
234 // I think there is an option in Socket mode register for this.
235 if (send_ACK)
236 {
237 w5100_write ( S0_CR, CR_RECV );
238 }
239
240 return NumBytes;
241}
242
243// returns number of words, transmitted into TX - buffer.
244U08 w5100_set_TX(U08 NumBytes)
245{
246 U16 freesize = get_S0_TX_FSR();
247 if (freesize == 0)
248 {
249 return 0;
250 }
251 if (freesize < NumBytes)
252 {
253 NumBytes = freesize;
254 }
255
256 U16 last_TX_write_pointer = get_S0_TX_WR();
257 U16 offset = last_TX_write_pointer & S0_TX_MASK;
258 U16 start_address = S0_TX_BASE + offset;
259
260
261 U16 upper_size, lower_size;
262 if (NumBytes > ETH_READ_BUFFER_SIZE)
263 {
264 NumBytes = ETH_READ_BUFFER_SIZE;
265 }
266 if (freesize == 0)
267 {
268 return 0;
269 }
270 else if ( freesize < NumBytes )
271 {
272 NumBytes = freesize;
273 }
274
275 // now calculate the offset address
276 // calculated according to W5100 datasheet page: 43
277
278 if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem
279 {
280 upper_size = (S0_RX_MASK + 1) - offset;
281 lower_size = NumBytes - upper_size;
282 for (U08 i = 0; i < upper_size; ++i)
283 {
284 eth_read_buffer[i] = w5100_read(start_address + i);
285 }
286 for (U08 i = 0; i < lower_size; ++i)
287 {
288 eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i);
289 }
290 }
291 else // if not data turn over in RX-mem
292 {
293 for (U08 i = 0; i < NumBytes; ++i)
294 {
295 eth_read_buffer[i] = w5100_read(start_address + i);
296 }
297 }
298
299 // inform W5100 about how much data was read out.
300 set_S0_RX_RD(last_TX_write_pointer + NumBytes);
301
302
303 return NumBytes;
304}
305
306
307
308
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