1 | //-----------------------------------------------------------------------------
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2 |
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3 | #include "w5100_spi_interface.h"
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4 | #include "spi_master.h"
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5 | #include "usart.h"
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6 | volatile BOOL sock0_connection_established = false;
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7 | volatile U08 eth_read_buffer[ETH_READ_BUFFER_SIZE];
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8 | volatile U08 eth_write_buffer[ETH_WRITE_BUFFER_SIZE];
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9 |
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10 | //-----------------------------------------------------------------------------
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11 | // INTERFACE CONTROL VARS
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12 |
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13 | bool w5100_needs_reset = true;
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14 | bool w5100_needs_init = true;
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15 | bool w5100_ready = false;
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16 |
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17 | U08 w5100_caretaker() {
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18 | U08 socket_status;
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19 | if (w5100_needs_reset)
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20 | w5100_reset();
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21 |
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22 | socket_status = w5100_sock_status();
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23 |
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24 | if (socket_status == SR_SOCK_ESTABLISHED) {
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25 | w5100_ready = true;
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26 |
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27 | // everything is fine...
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28 | return 0;
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29 | }
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30 | else if(socket_status < SR_SOCK_ESTABLISHED) {
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31 | // it might be LISTENING ... or not even OPEN
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32 | if (socket_status == SR_SOCK_CLOSED) {
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33 | w5100_init();
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34 | }
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35 | if (socket_status == SR_SOCK_INIT) {
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36 | w5100_init();
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37 | }
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38 | if (socket_status == SR_SOCK_LISTEN) {
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39 |
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40 | }
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41 | }
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42 | else { // all other socket states need a reset
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43 | w5100_needs_reset = true;
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44 | }
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45 | w5100_ready = false;
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46 | return 1;
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47 | }
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48 |
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49 | void w5100_reset() {
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50 | PORTB &= ~(1<<PB2); //#reset = LOW --> W5100 is in reset ...
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51 | _delay_ms(50); //reset
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52 |
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53 | PORTB |= 1<<PB2; //#reset = HIGH --> W5100 is active
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54 | _delay_ms(5); // give it 5ms to accomodate.
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55 | w5100_needs_reset = false;
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56 | }
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57 |
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58 |
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59 | void w5100_write( U16 addr, U08 data)
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60 | {
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61 | // setup the SPI interface according to W5100 specs.
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62 | // This is needed, because AD7719 has different SPI specs.
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63 | spi_setup_w5100();
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64 |
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65 | spi_write_buffer[0]=0xF0;
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66 | spi_write_buffer[1]=(U08)(addr>>8);
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67 | spi_write_buffer[2]=(U08)(addr);
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68 | spi_write_buffer[3]=data;
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69 |
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70 | spi_transfer_w5100(4);
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71 | // spi_read_buffer should contain 0x00 0x01 0x02 and 0x03 ... nice check!
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72 | }
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73 |
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74 | U08 w5100_read( U16 addr)
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75 | {
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76 | // setup the SPI interface according to W5100 specs.
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77 | // This is needed, because AD7719 has different SPI specs.
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78 | spi_setup_w5100();
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79 |
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80 | spi_write_buffer[0]=0x0F;
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81 | spi_write_buffer[1]=(U08)(addr>>8);
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82 | spi_write_buffer[2]=(U08)(addr);
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83 | spi_write_buffer[3]=0x00;
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84 |
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85 | spi_transfer_w5100(4);
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86 | return spi_read_buffer[3];
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87 | // spi_read_buffer should contain 0x00 0x01 0x02 and data ... nice check!
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88 | }
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89 |
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90 | U08 w5100_init (void)
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91 | {
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92 | U08 sock0_status = 0x00;
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93 |
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94 | // set FSCs MAC Address to value defined in w5100_spi_interface.h
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95 | w5100_write( CM_SHAR0, FSC_MAC_ADDRESS0 );
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96 | w5100_write( CM_SHAR1, FSC_MAC_ADDRESS1 );
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97 | w5100_write( CM_SHAR2, FSC_MAC_ADDRESS2 );
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98 | w5100_write( CM_SHAR3, FSC_MAC_ADDRESS3 );
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99 | w5100_write( CM_SHAR4, FSC_MAC_ADDRESS4 );
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100 | w5100_write( CM_SHAR5, FSC_MAC_ADDRESS5 );
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101 |
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102 | //set IP
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103 | w5100_write( CM_SIPR0, FSC_IP_ADDRESS0 );
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104 | w5100_write( CM_SIPR1, FSC_IP_ADDRESS1 );
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105 | w5100_write( CM_SIPR2, FSC_IP_ADDRESS2 );
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106 | w5100_write( CM_SIPR3, FSC_IP_ADDRESS3 );
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107 |
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108 | // set subnet mask
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109 | w5100_write( CM_SUBR0, FSC_SUBNET_MASK0 );
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110 | w5100_write( CM_SUBR1, FSC_SUBNET_MASK1 );
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111 | w5100_write( CM_SUBR2, FSC_SUBNET_MASK2 );
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112 | w5100_write( CM_SUBR3, FSC_SUBNET_MASK3 );
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113 |
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114 | // set IP of Gateway used by FSC
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115 | w5100_write( CM_GAR0, FSC_GATEWAY_ADDRESS0 );
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116 | w5100_write( CM_GAR1, FSC_GATEWAY_ADDRESS1 );
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117 | w5100_write( CM_GAR2, FSC_GATEWAY_ADDRESS2 );
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118 | w5100_write( CM_GAR3, FSC_GATEWAY_ADDRESS3 );
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119 |
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120 | //set socket read and write fifo sizes
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121 | w5100_write( CM_RMSR, 0x0A); // --> 4k for socket 0 and 1
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122 | w5100_write( CM_TMSR, 0x0A); // --> 4k for socket 0 and 1
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123 |
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124 |
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125 | w5100_write ( S0_MR, 0x01); // set Socket 0 as TCP
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126 | w5100_write ( S0_PORT0, 0x13 ); // Port 5000 -> 0x1388
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127 | w5100_write ( S0_PORT1, 0x88 );
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128 | w5100_write ( S0_CR, CR_OPEN ); // issue Socket open command
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129 | while (sock0_status != SR_SOCK_INIT) {
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130 | sock0_status = w5100_read(S0_SR); // request socket 0 status
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131 | }
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132 |
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133 | w5100_write ( S0_CR, CR_LISTEN ); // issue Socket listen command
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134 | while (sock0_status != SR_SOCK_LISTEN) {
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135 | sock0_status = w5100_read(S0_SR); // request socket 0 status
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136 | }
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137 | return sock0_status;
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138 | }
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139 |
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140 |
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141 | BOOL w5100_is_established()
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142 | {
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143 | if ( w5100_read(S0_SR) == SR_SOCK_ESTABLISHED )
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144 | {
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145 | sock0_connection_established = true;
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146 | }
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147 | else
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148 | {
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149 | sock0_connection_established = false;
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150 | }
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151 | return sock0_connection_established;
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152 |
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153 | }
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154 |
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155 | U08 w5100_sock_status()
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156 | {
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157 | return w5100_read(S0_SR);
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158 | }
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159 |
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160 |
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161 | // getters of TX and RX registers
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162 | // S0_TX_FSR
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163 | U16 get_S0_TX_FSR()
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164 | {
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165 | U16 freesize;
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166 | freesize=w5100_read(S0_TX_FSR0);
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167 | freesize = freesize << 8;
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168 | freesize += w5100_read(S0_TX_FSR1);
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169 | return freesize;
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170 | }
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171 |
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172 | // S0_TX_RD
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173 | U16 get_S0_TX_RD()
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174 | {
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175 | U16 readpointer;
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176 | readpointer=w5100_read(S0_TX_RD0);
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177 | readpointer = readpointer << 8;
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178 | readpointer += w5100_read(S0_TX_RD1);
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179 | return readpointer;
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180 | }
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181 |
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182 | // S0_TX_WR
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183 | U16 get_S0_TX_WR()
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184 | {
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185 | U16 writepointer;
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186 | writepointer=w5100_read(S0_TX_WR0);
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187 | writepointer = writepointer << 8;
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188 | writepointer += w5100_read(S0_TX_WR1);
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189 | return writepointer;
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190 | }
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191 |
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192 | // S0_RX_RSR
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193 | U16 get_S0_RX_RSR()
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194 | {
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195 | U16 received_size;
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196 | received_size=w5100_read(S0_RX_RSR0);
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197 | received_size = received_size << 8;
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198 | received_size += w5100_read(S0_RX_RSR1); // S0_RX_RSR1 is the least significant byte ...
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199 | return received_size;
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200 | }
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201 |
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202 | // S0_RX_RD
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203 | U16 get_S0_RX_RD()
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204 | {
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205 | U16 readpointer;
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206 | readpointer=w5100_read(S0_RX_RD0);
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207 | readpointer = readpointer << 8;
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208 | readpointer += w5100_read(S0_RX_RD1);
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209 | return readpointer;
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210 | }
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211 |
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212 | // setters for some RX and TX registers
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213 | // S0_TX_WR
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214 | void set_S0_TX_WR(U16 value)
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215 | {
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216 | U08 high_byte = (value>>8);
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217 | U08 low_byte = value&0x00FF;
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218 | w5100_write(S0_TX_WR0, high_byte);
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219 | w5100_write(S0_TX_WR1, low_byte);
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220 | }
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221 |
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222 | // S0_TX_RD
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223 | void set_S0_RX_RD(U16 value)
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224 | {
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225 | U08 high_byte = (value>>8);
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226 | U08 low_byte = value&0x00FF;
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227 |
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228 | w5100_write(S0_RX_RD0, high_byte);
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229 | w5100_write(S0_RX_RD1, low_byte);
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230 | }
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231 |
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232 | U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK)
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233 | {
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234 | U16 size = get_S0_RX_RSR();
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235 | U16 upper_size, lower_size;
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236 | if (NumBytes > ETH_READ_BUFFER_SIZE)
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237 | {
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238 | NumBytes = ETH_READ_BUFFER_SIZE;
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239 | }
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240 | if (size == 0)
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241 | {
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242 | return 0;
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243 | }
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244 | else if ( size < NumBytes )
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245 | {
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246 | NumBytes = size;
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247 | }
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248 |
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249 | // now calculate the offset address
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250 | // calculated according to W5100 datasheet page: 43
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251 | U16 last_RX_read_pointer = get_S0_RX_RD();
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252 | U16 offset = last_RX_read_pointer & S0_RX_MASK;
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253 | U16 start_address = S0_RX_BASE + offset;
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254 |
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255 | if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem
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256 | {
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257 | upper_size = (S0_RX_MASK + 1) - offset;
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258 | lower_size = NumBytes - upper_size;
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259 | for (U08 i = 0; i < upper_size; ++i)
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260 | {
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261 | eth_read_buffer[i] = w5100_read(start_address + i);
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262 | }
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263 | for (U08 i = 0; i < lower_size; ++i)
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264 | {
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265 | eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i);
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266 | }
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267 | }
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268 | else // if not data turn over in RX-mem
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269 | {
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270 | for (U08 i = 0; i < NumBytes; ++i)
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271 | {
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272 | eth_read_buffer[i] = w5100_read(start_address + i);
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273 | }
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274 | }
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275 |
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276 | // inform W5100 about how much data was read out.
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277 | set_S0_RX_RD(last_RX_read_pointer + NumBytes);
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278 | w5100_write ( S0_CR, CR_RECV );
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279 |
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280 | usart_write_U16_hex(get_S0_TX_FSR()); usart_write_char('\t'); usart_write_char('|');
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281 | usart_write_U16_hex(get_S0_TX_RD()); usart_write_char('\t'); usart_write_char('|');
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282 | usart_write_U16_hex(get_S0_TX_WR()); usart_write_char('\t'); usart_write_char('|');
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283 | usart_write_U16_hex(get_S0_RX_RSR()); usart_write_char('\t'); usart_write_char('|');
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284 | usart_write_U16_hex(get_S0_RX_RD()); usart_write_char('\t'); usart_write_char('|');
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285 |
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286 | // if user wishes, W5100 may inform peer about receiption.
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287 | // this should be done quickly, otherwise timeout may occur on
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288 | // peer side, and peer retransmitts or so ...
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289 | //
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290 | // maybe it is necessary to acknowledge receiption very early.
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291 | // I think there is an option in Socket mode register for this.
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292 | if (send_ACK)
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293 | {
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294 | //w5100_write ( S0_CR, CR_RECV );
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295 | }
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296 |
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297 | return NumBytes;
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298 | }
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299 |
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300 | // returns number of words, transmitted into TX - buffer.
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301 | U16 w5100_set_TX(U08* string, U16 NumBytes) {
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302 |
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303 | U16 freesize = get_S0_TX_FSR();
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304 | if (freesize == 0)
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305 | {
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306 | return 0;
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307 | }
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308 | usart_write_str((U08*)"sending via eth: with pointer:");
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309 | usart_write_U16_hex(string);
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310 | usart_write_str((U08*)" #of bytes: ");
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311 | usart_write_U16(NumBytes,4 );
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312 | usart_write_char(' \n');
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313 |
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314 | U16 last_TX_write_pointer = get_S0_TX_WR();
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315 | U16 offset = last_TX_write_pointer & S0_TX_MASK;
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316 | U16 start_address = S0_TX_BASE + offset;
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317 |
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318 |
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319 | U16 upper_size, lower_size;
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320 | /*
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321 | if (NumBytes > ETH_WRITE_BUFFER_SIZE)
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322 | {
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323 | NumBytes = ETH_WRITE_BUFFER_SIZE;
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324 | }
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325 | if (freesize == 0)
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326 | {
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327 | return 0;
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328 | }
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329 | else */
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330 | if ( freesize < NumBytes )
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331 | {
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332 | NumBytes = freesize;
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333 | }
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334 |
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335 | // now calculate the offset address
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336 | // calculated according to W5100 datasheet page: 44
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337 |
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338 | if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem
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339 | {
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340 | upper_size = (S0_RX_MASK + 1) - offset;
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341 | lower_size = NumBytes - upper_size;
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342 | for (U08 i = 0; i < upper_size; ++i)
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343 | {
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344 | w5100_write(start_address + i, string[i]);
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345 | }
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346 | for (U08 i = 0; i < lower_size; ++i)
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347 | {
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348 | w5100_write(S0_RX_BASE + i, string[upper_size+i]);
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349 | }
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350 | }
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351 | else // if not data turn over in RX-mem
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352 | {
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353 | for (U08 i = 0; i < NumBytes; ++i)
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354 | {
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355 | w5100_write(start_address + i, string[i]);
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356 | }
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357 | }
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358 |
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359 | // inform W5100 about how much data was read out.
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360 | set_S0_TX_WR(last_TX_write_pointer + NumBytes);
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361 |
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362 | // tell it to send now the data away
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363 | w5100_write( S0_CR, CR_SEND);
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364 |
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365 | return NumBytes;
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366 | }
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367 |
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