| 1 | #ifndef __W5100_SPI_INTERFACE_H
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| 2 | #define __W5100_SPI_INTERFACE_H
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| 3 | //-----------------------------------------------------------------------------
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| 4 |
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| 5 | #include "typedefs.h"
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| 6 | #include "application.h"
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| 7 | #include "num_conversion.h"
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| 8 |
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| 9 | extern volatile BOOL sock0_connection_established;
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| 10 |
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| 11 |
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| 12 | #define ETH_READ_BUFFER_SIZE 4
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| 13 | #define ETH_WRITE_BUFFER_SIZE 32
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| 14 | extern volatile U08 eth_read_buffer[ETH_READ_BUFFER_SIZE];
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| 15 | extern volatile U08 eth_write_buffer[ETH_WRITE_BUFFER_SIZE];
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| 16 | extern U08 eth_write_index;
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| 17 | //-----------------------------------------------------------------------------
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| 18 | // Port Definitions
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| 19 | // Pin Definitions
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| 20 | // W5100 is SPI device 0
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| 21 | // -- so there is no need to define special pins.
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| 22 | // -- refer to the device by using the global buffers:
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| 23 | // volatile U08 spi_read_buffer[SPI_READ_BUFFER_SIZE];
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| 24 | // volatile U08 spi_write_buffer[SPI_WRITE_BUFFER_SIZE];
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| 25 | //
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| 26 | // and the spi function:
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| 27 | // void spi_transfer(U08 bytes, U08 device)
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| 28 | //
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| 29 | // when only sending one byte, you can do:
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| 30 | // U08 returnvalue;
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| 31 | // CLR_BIT(SPI_DEVICE_SS_PRT[0], SPI_DEVICE_SS[0]); // Set CS low
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| 32 | // returnvalue = spi_transfer_byte(0xFF);
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| 33 | // SET_BIT(SPI_DEVICE_SS_PRT[0], SPI_DEVICE_SS[0]); // Set CS high
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| 34 | //
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| 35 | // W5100 supports SPI modes 0 and 3 --> cpol/cpha= 0/0 or 1/1
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| 36 |
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| 37 | // we only use socket 0 in this application. So only a few of W5100 adresses are mentioned here
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| 38 | // W5100 MEM Addresses
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| 39 | // Common registers:
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| 40 | #define CM_MR 0x0000 // mode register
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| 41 | #define CM_GAR0 0x0001 // Gateway adress
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| 42 | #define CM_GAR1 0x0002 // Gateway adress
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| 43 | #define CM_GAR2 0x0003 // Gateway adress
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| 44 | #define CM_GAR3 0x0004 // Gateway adress
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| 45 | #define CM_SUBR0 0x0005 // Subnetmask adress
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| 46 | #define CM_SUBR1 0x0006 // Subnetmask adress
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| 47 | #define CM_SUBR2 0x0007 // Subnetmask adress
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| 48 | #define CM_SUBR3 0x0008 // Subnetmask adress
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| 49 | #define CM_SHAR0 0x0009 // Source Hardware adress: MAC
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| 50 | #define CM_SHAR1 0x000A // Source Hardware adress: MAC
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| 51 | #define CM_SHAR2 0x000B // Source Hardware adress: MAC
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| 52 | #define CM_SHAR3 0x000C // Source Hardware adress: MAC
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| 53 | #define CM_SHAR4 0x000D // Source Hardware adress: MAC
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| 54 | #define CM_SHAR5 0x000E // Source Hardware adress: MAC
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| 55 | #define CM_SIPR0 0x000F // Source IP adress
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| 56 | #define CM_SIPR1 0x0010 // Source IP adress
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| 57 | #define CM_SIPR2 0x0011 // Source IP adress
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| 58 | #define CM_SIPR3 0x0012 // Source IP adress
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| 59 | #define CM_IR 0x0015 // Interrupt
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| 60 | #define CM_IMR 0x0016 // Source IP adress
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| 61 | #define CM_RTR0 0x0017 // retry time register
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| 62 | #define CM_RTR1 0x0018 // retry time register
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| 63 | #define CM_RCR 0x0019 // Retry count
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| 64 | #define CM_RMSR 0x001A // RX mem size -- full mem size for sock0 --> value=0x03
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| 65 | #define CM_TMSR 0x001B // TX mem size -- full mem size for sock0 --> value=0x03
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| 66 |
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| 67 | // Socket 0 registers
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| 68 | #define S0_MR 0x0400 // Socket 0 mode -- for TCP value = 0x01 (set bit 5 for no delay ACK)
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| 69 | #define S0_CR 0x0401 // socket 0 command -- for commands see below
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| 70 | #define S0_IR 0x0402 // socket 0 interrupt -- see bit description below
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| 71 | #define S0_SR 0x0403 // socket 0 status -- see below
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| 72 | #define S0_PORT0 0x0404 // socket 0 Port MSB -- FSC might get port number 0x1F5C = 8028, since we have only one FSC in cam
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| 73 | #define S0_PORT1 0x0405 // socket 0 Port LSB -- 0xF5C1= 62913 is okay as well ...
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| 74 | #define S0_MSSR0 0x0412 // max segment size --
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| 75 | #define S0_MSSR1 0x0413 // max segment size -- reset value is 0xFFFF; is set to other party value, if in TCP passive mode
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| 76 | #define S0_TX_FSR0 0x0420 // socket 0 TX free size
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| 77 | #define S0_TX_FSR1 0x0421 // socket 0 TX free size
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| 78 | #define S0_TX_RD0 0x0422 // socket 0 TX read pointer -- read only:
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| 79 | #define S0_TX_RD1 0x0423 // socket 0 TX read pointer
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| 80 | #define S0_TX_WR0 0x0424 // socket 0 TX write pointer
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| 81 | #define S0_TX_WR1 0x0425 // socket 0 TX write pointer
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| 82 | #define S0_RX_RSR0 0x0426 // socket 0 RX received size
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| 83 | #define S0_RX_RSR1 0x0427 // socket 0 RX received size
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| 84 | #define S0_RX_RD0 0x0428 // socket 0 RX read pointer
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| 85 | #define S0_RX_RD1 0x0429 // socket 0 RX read pointer
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| 86 |
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| 87 |
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| 88 |
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| 89 | // some register values:
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| 90 | #define MR_TCP 0
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| 91 | #define MR_NOACKDELAY 5
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| 92 |
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| 93 | #define CR_OPEN 0x01
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| 94 | #define CR_LISTEN 0x02
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| 95 | #define CR_CONECT 0x04
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| 96 | #define CR_DISCON 0x08
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| 97 | #define CR_CLOSE 0x10
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| 98 | #define CR_SEND 0x20
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| 99 | #define CR_RECV 0x40
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| 100 | #define CR_SEND_MAC 0x21
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| 101 | #define CR_SEND_KEEP 0x22
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| 102 |
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| 103 | #define IR_SEND_OK 4
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| 104 | #define IR_TIMEOUT 3
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| 105 | #define IR_RECV 2
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| 106 | #define IR_DISCON 1
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| 107 | #define IR_CON 0
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| 108 |
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| 109 | #define SR_SOCK_CLOSED 0x00
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| 110 | #define SR_SOCK_INIT 0x13
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| 111 | #define SR_SOCK_LISTEN 0x14
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| 112 | #define SR_SOCK_ESTABLISHED 0x17
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| 113 | #define SR_SOCK_CLOSE_WAIT 0x1C
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| 114 | #define SR_SOCK_UDP 0x22
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| 115 | #define SR_SOCK_IPRAW 0x32
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| 116 | #define SR_SOCK_MACRAW 0x42
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| 117 | #define SR_SOCK_PPPOE 0x5F
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| 118 | //changing
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| 119 | #define SR_SOCK_SYNSENT 0x15
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| 120 | #define SR_SOCK_SYNRECV 0x16
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| 121 | #define SR_SOCK_FIN_WAIT 0x18
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| 122 | #define SR_SOCK_CLOSING 0x1A
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| 123 | #define SR_SOCK_TIME_WAIT 0x1B
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| 124 | #define SR_SOCK_LAST_ACK 0x1D
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| 125 | #define SR_SOCK_ARP0 0x11
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| 126 | #define SR_SOCK_ARP1 0x21
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| 127 | #define SR_SOCK_ARP2 0x31
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| 128 |
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| 129 | // low level functions
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| 130 | void w5100_write( U16 addr, U08 data);
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| 131 | U08 w5100_read( U16 addr);
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| 132 |
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| 133 | //------------------------------------------------------------------------------
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| 134 | // Description of w5100_init() function:
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| 135 | //------------------------------------------------------------------------------
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| 136 | //------------------------------------------------------------------------------
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| 137 | // BASIC SETTINGS:
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| 138 | //------------------------------------------------------------------------------
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| 139 | // leave common MR in default state: 0x00
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| 140 | // leave IMR in default state: 0x00 no interrupt will occur, since #INT line is not routed
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| 141 | // leave RTR in default state: 0x07D0 --> 200ms
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| 142 | // leave RCR in default state: 0x08, after 8 re-transmissionsm, the TIMEOUT bit in Sn_IR is set '1'
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| 143 | //------------------------------------------------------------------------------
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| 144 | // NETWORK SETTING:
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| 145 | // set GAR to FSC_GATEWAY_ADDRESS
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| 146 | //#define FSC_GATEWAY_ADDRESS0 0xC0 // 192.33.96.1
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| 147 | //#define FSC_GATEWAY_ADDRESS1 0x21
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| 148 | //#define FSC_GATEWAY_ADDRESS2 0x60
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| 149 | //#define FSC_GATEWAY_ADDRESS3 0x01
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| 150 |
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| 151 | #define FSC_GATEWAY_ADDRESS0 0xC0 // 192.168.0.1
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| 152 | #define FSC_GATEWAY_ADDRESS1 0x21
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| 153 | #define FSC_GATEWAY_ADDRESS2 0x60
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| 154 | #define FSC_GATEWAY_ADDRESS3 0x01
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| 155 |
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| 156 |
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| 157 | // set SHAR to FSC_MAC_ADDRESS
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| 158 | #define FSC_MAC_ADDRESS0 0xFA //FA:C7:0F:AD:22:01
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| 159 | #define FSC_MAC_ADDRESS1 0xC7
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| 160 | #define FSC_MAC_ADDRESS2 0x0F
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| 161 | #define FSC_MAC_ADDRESS3 0xAD
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| 162 | #define FSC_MAC_ADDRESS4 0x22
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| 163 | #define FSC_MAC_ADDRESS5 0x01
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| 164 | // set SUBR to FSC_SUBNET_MASK
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| 165 | #define FSC_SUBNET_MASK0 255 //255.255.248.0
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| 166 | #define FSC_SUBNET_MASK1 255
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| 167 | #define FSC_SUBNET_MASK2 255
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| 168 | #define FSC_SUBNET_MASK3 0
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| 169 | // set SIPR to FSC_IP_ADDRESS
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| 170 | //#define FSC_IP_ADDRESS0 0xC0 // 192.33.99.247
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| 171 | //#define FSC_IP_ADDRESS1 0x21
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| 172 | //#define FSC_IP_ADDRESS2 0x63
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| 173 | //#define FSC_IP_ADDRESS3 0xF7
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| 174 | #define FSC_IP_ADDRESS0 192 // 192.168.0.2
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| 175 | #define FSC_IP_ADDRESS1 168
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| 176 | #define FSC_IP_ADDRESS2 0
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| 177 | #define FSC_IP_ADDRESS3 2
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| 178 | //------------------------------------------------------------------------------
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| 179 | // MEM SETTINGS:
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| 180 | // we plan the possible use of 2 Sockets:
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| 181 | // Socket 0 for command input and requested data output
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| 182 | // Socket 1 as a Webserver
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| 183 | //
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| 184 | // set RMSR=0x0A --> 4k memory for Socket 0 and 1
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| 185 | #define RX_MEM_BASE 0x6000
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| 186 | #define S0_RX_BASE 0x6000 // since it is the first socket its base adress is just the RX MEM SPACE BASE
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| 187 | #define S0_RX_MASK 0x0FFF // this is 4k - 1
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| 188 | #define S1_RX_BASE 0x7000 // 2nd socket start, right after first socket
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| 189 | #define S1_RX_MASK 0x0FFF // again: 4k - 1
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| 190 | // set TMSR=0x0A --> 4k mem for each socket
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| 191 | #define TX_MEM_BASE 0x4000
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| 192 | #define S0_TX_BASE 0x4000 // since it is the first socket its base adress is just the RX MEM SPACE BASE
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| 193 | #define S0_TX_MASK 0x0FFF // this is 4k - 1
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| 194 | #define S1_TX_BASE 0x5000 // 2nd socket start, right after first socket
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| 195 | #define S1_TX_MASK 0x0FFF // again: 4k - 1
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| 196 | //------------------------------------------------------------------------------
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| 197 | U08 w5100_init();
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| 198 |
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| 199 |
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| 200 | // -- returns: TRUE if socket status is == SR_SOCK_ESTABLISHED
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| 201 | BOOL w5100_is_established();
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| 202 | // request socket status info:
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| 203 | U08 w5100_sock_status();
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| 204 |
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| 205 |
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| 206 | U16 w5100_get_received_size();
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| 207 | U16 w5100_get_start_address();
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| 208 | //-----------------------------------------------------------------------------
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| 209 | #endif //__W5100_SPI_INTERFACE_H
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| 210 |
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| 211 | U16 get_S0_TX_FSR();
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| 212 | U16 get_S0_TX_RD();
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| 213 | U16 get_S0_TX_WR();
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| 214 | U16 get_S0_RX_RSR();
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| 215 | U16 get_S0_RX_RD();
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| 216 | U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK);
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| 217 | void w5100_TX(U08 NumBytes, U08 *str);
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| 218 | U16 w5100_set_TX(U08* string, U16 NumBytes);
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| 219 |
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| 220 | extern bool w5100_needs_reset;
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| 221 | extern bool w5100_needs_init;
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| 222 | extern bool w5100_ready;
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| 223 |
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| 224 |
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| 225 |
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| 226 | U08 w5100_caretaker();
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| 227 | void w5100_reset() ;
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| 228 |
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| 229 |
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| 230 | void eth_write_str( U08* str );
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| 231 | void eth_writeln_str( U08* str ); |
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