source: firmware/FSC/src/w5100_spi_interface.h @ 10674

Last change on this file since 10674 was 10674, checked in by neise, 9 years ago
ethernet with user interface test
File size: 8.5 KB
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1#ifndef __W5100_SPI_INTERFACE_H
2#define __W5100_SPI_INTERFACE_H
3//-----------------------------------------------------------------------------
4
5#include "typedefs.h"
6#include "application.h"
7#include "num_conversion.h"
8
9extern volatile BOOL sock0_connection_established;
10
11
12#define ETH_READ_BUFFER_SIZE 32
13#define ETH_WRITE_BUFFER_SIZE 16
14extern volatile U08 eth_read_buffer[ETH_READ_BUFFER_SIZE];
15extern volatile U08 eth_write_buffer[ETH_WRITE_BUFFER_SIZE];
16//-----------------------------------------------------------------------------
17// Port Definitions
18// Pin Definitions
19// W5100 is SPI device 0
20// -- so there is no need to define special pins.
21// -- refer to the device by using the global buffers:
22//      volatile U08 spi_read_buffer[SPI_READ_BUFFER_SIZE];
23//      volatile U08 spi_write_buffer[SPI_WRITE_BUFFER_SIZE];
24//
25//      and the spi function:
26//      void spi_transfer(U08 bytes, U08 device)
27//
28//      when only sending one byte, you can do:
29//      U08 returnvalue;
30//      CLR_BIT(SPI_DEVICE_SS_PRT[0], SPI_DEVICE_SS[0]);        // Set CS low
31//      returnvalue = spi_transfer_byte(0xFF);         
32//  SET_BIT(SPI_DEVICE_SS_PRT[0], SPI_DEVICE_SS[0]);    // Set CS high
33//
34//      W5100 supports SPI modes 0 and 3  --> cpol/cpha= 0/0 or 1/1
35
36// we only use socket 0 in this application. So only a few of W5100 adresses are mentioned here
37// W5100 MEM Addresses
38// Common registers:
39#define CM_MR    0x0000         // mode register
40#define CM_GAR0  0x0001         // Gateway adress
41#define CM_GAR1  0x0002         // Gateway adress
42#define CM_GAR2  0x0003         // Gateway adress
43#define CM_GAR3  0x0004         // Gateway adress
44#define CM_SUBR0 0x0005         // Subnetmask adress
45#define CM_SUBR1 0x0006         // Subnetmask adress
46#define CM_SUBR2 0x0007         // Subnetmask adress
47#define CM_SUBR3 0x0008         // Subnetmask adress
48#define CM_SHAR0 0x0009         // Source Hardware adress: MAC
49#define CM_SHAR1 0x000A         // Source Hardware adress: MAC
50#define CM_SHAR2 0x000B         // Source Hardware adress: MAC
51#define CM_SHAR3 0x000C         // Source Hardware adress: MAC
52#define CM_SHAR4 0x000D         // Source Hardware adress: MAC
53#define CM_SHAR5 0x000E         // Source Hardware adress: MAC
54#define CM_SIPR0 0x000F         // Source IP adress
55#define CM_SIPR1 0x0010         // Source IP adress
56#define CM_SIPR2 0x0011         // Source IP adress
57#define CM_SIPR3 0x0012         // Source IP adress
58#define CM_IR    0x0015         // Interrupt
59#define CM_IMR   0x0016         // Source IP adress
60#define CM_RTR0  0x0017         // retry time register
61#define CM_RTR1  0x0018         // retry time register
62#define CM_RCR   0x0019         // Retry count
63#define CM_RMSR  0x001A         // RX mem size                                  -- full mem size for sock0 --> value=0x03
64#define CM_TMSR  0x001B         // TX mem size                                  -- full mem size for sock0 --> value=0x03
65
66// Socket 0 registers
67#define S0_MR           0x0400          // Socket 0 mode                        -- for TCP value = 0x01 (set bit 5 for no delay ACK)
68#define S0_CR           0x0401          // socket 0 command                     -- for commands see below
69#define S0_IR           0x0402          // socket 0 interrupt           -- see bit description below
70#define S0_SR           0x0403          // socket 0 status                      -- see below
71#define S0_PORT0        0x0404          // socket 0 Port MSB                    -- FSC might get port number 0x1F5C = 8028, since we have only one FSC in cam
72#define S0_PORT1        0x0405          // socket 0 Port LSB                    -- 0xF5C1= 62913 is okay as well ...
73#define S0_MSSR0        0x0412          // max segment size                     --
74#define S0_MSSR1        0x0413          // max segment size                     -- reset value is 0xFFFF; is set to other party value, if in TCP passive mode
75#define S0_TX_FSR0      0x0420          // socket 0 TX free size
76#define S0_TX_FSR1      0x0421          // socket 0 TX free size
77#define S0_TX_RD0       0x0422          // socket 0 TX read pointer     -- read only:
78#define S0_TX_RD1       0x0423          // socket 0 TX read pointer
79#define S0_TX_WR0       0x0424          // socket 0 TX write pointer
80#define S0_TX_WR1       0x0425          // socket 0 TX write pointer
81#define S0_RX_RSR0      0x0426          // socket 0 RX received size
82#define S0_RX_RSR1      0x0427          // socket 0 RX received size
83#define S0_RX_RD0       0x0428          // socket 0 RX read pointer
84#define S0_RX_RD1       0x0429          // socket 0 RX read pointer
85
86
87
88// some register values:
89#define MR_TCP                  0
90#define MR_NOACKDELAY   5
91
92#define CR_OPEN                 0x01
93#define CR_LISTEN               0x02
94#define CR_CONECT               0x04
95#define CR_DISCON               0x08
96#define CR_CLOSE                0x10
97#define CR_SEND                 0x20
98#define CR_RECV                 0x40
99#define CR_SEND_MAC             0x21
100#define CR_SEND_KEEP    0x22
101
102#define IR_SEND_OK              4
103#define IR_TIMEOUT              3
104#define IR_RECV                 2
105#define IR_DISCON               1
106#define IR_CON                  0
107
108#define SR_SOCK_CLOSED                  0x00
109#define SR_SOCK_INIT                    0x13
110#define SR_SOCK_LISTEN                  0x14
111#define SR_SOCK_ESTABLISHED             0x17
112#define SR_SOCK_CLOSE_WAIT              0x1C
113#define SR_SOCK_UDP                             0x22
114#define SR_SOCK_IPRAW                   0x32
115#define SR_SOCK_MACRAW                  0x42
116#define SR_SOCK_PPPOE                   0x5F
117//changing
118#define SR_SOCK_SYNSENT                 0x15
119#define SR_SOCK_SYNRECV                 0x16
120#define SR_SOCK_FIN_WAIT                0x18
121#define SR_SOCK_CLOSING                 0x1A
122#define SR_SOCK_TIME_WAIT               0x1B
123#define SR_SOCK_LAST_ACK                0x1D
124#define SR_SOCK_ARP0                    0x11
125#define SR_SOCK_ARP1                    0x21
126#define SR_SOCK_ARP2                    0x31
127
128// low level functions
129void w5100_write( U16 addr, U08 data);
130U08 w5100_read( U16 addr);
131
132//------------------------------------------------------------------------------
133// Description of w5100_init() function:
134//------------------------------------------------------------------------------
135//------------------------------------------------------------------------------
136// BASIC SETTINGS:
137//------------------------------------------------------------------------------
138// leave common MR in default state: 0x00
139// leave IMR in default state: 0x00 no interrupt will occur, since #INT line is not routed
140// leave RTR in default state: 0x07D0  --> 200ms
141// leave RCR in default state: 0x08, after 8 re-transmissionsm, the TIMEOUT bit in Sn_IR is set '1'
142//------------------------------------------------------------------------------
143// NETWORK SETTING:
144// set GAR to FSC_GATEWAY_ADDRESS
145//#define FSC_GATEWAY_ADDRESS0 0xC0             // 192.33.96.1
146//#define FSC_GATEWAY_ADDRESS1 0x21
147//#define FSC_GATEWAY_ADDRESS2 0x60
148//#define FSC_GATEWAY_ADDRESS3 0x01
149
150#define FSC_GATEWAY_ADDRESS0 0xC0               // 192.168.0.1
151#define FSC_GATEWAY_ADDRESS1 0x21
152#define FSC_GATEWAY_ADDRESS2 0x60
153#define FSC_GATEWAY_ADDRESS3 0x01
154
155
156// set SHAR to FSC_MAC_ADDRESS
157#define FSC_MAC_ADDRESS0 0xFA   //FA:C7:0F:AD:22:01
158#define FSC_MAC_ADDRESS1 0xC7
159#define FSC_MAC_ADDRESS2 0x0F
160#define FSC_MAC_ADDRESS3 0xAD
161#define FSC_MAC_ADDRESS4 0x22
162#define FSC_MAC_ADDRESS5 0x01
163// set SUBR to FSC_SUBNET_MASK
164#define FSC_SUBNET_MASK0 255    //255.255.248.0
165#define FSC_SUBNET_MASK1 255
166#define FSC_SUBNET_MASK2 255
167#define FSC_SUBNET_MASK3 0
168// set SIPR to FSC_IP_ADDRESS
169//#define FSC_IP_ADDRESS0 0xC0  // 192.33.99.247
170//#define FSC_IP_ADDRESS1 0x21
171//#define FSC_IP_ADDRESS2 0x63
172//#define FSC_IP_ADDRESS3 0xF7
173#define FSC_IP_ADDRESS0 192     // 192.168.0.2
174#define FSC_IP_ADDRESS1 168
175#define FSC_IP_ADDRESS2 0
176#define FSC_IP_ADDRESS3 2
177//------------------------------------------------------------------------------
178// MEM SETTINGS:
179// we plan the possible use of 2 Sockets:
180// Socket 0 for command input and requested data output
181// Socket 1 as a Webserver
182//
183// set RMSR=0x0A --> 4k memory for Socket 0 and 1
184#define RX_MEM_BASE 0x6000
185#define S0_RX_BASE  0x6000                      // since it is the first socket its base adress is just the RX MEM SPACE BASE
186#define S0_RX_MASK  0x0FFF                      // this is 4k - 1
187#define S1_RX_BASE  0x7000                      // 2nd socket start, right after first socket
188#define S1_RX_MASK  0x0FFF                      // again: 4k - 1
189// set TMSR=0x0A --> 4k mem for each socket
190#define TX_MEM_BASE 0x4000
191#define S0_TX_BASE  0x4000                      // since it is the first socket its base adress is just the RX MEM SPACE BASE
192#define S0_TX_MASK  0x0FFF                      // this is 4k - 1
193#define S1_TX_BASE  0x5000                      // 2nd socket start, right after first socket
194#define S1_TX_MASK  0x0FFF                      // again: 4k - 1
195//------------------------------------------------------------------------------
196U08 w5100_init();
197
198
199// -- returns: TRUE if socket status is == SR_SOCK_ESTABLISHED
200BOOL w5100_is_established();
201// request socket status info:
202U08 w5100_sock_status();
203
204
205U16 w5100_get_received_size();
206U16 w5100_get_start_address();
207//-----------------------------------------------------------------------------
208#endif //__W5100_SPI_INTERFACE_H
209
210U16 get_S0_TX_FSR();
211U16 get_S0_TX_RD();
212U16 get_S0_TX_WR();
213U16 get_S0_RX_RSR();
214U16 get_S0_RX_RD();
215U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK);
216void w5100_TX(U08 NumBytes, U08 *str);
217U08 w5100_set_TX(U08 NumBytes);
218
219extern bool w5100_needs_reset;
220extern bool w5100_needs_init;
221extern bool w5100_ready;
222
223
224
225U08 w5100_caretaker();
226void w5100_reset() ;
227
228
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