source: firmware/FSC/usb_src/application.c@ 13414

Last change on this file since 13414 was 10236, checked in by neise, 14 years ago
File size: 2.8 KB
Line 
1//-----------------------------------------------------------------------------
2
3#include "application.h"
4#include <avr/wdt.h>
5
6
7//-----------------------------------------------------------------------------
8
9volatile U08 app_reset_source;
10//-----------------------------------------------------------------------------
11
12void app_init(void)
13{
14 app_reset_source = MCUSR; // Save last reset source
15 MCUSR = 0x00; // Clear reset source for next reset cycle
16
17
18 // Dangerous here: I still do not know much about the watchdog.
19 // This code is still from Udo Juerss.
20
21 // The watchdog timer is disabled by default ("startup.asm")
22 #ifdef USE_WATCHDOG
23 WDTCSR = WDTOE | (1 << WDE); // Enable watchdog reset (~16ms)
24 #endif
25
26 // define PORTS
27 // USART
28 DDRD &= ~(1<<PD0); // PD0 = RXD is input
29 DDRD |= 1<<PD1; // PD1 = TXD is output
30
31
32 // SPARE OUT/-INPUTS
33 DDRB |= (1<<PB2) | (1<<PB3); // set Out1_spare & out2_spare as outputs
34 DDRA &= ~(1<<PA7); // set In1_spare as input
35 DDRC &= ~(1<<PC7); // set In2_spare as input
36 PORTA |= (1<<PA7); // swtich on pullup on In1_spare
37 PORTC |= (1<<PC7); // swtich on pullup on In2_spare
38
39 // ATmega internal ADC input
40 DDRA &= ~(1<<PA6);
41
42 // MUXER ADDRESS OUTs
43 DDRA |= 0x3F; // SA-pins -> output
44 DDRC |= 0x7F; // SB-pins -> output
45
46 // SPI
47 // set all CS's: output
48 DDRB |= (1 << SPI_E_CS);
49 DDRD |= (1 << SPI_AD_CS) |(1 << SPI_M_CS) |(1 << SPI_A_CS);
50
51 // set all Chips selects HIGH
52 PORTB |= (1 << SPI_E_CS);
53 PORTD |= (1 << SPI_AD_CS) |(1 << SPI_M_CS) |(1 << SPI_A_CS);
54
55 // set MOSI and SCK: output & // set MISO: input
56 SPI_DDR |= (1 << SPI_MOSI);
57 SPI_DDR |= (1 << SPI_SCLK);
58 SPI_DDR &= ~(1 << SPI_MISO);
59
60 // set MOSI, SCK: HIGH. MISO leave alone.
61 SPI_PRT |= (1 << SPI_MOSI);
62 SPI_PRT |= (1 << SPI_SCLK);
63 //SPI_PRT |= (1 << SPI_MISO);
64
65 // ADC
66 DDRD &= ~(1<<PD6); // PD6 is AD_READY input
67 DDRD |= 1<<PD7; // PD7 is AD_RESET output
68
69 // ACCELEROMETER
70 DDRD &= ~(1<<PD2); // PD2 is ACC_READY input
71
72 //MAX6662 <--- not assembled
73 // DDRB &= ~(1<<PB0); // PB0 is over temperature alert input
74 // DDRB &= ~(1<<PB1); // PB1 is general temperature altert input
75}
76
77
78
79//-----------------------------------------------------------------------------
80
81void app_set_watchdog_prescaler(tWDT_PRESCALE wdt_prescale) // Set watchdog prescale
82{
83 U08 sreg_backup = SREG; // Copy status register to variable
84 U08 wdtcsr_value = WDE + wdt_prescale; // Set new prescale value to variable
85
86 cli(); // Disable interrups
87 wdt_reset(); // Reset watchdog
88
89 WDTCR |= (1 << WDTOE) | (1 << WDE); // Unlock register access, 4 cycles to store new value
90 WDTCR = wdtcsr_value; // Set new watchdog prescaler
91 SREG = sreg_backup; // Restore status register
92}
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