source: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd@ 10231

Last change on this file since 10231 was 10231, checked in by vogler, 15 years ago
Check in Clock conditioner interface first version
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14 February 2010
6-- Design Name:
7-- Module Name: FTM Clock conditioner Interface
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the LMK03000 Clock conditioner
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications: February 21 2011 by Patrick Vogler
21----------------------------------------------------------------------------------
22
23library IEEE;
24use IEEE.STD_LOGIC_1164.ALL;
25use IEEE.STD_LOGIC_ARITH.ALL;
26use IEEE.STD_LOGIC_UNSIGNED.ALL;
27
28---- Uncomment the following library declaration if instantiating
29---- any Xilinx primitives in this code.
30--library UNISIM;
31--use UNISIM.VComponents.all;
32
33library ftm_definitions;
34USE ftm_definitions.ftm_array_types.all;
35USE ftm_definitions.ftm_constants.all;
36
37
38
39entity Clock_cond_interface is
40 port(
41
42
43-- Clock
44-------------------------------------------------------------------------------
45 clk : IN STD_LOGIC; -- 50 MHz system clock
46
47
48-- Clock conditioner LMK03000
49-------------------------------------------------------------------------------
50 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
51 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
52 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
53
54 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
55 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
56
57
58-- Time Marker
59-------------------------------------------------------------------------------
60 TIM_Sel : out STD_LOGIC; -- Time Marker selector
61 -- 1 = time marker from Clock conditioner
62 -- for DRS timing calibration
63 --
64 -- 0 = time marker from FPGA for normal
65 -- operation / physics run
66
67
68
69-- FPGA intern clock conditioner configuration data
70-------------------------------------------------------------------------------
71 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
72 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
73 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
74 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
75 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
76 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
77 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
78 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
79
80
81
82
83-- FPGA intern control signals
84-------------------------------------------------------------------------------
85 start_config : in STD_LOGIC; -- load new configuration into the clock
86 -- conditioner
87
88 config_started : out STD_LOGIC; -- indicates that the new configuration
89 -- is currently loaded into the clock conditioner
90
91 config_done : out STD_LOGIC; -- indicates that the configuration has
92 -- been loaded and the clock conditioners
93 -- PLL is locked
94
95 timemarker_select: in STD_LOGIC -- selects time marker source
96 --
97 -- 1 = time marker from Clock conditioner
98 -- for DRS timing calibration
99 --
100 -- 0 = time marker from FPGA for normal
101 -- operation / physics run
102
103 );
104end Clock_cond_interface;
105
106
107
108
109architecture Behavioral of Clock_cond_interface is
110
111
112component microwire_interface IS
113 PORT(
114 clk : IN std_logic;
115 clk_uwire : OUT std_logic; --- IN or OUT ?
116 data_uwire : OUT std_logic;
117 le_uwire : OUT std_logic;
118 clk_cond_array : IN clk_cond_array_type;
119 config_start : IN std_logic;
120 config_ready : OUT std_logic;
121 config_started : OUT std_logic
122 );
123end component;
124
125
126
127
128 signal clk_50M_sig : STD_LOGIC; -- system clock
129-- signal start_config_sig : STD_LOGIC;
130
131 signal config_ready_sig : STD_LOGIC;
132 signal clk_uwire_sig : STD_LOGIC;
133
134 signal config_started_sig : STD_LOGIC;
135
136 signal clk_cond_array_sig : clk_cond_array_type;
137
138 signal cc_R0_sig : std_logic_vector (31 downto 0);
139 signal cc_R1_sig : std_logic_vector (31 downto 0);
140 signal cc_R8_sig : std_logic_vector (31 downto 0);
141 signal cc_R9_sig : std_logic_vector (31 downto 0);
142 signal cc_R11_sig : std_logic_vector (31 downto 0);
143 signal cc_R13_sig : std_logic_vector (31 downto 0);
144 signal cc_R14_sig : std_logic_vector (31 downto 0);
145 signal cc_R15_sig : std_logic_vector (31 downto 0);
146
147begin
148
149 Inst_microwire_interface:microwire_interface
150 port map (
151 clk => clk_50M_sig,
152 clk_uwire => clk_uwire_sig,
153 data_uwire => DATA_Clk_Cond,
154 le_uwire => LE_Clk_Cond,
155 clk_cond_array => clk_cond_array_sig,
156
157 config_start => start_config,
158 -- config_start => start_config_sig,
159 -- config_start <= start_config_sig,
160
161 config_ready => config_ready_sig,
162 config_started => config_started_sig
163 );
164
165
166 config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration
167 -- has been loaded and
168 -- the PLL is locked again
169
170 TIM_Sel <= timemarker_select;
171 CLK_Clk_Cond <= clk_uwire_sig;
172
173 clk_50M_sig <= clk;
174 -- start_config_sig <= start_config;
175
176 -- start_config <= start_config_sig;
177
178
179 config_started <= config_started_sig;
180
181 cc_R0_sig <= cc_R0;
182 cc_R1_sig <= cc_R1;
183 cc_R8_sig <= cc_R8;
184 cc_R9_sig <= cc_R9;
185 cc_R11_sig <= cc_R11;
186 cc_R13_sig <= cc_R13;
187 cc_R14_sig <= cc_R14;
188 cc_R15_sig <= cc_R15;
189
190 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
191 -- bit 31 of register 0
192 clk_cond_array_sig(1) <= cc_R0_sig;
193 clk_cond_array_sig(2) <= cc_R1_sig;
194 clk_cond_array_sig(3) <= cc_R8_sig;
195 clk_cond_array_sig(4) <= cc_R9_sig;
196 clk_cond_array_sig(5) <= cc_R11_sig;
197 clk_cond_array_sig(6) <= cc_R13_sig;
198 clk_cond_array_sig(7) <= cc_R14_sig;
199 clk_cond_array_sig(8) <= cc_R15_sig;
200
201
202end Behavioral;
203
204
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