source: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd@ 10700

Last change on this file since 10700 was 10639, checked in by weitzel, 15 years ago
FTM: keep-alive of Wiznet actiated, clock conditioner interface updated, trigger ID sending updated
File size: 9.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14 February 2010
6-- Design Name:
7-- Module Name: FTM Clock conditioner Interface
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the LMK03000 Clock conditioner
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications: February 21 2011 by Patrick Vogler
21-- March 23 2011 by Patrick Vogler
22-- May 03 2011 by Patrick Vogler and Quirin Weitzel
23----------------------------------------------------------------------------------
24
25library IEEE;
26use IEEE.STD_LOGIC_1164.ALL;
27use IEEE.STD_LOGIC_ARITH.ALL;
28use IEEE.STD_LOGIC_UNSIGNED.ALL;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35library ftm_definitions;
36USE ftm_definitions.ftm_array_types.all;
37USE ftm_definitions.ftm_constants.all;
38
39
40entity Clock_cond_interface is
41 port(
42
43 -- Clock
44 -------------------------------------------------------------------------------
45 clk : IN STD_LOGIC; -- 50 MHz system clock
46
47
48 -- Clock conditioner LMK03000
49 -------------------------------------------------------------------------------
50 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
51 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
52 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
53
54 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
55 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
56
57
58 -- Time Marker
59 -------------------------------------------------------------------------------
60 TIM_Sel : out STD_LOGIC; -- Time Marker selector
61 -- 1 = time marker from Clock conditioner
62 -- for DRS timing calibration
63 --
64 -- 0 = time marker from FPGA for normal
65 -- operation / physics run
66
67
68 -- FPGA intern clock conditioner configuration data
69 -------------------------------------------------------------------------------
70 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
71 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
72 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
73 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
74 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
75 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
76 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
77 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
78
79
80 -- FPGA intern control signals
81 -------------------------------------------------------------------------------
82 start_config : in STD_LOGIC; -- load new configuration into the clock
83 -- conditioner
84
85 config_started : out STD_LOGIC; -- indicates that the new configuration
86 -- is currently loaded into the clock conditioner
87
88 config_done : out STD_LOGIC; -- indicates that the configuration has
89 -- been loaded and the clock conditioners
90 -- PLL is locked
91
92 timemarker_select: in STD_LOGIC -- selects time marker source
93 --
94 -- 1 = time marker from Clock conditioner
95 -- for DRS timing calibration
96 --
97 -- 0 = time marker from FPGA for normal
98 -- operation / physics run
99
100 );
101end Clock_cond_interface;
102
103
104architecture Behavioral of Clock_cond_interface is
105
106
107 component microwire_interface IS
108 PORT(
109 clk : IN std_logic;
110 clk_uwire : OUT std_logic; --- IN or OUT ?
111 data_uwire : OUT std_logic;
112 le_uwire : OUT std_logic;
113 clk_cond_array : IN clk_cond_array_type;
114 config_start : IN std_logic;
115 config_ready : OUT std_logic;
116 config_started : OUT std_logic
117 );
118 end component;
119
120
121 signal clk_50M_sig : STD_LOGIC; -- system clock
122 --signal start_config_sig : STD_LOGIC;
123
124 signal config_ready_sig : STD_LOGIC;
125 signal clk_uwire_sig : STD_LOGIC;
126
127 signal config_started_sig : STD_LOGIC;
128
129 signal clk_cond_array_sig : clk_cond_array_type;
130
131 signal cc_R0_sig : std_logic_vector (31 downto 0);
132 signal cc_R1_sig : std_logic_vector (31 downto 0);
133
134 signal cc_R2_sig : std_logic_vector (31 downto 0);
135 signal cc_R3_sig : std_logic_vector (31 downto 0);
136 signal cc_R4_sig : std_logic_vector (31 downto 0);
137 signal cc_R5_sig : std_logic_vector (31 downto 0);
138 signal cc_R6_sig : std_logic_vector (31 downto 0);
139 signal cc_R7_sig : std_logic_vector (31 downto 0);
140
141 signal cc_R8_sig : std_logic_vector (31 downto 0);
142 signal cc_R9_sig : std_logic_vector (31 downto 0);
143 signal cc_R11_sig : std_logic_vector (31 downto 0);
144 signal cc_R13_sig : std_logic_vector (31 downto 0);
145 signal cc_R14_sig : std_logic_vector (31 downto 0);
146 signal cc_R15_sig : std_logic_vector (31 downto 0);
147
148 signal timemarker_select_sig : std_logic := '0';
149
150 type TIM_SEL_STATE_TYPE is (IDLE, CONFIG);
151 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
152
153
154begin
155
156 Inst_microwire_interface:microwire_interface
157 port map (
158 clk => clk_50M_sig,
159 clk_uwire => clk_uwire_sig,
160 data_uwire => DATA_Clk_Cond,
161 le_uwire => LE_Clk_Cond,
162 clk_cond_array => clk_cond_array_sig,
163 config_start => start_config,
164
165 -- config_start => start_config_sig,
166 -- config_start <= start_config_sig,
167
168 config_ready => config_ready_sig,
169 config_started => config_started_sig
170 );
171
172
173
174 --config_done <= config_ready_sig; -- indicates that the configuration
175 -- has been loaded
176
177
178
179 config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration
180 -- has been loaded and
181 -- the PLL is locked again
182
183
184
185 --TIM_Sel <= timemarker_select;
186
187 TIM_Sel <= timemarker_select_sig;
188
189 tim_sel_proc : process (clk_uwire_sig)
190 begin
191 if rising_edge(clk_uwire_sig) then
192 case tim_sel_state is
193 when IDLE =>
194 if start_config = '1' then
195 timemarker_select_sig <= '0';
196 tim_sel_state <= CONFIG;
197 end if;
198 when CONFIG =>
199 if config_ready_sig = '1' then
200 timemarker_select_sig <= timemarker_select;
201 tim_sel_state <= IDLE;
202 end if;
203 end case;
204 end if;
205 end process tim_sel_proc;
206
207
208 CLK_Clk_Cond <= clk_uwire_sig;
209
210 clk_50M_sig <= clk;
211
212 -- start_config_sig <= start_config;
213 -- start_config <= start_config_sig;
214 config_started <= config_started_sig;
215
216 cc_R0_sig <= cc_R0;
217 cc_R1_sig <= cc_R1;
218 cc_R2_sig <= cc_R2_const;
219 cc_R3_sig <= cc_R3_const;
220 cc_R4_sig <= cc_R4_const;
221 cc_R5_sig <= cc_R5_const;
222 cc_R6_sig <= cc_R6_const;
223 cc_R7_sig <= cc_R7_const;
224 cc_R8_sig <= cc_R8;
225 cc_R9_sig <= cc_R9;
226 cc_R11_sig <= cc_R11;
227 cc_R13_sig <= cc_R13;
228 cc_R14_sig <= cc_R14;
229 cc_R15_sig <= cc_R15;
230
231 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
232 -- bit 31 of register 0
233 clk_cond_array_sig(1) <= cc_R0_sig;
234 clk_cond_array_sig(2) <= cc_R1_sig;
235
236 clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
237 clk_cond_array_sig(4) <= cc_R3_sig;
238 clk_cond_array_sig(5) <= cc_R4_sig;
239 clk_cond_array_sig(6) <= cc_R5_sig;
240 clk_cond_array_sig(7) <= cc_R6_sig;
241 clk_cond_array_sig(8) <= cc_R7_sig;
242
243 clk_cond_array_sig(9) <= cc_R8_sig;
244 clk_cond_array_sig(10) <= cc_R9_sig;
245 clk_cond_array_sig(11) <= cc_R11_sig;
246 clk_cond_array_sig(12) <= cc_R13_sig;
247 clk_cond_array_sig(13) <= cc_R14_sig;
248 clk_cond_array_sig(14) <= cc_R15_sig;
249
250end Behavioral;
Note: See TracBrowser for help on using the repository browser.