source: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd@ 11285

Last change on this file since 11285 was 10740, checked in by weitzel, 14 years ago
several bugfixes for FTM firmware
File size: 8.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14 February 2010
6-- Design Name:
7-- Module Name: FTM Clock conditioner Interface
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the LMK03000 Clock conditioner
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications: February 21 2011 by Patrick Vogler
21-- March 23 2011 by Patrick Vogler
22-- May 03 2011 by Patrick Vogler and Quirin Weitzel
23----------------------------------------------------------------------------------
24
25library IEEE;
26use IEEE.STD_LOGIC_1164.ALL;
27use IEEE.STD_LOGIC_ARITH.ALL;
28use IEEE.STD_LOGIC_UNSIGNED.ALL;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35library ftm_definitions;
36USE ftm_definitions.ftm_array_types.all;
37USE ftm_definitions.ftm_constants.all;
38
39
40entity Clock_cond_interface is
41 port(
42
43 -- Clock
44 -------------------------------------------------------------------------------
45 clk : IN STD_LOGIC; -- 50 MHz system clock
46
47 -- Clock conditioner LMK03000
48 -------------------------------------------------------------------------------
49 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
50 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
51 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
52
53 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
54 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
55
56 -- Time Marker
57 -------------------------------------------------------------------------------
58 TIM_Sel : out STD_LOGIC; -- Time Marker selector
59 -- 1 = time marker from Clock conditioner
60 -- for DRS timing calibration
61 --
62 -- 0 = time marker from FPGA for normal
63 -- operation / physics run
64
65 -- FPGA intern clock conditioner configuration data
66 -------------------------------------------------------------------------------
67 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
68 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
69 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
70 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
71 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
72 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
73 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
74 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
75
76 -- FPGA intern control signals
77 -------------------------------------------------------------------------------
78 start_config : in STD_LOGIC; -- load new configuration into the clock
79 -- conditioner
80
81 config_started : out STD_LOGIC; -- indicates that the new configuration
82 -- is currently loaded into the clock conditioner
83
84 config_done : out STD_LOGIC; -- indicates that the configuration has
85 -- been loaded and the clock conditioners
86 -- PLL is locked
87
88 timemarker_select: in STD_LOGIC -- selects time marker source
89 --
90 -- 1 = time marker from Clock conditioner
91 -- for DRS timing calibration
92 --
93 -- 0 = time marker from FPGA for normal
94 -- operation / physics run
95
96 );
97end Clock_cond_interface;
98
99
100architecture Behavioral of Clock_cond_interface is
101
102 component microwire_interface IS
103 PORT(
104 clk : IN std_logic;
105 clk_uwire : OUT std_logic;
106 data_uwire : OUT std_logic;
107 le_uwire : OUT std_logic;
108 clk_cond_array : IN clk_cond_array_type;
109 config_start : IN std_logic;
110 config_ready : OUT std_logic;
111 config_started : OUT std_logic
112 );
113 end component;
114
115 signal clk_50M_sig : STD_LOGIC; -- system clock (50MHz)
116 signal clk_uwire_sig : STD_LOGIC; -- 2 MHz
117
118 signal config_ready_sig : STD_LOGIC;
119 signal config_started_sig : STD_LOGIC;
120
121 signal clk_cond_array_sig : clk_cond_array_type;
122
123 signal cc_R0_sig : std_logic_vector (31 downto 0);
124 signal cc_R1_sig : std_logic_vector (31 downto 0);
125
126 signal cc_R2_sig : std_logic_vector (31 downto 0);
127 signal cc_R3_sig : std_logic_vector (31 downto 0);
128 signal cc_R4_sig : std_logic_vector (31 downto 0);
129 signal cc_R5_sig : std_logic_vector (31 downto 0);
130 signal cc_R6_sig : std_logic_vector (31 downto 0);
131 signal cc_R7_sig : std_logic_vector (31 downto 0);
132
133 signal cc_R8_sig : std_logic_vector (31 downto 0);
134 signal cc_R9_sig : std_logic_vector (31 downto 0);
135 signal cc_R11_sig : std_logic_vector (31 downto 0);
136 signal cc_R13_sig : std_logic_vector (31 downto 0);
137 signal cc_R14_sig : std_logic_vector (31 downto 0);
138 signal cc_R15_sig : std_logic_vector (31 downto 0);
139
140 signal timemarker_select_sig : std_logic := '0';
141
142 type TIM_SEL_STATE_TYPE is (IDLE, CONFIG);
143 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
144
145 signal load_detect_sr : std_logic_vector (1 downto 0) := "00";
146
147begin
148
149 Inst_microwire_interface:microwire_interface
150 port map (
151 clk => clk_50M_sig,
152 clk_uwire => clk_uwire_sig,
153 data_uwire => DATA_Clk_Cond,
154 le_uwire => LE_Clk_Cond,
155 clk_cond_array => clk_cond_array_sig,
156 config_start => start_config,
157 config_ready => config_ready_sig,
158 config_started => config_started_sig
159 );
160
161 sync_ld_proc : process (clk_uwire_sig)
162 begin
163 if rising_edge(clk_uwire_sig) then
164 load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond;
165 end if;
166 end process sync_ld_proc;
167
168 --config_done <= config_ready_sig; -- indicates that the configuration
169 -- has been loaded
170
171 --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration
172 -- has been loaded and
173 -- the PLL has locked
174
175 config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
176
177 TIM_Sel <= timemarker_select_sig;
178
179 tim_sel_proc : process (clk_uwire_sig)
180 begin
181 if rising_edge(clk_uwire_sig) then
182 case tim_sel_state is
183 when IDLE =>
184 if start_config = '1' then
185 timemarker_select_sig <= '0';
186 tim_sel_state <= CONFIG;
187 end if;
188 when CONFIG =>
189 if config_ready_sig = '1' then
190 timemarker_select_sig <= timemarker_select;
191 tim_sel_state <= IDLE;
192 end if;
193 end case;
194 end if;
195 end process tim_sel_proc;
196
197 CLK_Clk_Cond <= clk_uwire_sig;
198
199 clk_50M_sig <= clk;
200
201 config_started <= config_started_sig;
202
203 cc_R0_sig <= cc_R0;
204 cc_R1_sig <= cc_R1;
205 cc_R2_sig <= cc_R2_const;
206 cc_R3_sig <= cc_R3_const;
207 cc_R4_sig <= cc_R4_const;
208 cc_R5_sig <= cc_R5_const;
209 cc_R6_sig <= cc_R6_const;
210 cc_R7_sig <= cc_R7_const;
211 cc_R8_sig <= cc_R8;
212 cc_R9_sig <= cc_R9;
213 cc_R11_sig <= cc_R11;
214 cc_R13_sig <= cc_R13;
215 cc_R14_sig <= cc_R14;
216 cc_R15_sig <= cc_R15;
217
218 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
219 -- bit 31 of register 0
220 clk_cond_array_sig(1) <= cc_R0_sig;
221 clk_cond_array_sig(2) <= cc_R1_sig;
222
223 clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
224 clk_cond_array_sig(4) <= cc_R3_sig;
225 clk_cond_array_sig(5) <= cc_R4_sig;
226 clk_cond_array_sig(6) <= cc_R5_sig;
227 clk_cond_array_sig(7) <= cc_R6_sig;
228 clk_cond_array_sig(8) <= cc_R7_sig;
229
230 clk_cond_array_sig(9) <= cc_R8_sig;
231 clk_cond_array_sig(10) <= cc_R9_sig;
232 clk_cond_array_sig(11) <= cc_R11_sig;
233 clk_cond_array_sig(12) <= cc_R13_sig;
234 clk_cond_array_sig(13) <= cc_R14_sig;
235 clk_cond_array_sig(14) <= cc_R15_sig;
236
237end Behavioral;
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