source: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd@ 11651

Last change on this file since 11651 was 11648, checked in by vogler, 15 years ago
clock cond interface, new settings loaded only when changed
File size: 10.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14 February 2010
6-- Design Name:
7-- Module Name: FTM Clock conditioner Interface
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the LMK03000 Clock conditioner
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications: February 21 2011 by Patrick Vogler
21-- March 23 2011 by Patrick Vogler
22-- May 03 2011 by Patrick Vogler and Quirin Weitzel
23-- July 19 2011 by Patrick Vogler
24----------------------------------------------------------------------------------
25
26library IEEE;
27use IEEE.STD_LOGIC_1164.ALL;
28use IEEE.STD_LOGIC_ARITH.ALL;
29use IEEE.STD_LOGIC_UNSIGNED.ALL;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33--library UNISIM;
34--use UNISIM.VComponents.all;
35
36library ftm_definitions;
37USE ftm_definitions.ftm_array_types.all;
38USE ftm_definitions.ftm_constants.all;
39
40
41entity Clock_cond_interface is
42 port(
43
44 -- Clock
45 -------------------------------------------------------------------------------
46 clk : IN STD_LOGIC; -- 50 MHz system clock
47
48 -- Clock conditioner LMK03000
49 -------------------------------------------------------------------------------
50 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
51 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
52 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
53
54 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
55 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
56
57 -- Time Marker
58 -------------------------------------------------------------------------------
59 TIM_Sel : out STD_LOGIC; -- Time Marker selector
60 -- 1 = time marker from Clock conditioner
61 -- for DRS timing calibration
62 --
63 -- 0 = time marker from FPGA for normal
64 -- operation / physics run
65
66 -- FPGA intern clock conditioner configuration data
67 -------------------------------------------------------------------------------
68 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
69 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
70 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
71 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
72 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
73 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
74 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
75 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
76
77 -- FPGA intern control signals
78 -------------------------------------------------------------------------------
79 start_config : in STD_LOGIC; -- load new configuration into the clock
80 -- conditioner
81
82 config_started : out STD_LOGIC; -- indicates that the new configuration
83 -- is currently loaded into the clock conditioner
84
85 config_done : out STD_LOGIC; -- indicates that the configuration has
86 -- been loaded
87
88 -- locked : out STD_LOGIC; -- PLL in the Clock Conditioner locked
89
90 timemarker_select: in STD_LOGIC -- selects time marker source
91 --
92 -- 1 = time marker from Clock conditioner
93 -- for DRS timing calibration
94 --
95 -- 0 = time marker from FPGA for normal
96 -- operation / physics run
97
98 );
99end Clock_cond_interface;
100
101
102
103architecture Behavioral of Clock_cond_interface is
104
105 component microwire_interface IS
106 PORT(
107 clk : IN std_logic;
108 clk_uwire : OUT std_logic;
109 data_uwire : OUT std_logic;
110 le_uwire : OUT std_logic;
111 clk_cond_array : IN clk_cond_array_type;
112 config_start : IN std_logic;
113 config_ready : OUT std_logic;
114 config_started : OUT std_logic
115 );
116 end component;
117
118 signal clk_50M_sig : STD_LOGIC; -- system clock (50MHz)
119 signal clk_uwire_sig : STD_LOGIC; -- 2 MHz
120
121 signal config_ready_sig : STD_LOGIC;
122 signal config_started_sig : STD_LOGIC;
123
124
125 signal clk_cond_array_sig : clk_cond_array_type;
126
127
128-- signal cc_R0_sig : std_logic_vector (31 downto 0);
129-- signal cc_R1_sig : std_logic_vector (31 downto 0);
130
131-- signal cc_R2_sig : std_logic_vector (31 downto 0);
132-- signal cc_R3_sig : std_logic_vector (31 downto 0);
133-- signal cc_R4_sig : std_logic_vector (31 downto 0);
134-- signal cc_R5_sig : std_logic_vector (31 downto 0);
135-- signal cc_R6_sig : std_logic_vector (31 downto 0);
136-- signal cc_R7_sig : std_logic_vector (31 downto 0);
137
138-- signal cc_R8_sig : std_logic_vector (31 downto 0);
139-- signal cc_R9_sig : std_logic_vector (31 downto 0);
140-- signal cc_R11_sig : std_logic_vector (31 downto 0);
141-- signal cc_R13_sig : std_logic_vector (31 downto 0);
142-- signal cc_R14_sig : std_logic_vector (31 downto 0);
143-- signal cc_R15_sig : std_logic_vector (31 downto 0);
144
145
146
147
148 signal timemarker_select_sig : std_logic := '0';
149
150 type TIM_SEL_STATE_TYPE is (IDLE, CONFIG);
151 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
152
153 signal load_detect_sr : std_logic_vector (1 downto 0) := "00";
154
155begin
156
157 Inst_microwire_interface:microwire_interface
158 port map (
159 clk => clk_50M_sig,
160 clk_uwire => clk_uwire_sig,
161 data_uwire => DATA_Clk_Cond,
162 le_uwire => LE_Clk_Cond,
163 clk_cond_array => clk_cond_array_sig,
164 config_start => start_config,
165 config_ready => config_ready_sig,
166 config_started => config_started_sig
167 );
168
169 sync_ld_proc : process (clk_uwire_sig)
170 begin
171 if rising_edge(clk_uwire_sig) then
172 load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond;
173 end if;
174 end process sync_ld_proc;
175
176 -- config_done <= config_ready_sig; -- indicates that the configuration
177 -- has been loaded
178
179 -- config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration
180 -- has been loaded and
181 -- the PLL has locked
182
183 config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
184
185-- config_done <= config_ready_sig;
186-- locked <= load_detect_sr(1) and load_detect_sr(0);
187
188
189
190
191 TIM_Sel <= timemarker_select_sig;
192
193 tim_sel_proc : process (clk_uwire_sig)
194 begin
195 if rising_edge(clk_uwire_sig) then
196 case tim_sel_state is
197 when IDLE =>
198 if start_config = '1' then
199 timemarker_select_sig <= '0';
200 tim_sel_state <= CONFIG;
201 end if;
202 when CONFIG =>
203 if config_ready_sig = '1' then
204 timemarker_select_sig <= timemarker_select;
205 tim_sel_state <= IDLE;
206 end if;
207 end case;
208 end if;
209 end process tim_sel_proc;
210
211 CLK_Clk_Cond <= clk_uwire_sig;
212
213 clk_50M_sig <= clk;
214
215 config_started <= config_started_sig;
216
217
218-- -----------------------------------------------------------------------------
219
220-- cc_R0_sig <= cc_R0;
221-- cc_R1_sig <= cc_R1;
222
223-- cc_R2_sig <= cc_R2_const;
224-- cc_R3_sig <= cc_R3_const;
225-- cc_R4_sig <= cc_R4_const;
226-- cc_R5_sig <= cc_R5_const;
227-- cc_R6_sig <= cc_R6_const;
228-- cc_R7_sig <= cc_R7_const;
229
230-- cc_R8_sig <= cc_R8;
231-- cc_R9_sig <= cc_R9;
232-- cc_R11_sig <= cc_R11;
233-- cc_R13_sig <= cc_R13;
234-- cc_R14_sig <= cc_R14;
235-- cc_R15_sig <= cc_R15;
236
237
238
239
240
241
242
243-- clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
244-- -- bit 31 of register 0
245-- clk_cond_array_sig(1) <= cc_R0_sig;
246-- clk_cond_array_sig(2) <= cc_R1_sig;
247
248-- clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
249-- clk_cond_array_sig(4) <= cc_R3_sig;
250-- clk_cond_array_sig(5) <= cc_R4_sig;
251-- clk_cond_array_sig(6) <= cc_R5_sig;
252-- clk_cond_array_sig(7) <= cc_R6_sig;
253-- clk_cond_array_sig(8) <= cc_R7_sig; -- unused channels
254
255-- clk_cond_array_sig(9) <= cc_R8_sig;
256-- clk_cond_array_sig(10) <= cc_R9_sig;
257-- clk_cond_array_sig(11) <= cc_R11_sig;
258-- clk_cond_array_sig(12) <= cc_R13_sig;
259-- clk_cond_array_sig(13) <= cc_R14_sig;
260-- clk_cond_array_sig(14) <= cc_R15_sig;
261
262-- -----------------------------------------------------------------------------
263
264
265 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
266 -- bit 31 of register 0
267 clk_cond_array_sig(1) <= cc_R0;
268 clk_cond_array_sig(2) <= cc_R1;
269
270 clk_cond_array_sig(3) <= cc_R2_const; -- unused channels
271 clk_cond_array_sig(4) <= cc_R3_const;
272 clk_cond_array_sig(5) <= cc_R4_const;
273 clk_cond_array_sig(6) <= cc_R5_const;
274 clk_cond_array_sig(7) <= cc_R6_const;
275 clk_cond_array_sig(8) <= cc_R7_const; -- unused channels
276
277 clk_cond_array_sig(9) <= cc_R8;
278 clk_cond_array_sig(10) <= cc_R9;
279 clk_cond_array_sig(11) <= cc_R11;
280 clk_cond_array_sig(12) <= cc_R13;
281 clk_cond_array_sig(13) <= cc_R14;
282 clk_cond_array_sig(14) <= cc_R15;
283
284
285end Behavioral;
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