source: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd@ 13414

Last change on this file since 13414 was 11653, checked in by vogler, 13 years ago
clock cond interface with PLL lock seperate
File size: 7.4 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14 February 2010
6-- Design Name:
7-- Module Name: FTM Clock conditioner Interface
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the LMK03000 Clock conditioner
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications: February 21 2011 by Patrick Vogler
21-- March 23 2011 by Patrick Vogler
22-- May 03 2011 by Patrick Vogler and Quirin Weitzel
23-- July 19 2011 by Patrick Vogler
24-- July 27 2011 by Patrick Vogler
25----------------------------------------------------------------------------------
26
27library IEEE;
28use IEEE.STD_LOGIC_1164.ALL;
29use IEEE.STD_LOGIC_ARITH.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31
32---- Uncomment the following library declaration if instantiating
33---- any Xilinx primitives in this code.
34--library UNISIM;
35--use UNISIM.VComponents.all;
36
37library ftm_definitions;
38USE ftm_definitions.ftm_array_types.all;
39USE ftm_definitions.ftm_constants.all;
40
41
42entity Clock_cond_interface is
43 port(
44
45 -- Clock
46 -------------------------------------------------------------------------------
47 clk : IN STD_LOGIC; -- 50 MHz system clock
48
49 -- Clock conditioner LMK03000
50 -------------------------------------------------------------------------------
51 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
52 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
53 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
54
55 SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
56 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
57
58 -- Time Marker
59 -------------------------------------------------------------------------------
60 TIM_Sel : out STD_LOGIC; -- Time Marker selector
61 -- 1 = time marker from Clock conditioner
62 -- for DRS timing calibration
63 --
64 -- 0 = time marker from FPGA for normal
65 -- operation / physics run
66
67 -- FPGA intern clock conditioner configuration data
68 -------------------------------------------------------------------------------
69 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
70 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
71 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
72 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
73 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
74 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
75 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
76 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
77
78 -- FPGA intern control signals
79 -------------------------------------------------------------------------------
80 start_config : in STD_LOGIC; -- load new configuration into the clock
81 -- conditioner
82
83 config_started : out STD_LOGIC; -- indicates that the new configuration
84 -- is currently loaded into the clock conditioner
85
86 config_done : out STD_LOGIC; -- indicates that the configuration has
87 -- been loaded
88
89 locked : out STD_LOGIC; -- PLL in the Clock Conditioner locked
90
91 timemarker_select: in STD_LOGIC -- selects time marker source
92 --
93 -- 1 = time marker from Clock conditioner
94 -- for DRS timing calibration
95 --
96 -- 0 = time marker from FPGA for normal
97 -- operation / physics run
98
99 );
100end Clock_cond_interface;
101
102
103
104architecture Behavioral of Clock_cond_interface is
105
106 component microwire_interface IS
107 PORT(
108 clk : IN std_logic;
109 clk_uwire : OUT std_logic;
110 data_uwire : OUT std_logic;
111 le_uwire : OUT std_logic;
112 clk_cond_array : IN clk_cond_array_type;
113 config_start : IN std_logic;
114 config_ready : OUT std_logic;
115 config_started : OUT std_logic
116 );
117 end component;
118
119 signal clk_50M_sig : STD_LOGIC; -- system clock (50MHz)
120 signal clk_uwire_sig : STD_LOGIC; -- 2 MHz
121
122 signal config_ready_sig : STD_LOGIC;
123 signal config_started_sig : STD_LOGIC;
124
125 signal clk_cond_array_sig : clk_cond_array_type;
126
127 signal timemarker_select_sig : std_logic := '0';
128
129 type TIM_SEL_STATE_TYPE is (IDLE, CONFIG);
130 signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
131
132 signal load_detect_sr : std_logic_vector (1 downto 0) := "00";
133
134begin
135
136 Inst_microwire_interface:microwire_interface
137 port map (
138 clk => clk_50M_sig,
139 clk_uwire => clk_uwire_sig,
140 data_uwire => DATA_Clk_Cond,
141 le_uwire => LE_Clk_Cond,
142 clk_cond_array => clk_cond_array_sig,
143 config_start => start_config,
144 config_ready => config_ready_sig,
145 config_started => config_started_sig
146 );
147
148 sync_ld_proc : process (clk_uwire_sig)
149 begin
150 if rising_edge(clk_uwire_sig) then
151 load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond;
152 end if;
153 end process sync_ld_proc;
154
155-- config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
156
157 config_done <= config_ready_sig;
158 locked <= load_detect_sr(1) and load_detect_sr(0);
159
160
161
162
163 TIM_Sel <= timemarker_select_sig;
164
165 tim_sel_proc : process (clk_uwire_sig)
166 begin
167 if rising_edge(clk_uwire_sig) then
168 case tim_sel_state is
169 when IDLE =>
170 if start_config = '1' then
171 timemarker_select_sig <= '0';
172 tim_sel_state <= CONFIG;
173 end if;
174 when CONFIG =>
175 if config_ready_sig = '1' then
176 timemarker_select_sig <= timemarker_select;
177 tim_sel_state <= IDLE;
178 end if;
179 end case;
180 end if;
181 end process tim_sel_proc;
182
183 CLK_Clk_Cond <= clk_uwire_sig;
184
185 clk_50M_sig <= clk;
186
187 config_started <= config_started_sig;
188
189 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting
190 -- bit 31 of register 0
191 clk_cond_array_sig(1) <= cc_R0;
192 clk_cond_array_sig(2) <= cc_R1;
193
194 clk_cond_array_sig(3) <= cc_R2_const; -- unused channels
195 clk_cond_array_sig(4) <= cc_R3_const;
196 clk_cond_array_sig(5) <= cc_R4_const;
197 clk_cond_array_sig(6) <= cc_R5_const;
198 clk_cond_array_sig(7) <= cc_R6_const;
199 clk_cond_array_sig(8) <= cc_R7_const; -- unused channels
200
201 clk_cond_array_sig(9) <= cc_R8;
202 clk_cond_array_sig(10) <= cc_R9;
203 clk_cond_array_sig(11) <= cc_R11;
204 clk_cond_array_sig(12) <= cc_R13;
205 clk_cond_array_sig(13) <= cc_R14;
206 clk_cond_array_sig(14) <= cc_R15;
207
208
209end Behavioral;
Note: See TracBrowser for help on using the repository browser.