source: firmware/FTM/Clock_cond_interface/microwire_controller.vhd@ 10316

Last change on this file since 10316 was 10231, checked in by vogler, 14 years ago
Check in Clock conditioner interface first version
File size: 3.4 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.spi_controller.beha
3--
4-- Created:
5-- by - Benjamin Krumm.UNKNOWN (EEPC8)
6-- at - 10:37:20 12.04.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10-- modified by Q. Weitzel
11--
12-------------------------------------------------------------------------------
13--
14-- modified by Patrick Vogler
15-- February 17 2011
16-- September 17 2010
17--
18-- modified to be used as a Microwire interface to control the clock
19-- conditioner LMK03000 on the FTM board
20-------------------------------------------------------------------------------
21
22LIBRARY ieee;
23USE ieee.std_logic_1164.all;
24USE ieee.std_logic_arith.all;
25USE ieee.std_logic_unsigned.all;
26
27
28library ftm_definitions;
29USE ftm_definitions.ftm_array_types.all;
30USE ftm_definitions.ftm_constants.all;
31
32
33
34ENTITY microwire_controller IS
35 PORT(
36 clk_uwire : IN std_logic; -- sclk
37 data_uwire : OUT std_logic := '0'; -- mosi
38 le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select
39
40 clk_cond_array : IN clk_cond_array_type; -- data to be loaded
41 -- into the clock conditioner
42 config_start : IN std_logic;
43 config_ready : OUT std_logic := '0';
44 config_started : OUT std_logic := '0'
45 );
46END microwire_controller ;
47
48
49ARCHITECTURE beha OF microwire_controller IS
50
51 type TYPE_uWire_STATE is (IDLE, LOAD_SHIFT_REG, SHIFT);
52 signal uwire_state : TYPE_uWire_STATE := IDLE;
53 signal register_count : integer range 0 to LMK03000_REGISTER_COUNT := 0;
54 signal bit_count : integer range 0 to LMK03000_REGISTER_WIDTH := 0;
55 signal shift_reg : std_logic_vector (LMK03000_REGISTER_WIDTH - 1 downto 0) := (others => '0');
56
57
58
59BEGIN
60
61 uwire_write_proc: process (clk_uwire)
62 begin
63
64 if falling_edge(clk_uwire) then
65
66 case uwire_state is
67
68 when IDLE =>
69
70 le_uwire <= '1';
71 config_ready <= '1';
72 config_started <= '0';
73 bit_count <= 0;
74 register_count <= 0;
75 data_uwire <= '0';
76
77 if (config_start = '1') then
78 config_ready <= '0';
79 uwire_state <= LOAD_SHIFT_REG;
80 end if;
81
82
83 when LOAD_SHIFT_REG =>
84 bit_count <= 0;
85 config_started <= '1';
86 shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0);
87 register_count <= register_count + 1;
88-- le_uwire <= '0';
89 uwire_state <= SHIFT;
90
91
92 when SHIFT =>
93 data_uwire <= shift_reg(LMK03000_REGISTER_WIDTH - 1);
94 le_uwire <= '0';
95 shift_reg <= shift_reg(LMK03000_REGISTER_WIDTH - 2 downto 0) & shift_reg(LMK03000_REGISTER_WIDTH - 1);
96 bit_count <= bit_count + 1;
97 if ((bit_count = LMK03000_REGISTER_WIDTH)AND(register_count = LMK03000_REGISTER_COUNT)) then
98 le_uwire <= '1';
99 uwire_state <= IDLE;
100 elsif ((bit_count =LMK03000_REGISTER_WIDTH )AND(NOT(register_count = LMK03000_REGISTER_COUNT))) then
101 le_uwire <= '1';
102 uwire_state <= LOAD_SHIFT_REG;
103 else
104 uwire_state <= SHIFT;
105 end if;
106
107 end case;
108 end if;
109
110 end process uwire_write_proc;
111
112END ARCHITECTURE beha;
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