source: firmware/FTM/Clock_cond_interface/microwire_controller.vhd@ 19205

Last change on this file since 19205 was 11648, checked in by vogler, 14 years ago
clock cond interface, new settings loaded only when changed
File size: 4.1 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.spi_controller.beha
3--
4-- Created:
5-- by - Benjamin Krumm.UNKNOWN (EEPC8)
6-- at - 10:37:20 12.04.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10-- modified by Q. Weitzel
11--
12-------------------------------------------------------------------------------
13--
14-- modified by Patrick Vogler
15-- February 17 2011
16-- September 17 2010
17--
18-- modified to be used as a Microwire interface to control the clock
19-- conditioner LMK03000 on the FTM board
20--
21-- modified July 19 2011 by Patrick Vogler
22--
23-------------------------------------------------------------------------------
24
25LIBRARY ieee;
26USE ieee.std_logic_1164.all;
27USE ieee.std_logic_arith.all;
28USE ieee.std_logic_unsigned.all;
29
30
31library ftm_definitions;
32USE ftm_definitions.ftm_array_types.all;
33USE ftm_definitions.ftm_constants.all;
34
35
36
37ENTITY microwire_controller IS
38 PORT(
39 clk_uwire : IN std_logic; -- sclk
40 data_uwire : OUT std_logic := '0'; -- mosi
41 le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select
42
43 clk_cond_array : IN clk_cond_array_type; -- data to be loaded
44 -- into the clock conditioner
45
46 config_start : IN std_logic;
47 config_ready : OUT std_logic := '0';
48 config_started : OUT std_logic := '0'
49 );
50END microwire_controller ;
51
52
53ARCHITECTURE beha OF microwire_controller IS
54
55 type TYPE_uWire_STATE is (IDLE, LOAD_SHIFT_REG, SHIFT);
56 signal uwire_state : TYPE_uWire_STATE := IDLE;
57 signal register_count : integer range 0 to LMK03000_REGISTER_COUNT := 0;
58 signal bit_count : integer range 0 to LMK03000_REGISTER_WIDTH := 0;
59 signal shift_reg : std_logic_vector (LMK03000_REGISTER_WIDTH - 1 downto 0) := (others => '0');
60
61 signal clk_cond_array_update : clk_cond_array_type := (others => (others => '0'));
62
63
64
65
66
67BEGIN
68
69 uwire_write_proc: process (clk_uwire)
70 begin
71
72 if falling_edge(clk_uwire) then
73
74 case uwire_state is
75
76 when IDLE =>
77
78 le_uwire <= '1';
79 config_ready <= '1';
80 config_started <= '0';
81 bit_count <= 0;
82 register_count <= 0;
83 data_uwire <= '0';
84
85 if (config_start = '1') then
86 config_ready <= '0';
87 uwire_state <= LOAD_SHIFT_REG;
88 end if;
89
90
91-------------------------------------------------------------------------------
92-- send new data only when settings changed
93
94 when LOAD_SHIFT_REG =>
95
96 if (clk_cond_array_update = clk_cond_array) then -- compare old and new settings
97 config_started <= '1';
98 uwire_state <= IDLE; -- do nothing if settings didn't change
99
100 else -- program new (changed !!) settings to clock conditioner
101 bit_count <= 0;
102 config_started <= '1';
103 shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0);
104 register_count <= register_count + 1;
105 uwire_state <= SHIFT;
106
107 end if;
108-------------------------------------------------------------------------------
109
110
111 when SHIFT =>
112 data_uwire <= shift_reg(LMK03000_REGISTER_WIDTH - 1);
113 le_uwire <= '0';
114 shift_reg <= shift_reg(LMK03000_REGISTER_WIDTH - 2 downto 0) & shift_reg(LMK03000_REGISTER_WIDTH - 1);
115 bit_count <= bit_count + 1;
116 if ((bit_count = LMK03000_REGISTER_WIDTH)AND(register_count = LMK03000_REGISTER_COUNT)) then
117 le_uwire <= '1';
118 clk_cond_array_update <= clk_cond_array; -- get a copy of the date for comparison lateron
119 uwire_state <= IDLE;
120 elsif ((bit_count =LMK03000_REGISTER_WIDTH )AND(NOT(register_count = LMK03000_REGISTER_COUNT))) then
121 le_uwire <= '1';
122 uwire_state <= LOAD_SHIFT_REG;
123 else
124 uwire_state <= SHIFT;
125 end if;
126
127 end case;
128 end if;
129
130 end process uwire_write_proc;
131
132END ARCHITECTURE beha;
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