source: firmware/FTM/FTM_central_control.vhd@ 11565

Last change on this file since 11565 was 11485, checked in by weitzel, 14 years ago
FTM firmware features now the config_single_FTU command (to be tested); also some defaults were changed
File size: 20.5 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_start_lp : out std_logic := '0';
68 config_started_lp : in std_logic;
69 config_ready_lp : in std_logic;
70 config_trigger : out std_logic := '0';
71 config_trigger_done : in std_logic;
72 dna_start : out std_logic := '0';
73 dna_ready : in std_logic;
74 crate_reset : IN std_logic;
75 crate_reset_ack : OUT std_logic := '0';
76 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
77 start_run : IN std_logic;
78 start_run_ack : OUT std_logic := '0';
79 stop_run : IN std_logic;
80 stop_run_ack : OUT std_logic := '0';
81 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
82 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
83 start_run_param : IN std_logic_vector (15 DOWNTO 0);
84 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
85 trigger_start : out std_logic := '0';
86 trigger_stop : out std_logic := '1';
87 enable_ID_sending : out std_logic := '0';
88 reset_timer : out std_logic := '0';
89 crate_res_0 : out std_logic := '1';
90 crate_res_1 : out std_logic := '1';
91 crate_res_2 : out std_logic := '1';
92 crate_res_3 : out std_logic := '1';
93 new_config_ftu : in std_logic; -- from ethernet_modul
94 new_config_ftu_ack : out std_logic := '0'; -- to ethernet_modul
95 config_single_FTU : out std_logic := '0'; -- to ftu_control
96 config_single_FTU_started : in std_logic; -- from ftu_control
97 config_single_FTU_done : in std_logic -- from ftu_control
98 );
99end FTM_central_control;
100
101architecture Behavioral of FTM_central_control is
102
103 signal reset_scaler_sig : std_logic := '0';
104 signal reset_period_sig : std_logic := '0';
105 signal scaler_counts_sig : integer := 0;
106 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
107 signal period_finished_sig : std_logic := '0';
108 signal wait_cnt_sig : integer range 0 to 10 := 0;
109 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
110 signal new_period_sig : std_logic := '0';
111 signal new_period_ack_sig : std_logic := '0';
112 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
113 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0;
114 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0) := (others => '0');
115
116 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
117 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
118 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
119 CP_CONFIG_CC, CP_CONFIG_CC_01,
120 CP_CONFIG_LP, CP_CONFIG_LP_01,
121 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
122 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
123 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
124 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
125 CP_SEND_START, CP_SEND_END,
126 CP_CRATE_RESET, CP_CRATE_RESET_01, CP_CRATE_RESET_ACK,
127 CP_CFG_SINGLE_FTU, CP_CFG_SINGLE_FTU_01, CP_CFG_SINGLE_FTU_02, CP_CFG_SINGLE_FTU_ACK);
128 signal state_central_proc : state_central_proc_type := CP_INIT;
129
130 signal after_rates_state : state_central_proc_type := CP_IDLE;
131 signal after_ping_state : state_central_proc_type := CP_IDLE;
132
133begin
134
135 --central_proc : process (clk, prescaling_FTU01)
136 central_proc : process (clk)
137 begin
138 if rising_edge (clk) then
139 case state_central_proc is
140
141 when CP_INIT => -- wait for DCMs to lock
142 current_cc_state <= X"FFFF";
143 cc_state_test <= X"01";
144 if (clk_ready = '1') then
145 state_central_proc <= CP_INIT_DNA;
146 end if;
147
148 when CP_INIT_DNA => -- get FPGA DNA
149 current_cc_state <= X"FFFF";
150 cc_state_test <= X"01";
151 if (dna_ready = '1') then
152 state_central_proc <= CP_INIT_TIMER;
153 dna_start <= '0';
154 reset_timer <= '1'; -- reset timer after power-up
155 else
156 dna_start <= '1';
157 state_central_proc <= CP_INIT_DNA;
158 end if;
159
160 when CP_INIT_TIMER =>
161 current_cc_state <= X"FFFF";
162 cc_state_test <= X"01";
163 reset_timer <= '0'; -- finish reset timer after power-up
164 state_central_proc <= CP_CONFIG;
165
166 when CP_CONFIG_START =>
167 current_cc_state <= FTM_STATE_CFG;
168 cc_state_test <= X"02";
169 if (config_started_ack = '1') then
170 config_started <= '0';
171 state_central_proc <= CP_CONFIG;
172 end if;
173
174 when CP_CONFIG =>
175 current_cc_state <= FTM_STATE_CFG;
176 cc_state_test <= X"03";
177 config_start_eth <= '1';
178 if (config_started_eth = '1') then
179 config_start_eth <= '0';
180 state_central_proc <= CP_CONFIG_01;
181 end if;
182
183 when CP_CONFIG_01 =>
184 current_cc_state <= FTM_STATE_CFG;
185 cc_state_test <= X"04";
186 if (config_ready_eth = '1') then
187 state_central_proc <= CP_CONFIG_CC;
188 --state_central_proc <= CP_CONFIG_SCALER;
189 --state_central_proc <= CP_IDLE;
190 --state_central_proc <= CP_CRATE_RESET;
191 end if;
192
193 when CP_CONFIG_CC =>
194 current_cc_state <= FTM_STATE_CFG;
195 cc_state_test <= X"05";
196 config_start_cc <= '1';
197 if (config_started_cc = '1') then
198 config_start_cc <= '0';
199 state_central_proc <= CP_CONFIG_CC_01;
200 end if;
201
202 when CP_CONFIG_CC_01 =>
203 current_cc_state <= FTM_STATE_CFG;
204 cc_state_test <= X"06";
205 if (config_ready_cc = '1') then
206 state_central_proc <= CP_CONFIG_LP;
207 --state_central_proc <= CP_CONFIG_FTU;
208 end if;
209
210 when CP_CONFIG_LP =>
211 current_cc_state <= FTM_STATE_CFG;
212 cc_state_test <= X"1C";
213 config_start_lp <= '1';
214 if (config_started_lp = '1') then
215 config_start_lp <= '0';
216 state_central_proc <= CP_CONFIG_LP_01;
217 end if;
218
219 when CP_CONFIG_LP_01 =>
220 current_cc_state <= FTM_STATE_CFG;
221 cc_state_test <= X"1D";
222 if (config_ready_lp = '1') then
223 state_central_proc <= CP_CONFIG_FTU;
224 end if;
225
226 when CP_CONFIG_FTU =>
227 current_cc_state <= FTM_STATE_CFG;
228 cc_state_test <= X"07";
229 config_start_ftu <= '1';
230 if (config_started_ftu = '1') then
231 config_start_ftu <= '0';
232 state_central_proc <= CP_CONFIG_FTU_01;
233 end if;
234
235 when CP_CONFIG_FTU_01 =>
236 current_cc_state <= FTM_STATE_CFG;
237 cc_state_test <= X"08";
238 if (config_ready_ftu = '1') then
239 state_central_proc <= CP_CONFIG_SCALER;
240 end if;
241
242 when CP_CONFIG_SCALER =>
243 current_cc_state <= FTM_STATE_CFG;
244 cc_state_test <= X"09";
245 prescaling_FTU01_sig <= prescaling_FTU01;
246 --reset_period_sig <= '1';
247 state_central_proc <= CP_CONFIG_SCALER_01;
248
249 when CP_CONFIG_SCALER_01 =>
250 current_cc_state <= FTM_STATE_CFG;
251 cc_state_test <= X"0A";
252 --reset_period_sig <= '0';
253 if wait_cnt_sig < 5 then
254 wait_cnt_sig <= wait_cnt_sig + 1;
255 reset_scaler_sig <= '1';
256 state_central_proc <= CP_CONFIG_SCALER_01;
257 else
258 wait_cnt_sig <= 0;
259 reset_scaler_sig <= '0';
260 state_central_proc <= CP_CONFIG_TRIGGER;
261 end if;
262
263 when CP_CONFIG_TRIGGER =>
264 current_cc_state <= FTM_STATE_CFG;
265 cc_state_test <= X"0B";
266 --config trigger_manager block
267 config_trigger <= '1';
268 state_central_proc <= CP_CONFIG_TRIGGER_01;
269
270 when CP_CONFIG_TRIGGER_01 =>
271 current_cc_state <= FTM_STATE_CFG;
272 cc_state_test <= X"0C";
273 config_trigger <= '0';
274 if (config_trigger_done = '1') then
275 state_central_proc <= CP_IDLE;
276 end if;
277
278 when CP_IDLE =>
279 current_cc_state <= FTM_STATE_IDLE;
280 reset_timer <= '0';
281 cc_state_test <= X"0D";
282 stop_run_ack <= '1';
283 start_run_ack <= '0';
284 if (new_config = '1') then
285 config_started <= '1';
286 start_run_ack <= '1'; --remove this line???
287 state_central_proc <= CP_CONFIG_START;
288 elsif (ping_ftu_start = '1') then
289 ping_ftu_start_ftu <= '1';
290 if (ping_ftu_started_ftu = '1') then
291 ping_ftu_start_ftu <= '0';
292 ping_ftu_started <= '1';
293 ping_ftu_ready <= '0';
294 after_ping_state <= CP_IDLE;
295 state_central_proc <= CP_PING;
296 end if;
297 --elsif (scaler_counts_sig = scaler_period_sig) then
298 elsif (new_period_sig = '1') then
299 new_period_ack_sig <= '1';
300 --rates_ftu <= '1';
301 --state_central_proc <= CP_READ_RATES;
302 after_rates_state <= CP_IDLE;
303 state_central_proc <= CP_START_RATES;
304 elsif (start_run = '1') then
305 start_run_ack <= '1';
306 if (start_run_param = PAR_START_RUN) then
307 reset_timer <= '1';
308 state_central_proc <= CP_RUNNING;
309 end if;
310 elsif (crate_reset = '1') then
311 crate_reset_param_sig <= crate_reset_param;
312 crate_reset_ack <= '1';
313 state_central_proc <= CP_CRATE_RESET;
314 elsif (new_config_ftu = '1') then
315 new_config_ftu_ack <= '1'; -- just acknowledge and do nothing (complete config will follow anyway)
316 state_central_proc <= CP_CFG_SINGLE_FTU_ACK;
317 end if;
318
319 when CP_RUNNING =>
320 reset_timer <= '0';
321 current_cc_state <= FTM_STATE_RUN;
322 cc_state_test <= X"0E";
323 if (start_run = '0') then
324 start_run_ack <= '0';
325 stop_run_ack <= '0';
326 state_central_proc <= CP_RUNNING_01;
327 end if;
328
329 when CP_RUNNING_01 =>
330 current_cc_state <= FTM_STATE_RUN;
331 cc_state_test <= X"0F";
332 start_run_ack <= '1';
333 trigger_start <= '1';
334 trigger_stop <= '0';
335 enable_Id_sending <= '1';
336 if (new_config = '1') then
337 config_started <= '1';
338 state_central_proc <= CP_CONFIG_ACK;
339 elsif (ping_ftu_start = '1') then
340 ping_ftu_start_ftu <= '1';
341 if (ping_ftu_started_ftu = '1') then
342 ping_ftu_start_ftu <= '0';
343 ping_ftu_started <= '1';
344 ping_ftu_ready <= '0';
345 after_ping_state <= CP_RUNNING_01;
346 state_central_proc <= CP_PING;
347 end if;
348 elsif (new_period_sig = '1') then
349 new_period_ack_sig <= '1';
350 --rates_ftu <= '1';
351 --state_central_proc <= CP_READ_RATES;
352 after_rates_state <= CP_RUNNING_01;
353 state_central_proc <= CP_START_RATES;
354 elsif (stop_run = '1') then
355 stop_run_ack <= '1';
356 trigger_start <= '0';
357 trigger_stop <= '1';
358 enable_Id_sending <= '0';
359 state_central_proc <= CP_RUNNING_02;
360 elsif (crate_reset = '1') then
361 crate_reset_ack <= '1';
362 state_central_proc <= CP_CRATE_RESET_ACK;
363 elsif (new_config_ftu = '1') then
364 new_config_ftu_ack <= '1'; -- acknowledge and then tell ftu_control to do it
365 state_central_proc <= CP_CFG_SINGLE_FTU;
366 end if;
367
368 when CP_RUNNING_02 =>
369 current_cc_state <= FTM_STATE_RUN;
370 cc_state_test <= X"10";
371 if (stop_run = '0') then
372 stop_run_ack <= '0';
373 reset_timer <= '1';
374 state_central_proc <= CP_IDLE;
375 end if;
376
377 when CP_CONFIG_ACK =>
378 cc_state_test <= X"11";
379 if (config_started_ack = '1') then
380 config_started <= '0';
381 state_central_proc <= CP_RUNNING_01;
382 end if;
383
384 when CP_PING =>
385 cc_state_test <= X"12";
386 if (ping_ftu_ready_ftu = '1') then
387 if (ping_ftu_start = '0') then
388 ping_ftu_started <= '0';
389 ping_ftu_ready <= '1';
390 --state_central_proc <= CP_IDLE;
391 state_central_proc <= after_ping_state;
392 end if;
393 end if;
394
395 when CP_START_RATES =>
396 cc_state_test <= X"13";
397 new_period_ack_sig <= '0';
398 dd_block_start_ftu <= '1';
399 dd_block_ready_ftu <= '0';
400 if (dd_block_start_ack_ftu = '1') then
401 dd_block_start_ftu <= '0';
402 rates_ftu <= '1';
403 state_central_proc <= CP_READ_RATES;
404 end if;
405
406 when CP_READ_RATES =>
407 cc_state_test <= X"14";
408 new_period_ack_sig <= '0';
409 if (rates_started_ftu = '1') then
410 rates_ftu <= '0';
411 state_central_proc <= CP_READ_RATES_01;
412 end if;
413
414 when CP_READ_RATES_01 =>
415 cc_state_test <= X"15";
416 if (rates_ready_ftu = '1') then
417 dd_block_ready_ftu <= '1';
418 if ( (start_run = '1') or (stop_run = '1') ) then
419 state_central_proc <= after_rates_state;
420 else
421 state_central_proc <= CP_SEND_START;
422 end if;
423 end if;
424
425 when CP_SEND_START =>
426 cc_state_test <= X"16";
427 dd_send <= '1';
428 if (dd_send_ack = '1') then
429 dd_send <= '0';
430 state_central_proc <= CP_SEND_END;
431 end if;
432
433 when CP_SEND_END =>
434 cc_state_test <= X"17";
435 if (dd_send_ready = '1') then
436 --state_central_proc <= CP_IDLE;
437 state_central_proc <= after_rates_state;
438 end if;
439
440 when CP_CRATE_RESET_ACK =>
441 cc_state_test <= X"18";
442 if (crate_reset = '0') then
443 crate_reset_ack <= '0';
444 state_central_proc <= CP_RUNNING_01;
445 end if;
446
447 when CP_CRATE_RESET =>
448 cc_state_test <= X"19";
449 if (crate_reset = '0') then
450 crate_reset_ack <= '0';
451 state_central_proc <= CP_CRATE_RESET_01;
452 end if;
453
454 when CP_CRATE_RESET_01 =>
455 cc_state_test <= X"1A";
456 if (reset_cnt_sig < RESET_TIME) then
457 reset_cnt_sig <= reset_cnt_sig + 1;
458 if (crate_reset_param_sig = "0000000000000001") then
459 crate_res_0 <= '0';
460 elsif (crate_reset_param_sig = "0000000000000010") then
461 crate_res_1 <= '0';
462 elsif (crate_reset_param_sig = "0000000000000100") then
463 crate_res_2 <= '0';
464 elsif (crate_reset_param_sig = "0000000000001000") then
465 crate_res_3 <= '0';
466 end if;
467 else
468 reset_cnt_sig <= 0;
469 crate_res_0 <= '1';
470 crate_res_1 <= '1';
471 crate_res_2 <= '1';
472 crate_res_3 <= '1';
473 state_central_proc <= CP_IDLE;
474 end if;
475
476 when CP_CFG_SINGLE_FTU =>
477 cc_state_test <= X"1E";
478 if (new_config_ftu = '0') then
479 new_config_ftu_ack <= '0';
480 config_single_FTU <= '1';
481 state_central_proc <= CP_CFG_SINGLE_FTU_01;
482 end if;
483
484 when CP_CFG_SINGLE_FTU_01 =>
485 cc_state_test <= X"1F";
486 if (config_single_FTU_started = '1') then
487 config_single_FTU <= '0';
488 state_central_proc <= CP_CFG_SINGLE_FTU_02;
489 end if;
490
491 when CP_CFG_SINGLE_FTU_02 =>
492 cc_state_test <= X"20";
493 if (config_single_FTU_done = '1') then
494 state_central_proc <= CP_RUNNING_01;
495 end if;
496
497 when CP_CFG_SINGLE_FTU_ACK =>
498 cc_state_test <= X"21";
499 if (new_config_ftu = '0') then
500 new_config_ftu_ack <= '0';
501 state_central_proc <= CP_IDLE;
502 end if;
503
504 when others =>
505 cc_state_test <= X"1B";
506
507 end case;
508 end if;
509 end process central_proc;
510
511 scaler_process: process(reset_scaler_sig, clk_scaler)
512 begin
513 if (reset_scaler_sig = '1') then
514 scaler_counts_sig <= 0;
515 period_finished_sig <= '0';
516 elsif rising_edge(clk_scaler) then
517 if (scaler_counts_sig < (scaler_period_sig - 1)) then
518 scaler_counts_sig <= scaler_counts_sig + 1;
519 period_finished_sig <= '0';
520 else
521 period_finished_sig <= '1';
522 scaler_counts_sig <= 0;
523 end if;
524 end if;
525 end process scaler_process;
526
527-- process(reset_period_sig)
528-- begin
529-- if rising_edge(reset_period_sig) then
530-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
531-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
532-- else
533-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
534-- end if;
535-- end if;
536-- end process;
537
538 process(prescaling_FTU01_sig)
539 begin
540 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
541 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
542 else
543 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
544 end if;
545 end process;
546
547 detect_period_finished: process(clk)
548 begin
549 if rising_edge(clk) then
550 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
551 if(new_period_ack_sig = '1') then
552 new_period_sig <= '0';
553 else
554 if (new_period_sr_sig(1 downto 0) = "01") then
555 new_period_sig <= '1';
556 end if;
557 end if;
558 end if;
559 end process detect_period_finished;
560
561end Behavioral;
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