source: firmware/FTM/FTM_central_control.vhd@ 15497

Last change on this file since 15497 was 11654, checked in by weitzel, 14 years ago
two new status states introduced for FTM to indicate lock status of clock conditioner
File size: 21.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 cc_locked : in std_logic;
68 config_start_lp : out std_logic := '0';
69 config_started_lp : in std_logic;
70 config_ready_lp : in std_logic;
71 config_trigger : out std_logic := '0';
72 config_trigger_done : in std_logic;
73 dna_start : out std_logic := '0';
74 dna_ready : in std_logic;
75 crate_reset : IN std_logic;
76 crate_reset_ack : OUT std_logic := '0';
77 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
78 start_run : IN std_logic;
79 start_run_ack : OUT std_logic := '0';
80 stop_run : IN std_logic;
81 stop_run_ack : OUT std_logic := '0';
82 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
83 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
84 start_run_param : IN std_logic_vector (15 DOWNTO 0);
85 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
86 trigger_start : out std_logic := '0';
87 trigger_stop : out std_logic := '1';
88 enable_ID_sending : out std_logic := '0';
89 reset_timer : out std_logic := '0';
90 crate_res_0 : out std_logic := '1';
91 crate_res_1 : out std_logic := '1';
92 crate_res_2 : out std_logic := '1';
93 crate_res_3 : out std_logic := '1';
94 new_config_ftu : in std_logic; -- from ethernet_modul
95 new_config_ftu_ack : out std_logic := '0'; -- to ethernet_modul
96 config_single_FTU : out std_logic := '0'; -- to ftu_control
97 config_single_FTU_started : in std_logic; -- from ftu_control
98 config_single_FTU_done : in std_logic -- from ftu_control
99 );
100end FTM_central_control;
101
102architecture Behavioral of FTM_central_control is
103
104 signal reset_scaler_sig : std_logic := '0';
105 signal reset_period_sig : std_logic := '0';
106 signal scaler_counts_sig : integer := 0;
107 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
108 signal period_finished_sig : std_logic := '0';
109 signal wait_cnt_sig : integer range 0 to 10 := 0;
110 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
111 signal new_period_sig : std_logic := '0';
112 signal new_period_ack_sig : std_logic := '0';
113 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
114 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0;
115 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0) := (others => '0');
116
117 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
118 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
119 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
120 CP_CONFIG_CC, CP_CONFIG_CC_01,
121 CP_CONFIG_LP, CP_CONFIG_LP_01,
122 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
123 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
124 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
125 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
126 CP_SEND_START, CP_SEND_END,
127 CP_CRATE_RESET, CP_CRATE_RESET_01, CP_CRATE_RESET_ACK,
128 CP_CFG_SINGLE_FTU, CP_CFG_SINGLE_FTU_01, CP_CFG_SINGLE_FTU_02, CP_CFG_SINGLE_FTU_ACK);
129 signal state_central_proc : state_central_proc_type := CP_INIT;
130
131 signal after_rates_state : state_central_proc_type := CP_IDLE;
132 signal after_ping_state : state_central_proc_type := CP_IDLE;
133
134begin
135
136 --central_proc : process (clk, prescaling_FTU01)
137 central_proc : process (clk)
138 begin
139 if rising_edge (clk) then
140 case state_central_proc is
141
142 when CP_INIT => -- wait for DCMs to lock
143 current_cc_state <= X"FFFF";
144 cc_state_test <= X"01";
145 if (clk_ready = '1') then
146 state_central_proc <= CP_INIT_DNA;
147 end if;
148
149 when CP_INIT_DNA => -- get FPGA DNA
150 current_cc_state <= X"FFFF";
151 cc_state_test <= X"01";
152 if (dna_ready = '1') then
153 state_central_proc <= CP_INIT_TIMER;
154 dna_start <= '0';
155 reset_timer <= '1'; -- reset timer after power-up
156 else
157 dna_start <= '1';
158 state_central_proc <= CP_INIT_DNA;
159 end if;
160
161 when CP_INIT_TIMER =>
162 current_cc_state <= X"FFFF";
163 cc_state_test <= X"01";
164 reset_timer <= '0'; -- finish reset timer after power-up
165 state_central_proc <= CP_CONFIG;
166
167 when CP_CONFIG_START =>
168 current_cc_state <= FTM_STATE_CFG;
169 cc_state_test <= X"02";
170 if (config_started_ack = '1') then
171 config_started <= '0';
172 state_central_proc <= CP_CONFIG;
173 end if;
174
175 when CP_CONFIG =>
176 current_cc_state <= FTM_STATE_CFG;
177 cc_state_test <= X"03";
178 config_start_eth <= '1';
179 if (config_started_eth = '1') then
180 config_start_eth <= '0';
181 state_central_proc <= CP_CONFIG_01;
182 end if;
183
184 when CP_CONFIG_01 =>
185 current_cc_state <= FTM_STATE_CFG;
186 cc_state_test <= X"04";
187 if (config_ready_eth = '1') then
188 state_central_proc <= CP_CONFIG_CC;
189 --state_central_proc <= CP_CONFIG_SCALER;
190 --state_central_proc <= CP_IDLE;
191 --state_central_proc <= CP_CRATE_RESET;
192 end if;
193
194 when CP_CONFIG_CC =>
195 current_cc_state <= FTM_STATE_CFG;
196 cc_state_test <= X"05";
197 config_start_cc <= '1';
198 if (config_started_cc = '1') then
199 config_start_cc <= '0';
200 state_central_proc <= CP_CONFIG_CC_01;
201 end if;
202
203 when CP_CONFIG_CC_01 =>
204 current_cc_state <= FTM_STATE_CFG;
205 cc_state_test <= X"06";
206 if (config_ready_cc = '1') then
207 state_central_proc <= CP_CONFIG_LP;
208 --state_central_proc <= CP_CONFIG_FTU;
209 end if;
210
211 when CP_CONFIG_LP =>
212 current_cc_state <= FTM_STATE_CFG;
213 cc_state_test <= X"1C";
214 config_start_lp <= '1';
215 if (config_started_lp = '1') then
216 config_start_lp <= '0';
217 state_central_proc <= CP_CONFIG_LP_01;
218 end if;
219
220 when CP_CONFIG_LP_01 =>
221 current_cc_state <= FTM_STATE_CFG;
222 cc_state_test <= X"1D";
223 if (config_ready_lp = '1') then
224 state_central_proc <= CP_CONFIG_FTU;
225 end if;
226
227 when CP_CONFIG_FTU =>
228 current_cc_state <= FTM_STATE_CFG;
229 cc_state_test <= X"07";
230 config_start_ftu <= '1';
231 if (config_started_ftu = '1') then
232 config_start_ftu <= '0';
233 state_central_proc <= CP_CONFIG_FTU_01;
234 end if;
235
236 when CP_CONFIG_FTU_01 =>
237 current_cc_state <= FTM_STATE_CFG;
238 cc_state_test <= X"08";
239 if (config_ready_ftu = '1') then
240 state_central_proc <= CP_CONFIG_SCALER;
241 end if;
242
243 when CP_CONFIG_SCALER =>
244 current_cc_state <= FTM_STATE_CFG;
245 cc_state_test <= X"09";
246 prescaling_FTU01_sig <= prescaling_FTU01;
247 --reset_period_sig <= '1';
248 state_central_proc <= CP_CONFIG_SCALER_01;
249
250 when CP_CONFIG_SCALER_01 =>
251 current_cc_state <= FTM_STATE_CFG;
252 cc_state_test <= X"0A";
253 --reset_period_sig <= '0';
254 if wait_cnt_sig < 5 then
255 wait_cnt_sig <= wait_cnt_sig + 1;
256 reset_scaler_sig <= '1';
257 state_central_proc <= CP_CONFIG_SCALER_01;
258 else
259 wait_cnt_sig <= 0;
260 reset_scaler_sig <= '0';
261 state_central_proc <= CP_CONFIG_TRIGGER;
262 end if;
263
264 when CP_CONFIG_TRIGGER =>
265 current_cc_state <= FTM_STATE_CFG;
266 cc_state_test <= X"0B";
267 --config trigger_manager block
268 config_trigger <= '1';
269 state_central_proc <= CP_CONFIG_TRIGGER_01;
270
271 when CP_CONFIG_TRIGGER_01 =>
272 current_cc_state <= FTM_STATE_CFG;
273 cc_state_test <= X"0C";
274 config_trigger <= '0';
275 if (config_trigger_done = '1') then
276 state_central_proc <= CP_IDLE;
277 end if;
278
279 when CP_IDLE =>
280 if (cc_locked = '1') then
281 current_cc_state <= FTM_STATE_IDLE;
282 else
283 current_cc_state <= FTM_STATE_IDLE_NOT_LOCKED;
284 end if;
285 reset_timer <= '0';
286 cc_state_test <= X"0D";
287 stop_run_ack <= '1';
288 start_run_ack <= '0';
289 if (new_config = '1') then
290 config_started <= '1';
291 start_run_ack <= '1'; --remove this line???
292 state_central_proc <= CP_CONFIG_START;
293 elsif (ping_ftu_start = '1') then
294 ping_ftu_start_ftu <= '1';
295 if (ping_ftu_started_ftu = '1') then
296 ping_ftu_start_ftu <= '0';
297 ping_ftu_started <= '1';
298 ping_ftu_ready <= '0';
299 after_ping_state <= CP_IDLE;
300 state_central_proc <= CP_PING;
301 end if;
302 --elsif (scaler_counts_sig = scaler_period_sig) then
303 elsif (new_period_sig = '1') then
304 new_period_ack_sig <= '1';
305 --rates_ftu <= '1';
306 --state_central_proc <= CP_READ_RATES;
307 after_rates_state <= CP_IDLE;
308 state_central_proc <= CP_START_RATES;
309 elsif (start_run = '1') then
310 start_run_ack <= '1';
311 if (start_run_param = PAR_START_RUN) then
312 reset_timer <= '1';
313 state_central_proc <= CP_RUNNING;
314 end if;
315 elsif (crate_reset = '1') then
316 crate_reset_param_sig <= crate_reset_param;
317 crate_reset_ack <= '1';
318 state_central_proc <= CP_CRATE_RESET;
319 elsif (new_config_ftu = '1') then
320 new_config_ftu_ack <= '1'; -- just acknowledge and do nothing (complete config will follow anyway)
321 state_central_proc <= CP_CFG_SINGLE_FTU_ACK;
322 end if;
323
324 when CP_RUNNING =>
325 reset_timer <= '0';
326 if (cc_locked = '1') then
327 current_cc_state <= FTM_STATE_RUN;
328 else
329 current_cc_state <= FTM_STATE_RUN_NOT_LOCKED;
330 end if;
331 cc_state_test <= X"0E";
332 if (start_run = '0') then
333 start_run_ack <= '0';
334 stop_run_ack <= '0';
335 state_central_proc <= CP_RUNNING_01;
336 end if;
337
338 when CP_RUNNING_01 =>
339 if (cc_locked = '1') then
340 current_cc_state <= FTM_STATE_RUN;
341 else
342 current_cc_state <= FTM_STATE_RUN_NOT_LOCKED;
343 end if;
344 cc_state_test <= X"0F";
345 start_run_ack <= '1';
346 trigger_start <= '1';
347 trigger_stop <= '0';
348 enable_Id_sending <= '1';
349 if (new_config = '1') then
350 config_started <= '1';
351 state_central_proc <= CP_CONFIG_ACK;
352 elsif (ping_ftu_start = '1') then
353 ping_ftu_start_ftu <= '1';
354 if (ping_ftu_started_ftu = '1') then
355 ping_ftu_start_ftu <= '0';
356 ping_ftu_started <= '1';
357 ping_ftu_ready <= '0';
358 after_ping_state <= CP_RUNNING_01;
359 state_central_proc <= CP_PING;
360 end if;
361 elsif (new_period_sig = '1') then
362 new_period_ack_sig <= '1';
363 --rates_ftu <= '1';
364 --state_central_proc <= CP_READ_RATES;
365 after_rates_state <= CP_RUNNING_01;
366 state_central_proc <= CP_START_RATES;
367 elsif (stop_run = '1') then
368 stop_run_ack <= '1';
369 trigger_start <= '0';
370 trigger_stop <= '1';
371 enable_Id_sending <= '0';
372 state_central_proc <= CP_RUNNING_02;
373 elsif (crate_reset = '1') then
374 crate_reset_ack <= '1';
375 state_central_proc <= CP_CRATE_RESET_ACK;
376 elsif (new_config_ftu = '1') then
377 new_config_ftu_ack <= '1'; -- acknowledge and then tell ftu_control to do it
378 state_central_proc <= CP_CFG_SINGLE_FTU;
379 end if;
380
381 when CP_RUNNING_02 =>
382 if (cc_locked = '1') then
383 current_cc_state <= FTM_STATE_RUN;
384 else
385 current_cc_state <= FTM_STATE_RUN_NOT_LOCKED;
386 end if;
387 cc_state_test <= X"10";
388 if (stop_run = '0') then
389 stop_run_ack <= '0';
390 reset_timer <= '1';
391 state_central_proc <= CP_IDLE;
392 end if;
393
394 when CP_CONFIG_ACK =>
395 cc_state_test <= X"11";
396 if (config_started_ack = '1') then
397 config_started <= '0';
398 state_central_proc <= CP_RUNNING_01;
399 end if;
400
401 when CP_PING =>
402 cc_state_test <= X"12";
403 if (ping_ftu_ready_ftu = '1') then
404 if (ping_ftu_start = '0') then
405 ping_ftu_started <= '0';
406 ping_ftu_ready <= '1';
407 --state_central_proc <= CP_IDLE;
408 state_central_proc <= after_ping_state;
409 end if;
410 end if;
411
412 when CP_START_RATES =>
413 cc_state_test <= X"13";
414 new_period_ack_sig <= '0';
415 dd_block_start_ftu <= '1';
416 dd_block_ready_ftu <= '0';
417 if (dd_block_start_ack_ftu = '1') then
418 dd_block_start_ftu <= '0';
419 rates_ftu <= '1';
420 state_central_proc <= CP_READ_RATES;
421 end if;
422
423 when CP_READ_RATES =>
424 cc_state_test <= X"14";
425 new_period_ack_sig <= '0';
426 if (rates_started_ftu = '1') then
427 rates_ftu <= '0';
428 state_central_proc <= CP_READ_RATES_01;
429 end if;
430
431 when CP_READ_RATES_01 =>
432 cc_state_test <= X"15";
433 if (rates_ready_ftu = '1') then
434 dd_block_ready_ftu <= '1';
435 if ( (start_run = '1') or (stop_run = '1') ) then
436 state_central_proc <= after_rates_state;
437 else
438 state_central_proc <= CP_SEND_START;
439 end if;
440 end if;
441
442 when CP_SEND_START =>
443 cc_state_test <= X"16";
444 dd_send <= '1';
445 if (dd_send_ack = '1') then
446 dd_send <= '0';
447 state_central_proc <= CP_SEND_END;
448 end if;
449
450 when CP_SEND_END =>
451 cc_state_test <= X"17";
452 if (dd_send_ready = '1') then
453 --state_central_proc <= CP_IDLE;
454 state_central_proc <= after_rates_state;
455 end if;
456
457 when CP_CRATE_RESET_ACK =>
458 cc_state_test <= X"18";
459 if (crate_reset = '0') then
460 crate_reset_ack <= '0';
461 state_central_proc <= CP_RUNNING_01;
462 end if;
463
464 when CP_CRATE_RESET =>
465 cc_state_test <= X"19";
466 if (crate_reset = '0') then
467 crate_reset_ack <= '0';
468 state_central_proc <= CP_CRATE_RESET_01;
469 end if;
470
471 when CP_CRATE_RESET_01 =>
472 cc_state_test <= X"1A";
473 if (reset_cnt_sig < RESET_TIME) then
474 reset_cnt_sig <= reset_cnt_sig + 1;
475 if (crate_reset_param_sig = "0000000000000001") then
476 crate_res_0 <= '0';
477 elsif (crate_reset_param_sig = "0000000000000010") then
478 crate_res_1 <= '0';
479 elsif (crate_reset_param_sig = "0000000000000100") then
480 crate_res_2 <= '0';
481 elsif (crate_reset_param_sig = "0000000000001000") then
482 crate_res_3 <= '0';
483 end if;
484 else
485 reset_cnt_sig <= 0;
486 crate_res_0 <= '1';
487 crate_res_1 <= '1';
488 crate_res_2 <= '1';
489 crate_res_3 <= '1';
490 state_central_proc <= CP_IDLE;
491 end if;
492
493 when CP_CFG_SINGLE_FTU =>
494 cc_state_test <= X"1E";
495 if (new_config_ftu = '0') then
496 new_config_ftu_ack <= '0';
497 config_single_FTU <= '1';
498 state_central_proc <= CP_CFG_SINGLE_FTU_01;
499 end if;
500
501 when CP_CFG_SINGLE_FTU_01 =>
502 cc_state_test <= X"1F";
503 if (config_single_FTU_started = '1') then
504 config_single_FTU <= '0';
505 state_central_proc <= CP_CFG_SINGLE_FTU_02;
506 end if;
507
508 when CP_CFG_SINGLE_FTU_02 =>
509 cc_state_test <= X"20";
510 if (config_single_FTU_done = '1') then
511 state_central_proc <= CP_RUNNING_01;
512 end if;
513
514 when CP_CFG_SINGLE_FTU_ACK =>
515 cc_state_test <= X"21";
516 if (new_config_ftu = '0') then
517 new_config_ftu_ack <= '0';
518 state_central_proc <= CP_IDLE;
519 end if;
520
521 when others =>
522 cc_state_test <= X"1B";
523
524 end case;
525 end if;
526 end process central_proc;
527
528 scaler_process: process(reset_scaler_sig, clk_scaler)
529 begin
530 if (reset_scaler_sig = '1') then
531 scaler_counts_sig <= 0;
532 period_finished_sig <= '0';
533 elsif rising_edge(clk_scaler) then
534 if (scaler_counts_sig < (scaler_period_sig - 1)) then
535 scaler_counts_sig <= scaler_counts_sig + 1;
536 period_finished_sig <= '0';
537 else
538 period_finished_sig <= '1';
539 scaler_counts_sig <= 0;
540 end if;
541 end if;
542 end process scaler_process;
543
544-- process(reset_period_sig)
545-- begin
546-- if rising_edge(reset_period_sig) then
547-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
548-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
549-- else
550-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
551-- end if;
552-- end if;
553-- end process;
554
555 process(prescaling_FTU01_sig)
556 begin
557 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
558 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
559 else
560 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
561 end if;
562 end process;
563
564 detect_period_finished: process(clk)
565 begin
566 if rising_edge(clk) then
567 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
568 if(new_period_ack_sig = '1') then
569 new_period_sig <= '0';
570 else
571 if (new_period_sr_sig(1 downto 0) = "01") then
572 new_period_sig <= '1';
573 end if;
574 end if;
575 end if;
576 end process detect_period_finished;
577
578end Behavioral;
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