source: firmware/FTM/FTM_central_control.vhd@ 10328

Last change on this file since 10328 was 10328, checked in by weitzel, 10 years ago
changes in FTM firmware to debug rates readout, clock conditioner added
File size: 9.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_scaler : IN std_logic;
38 new_config : IN std_logic;
39 config_started : OUT std_logic := '0';
40 config_started_ack : IN std_logic;
41 config_start_eth : OUT std_logic := '0';
42 config_started_eth : IN std_logic;
43 config_ready_eth : IN std_logic;
44 config_start_ftu : OUT std_logic := '0';
45 config_started_ftu : IN std_logic ;
46 config_ready_ftu : IN std_logic ;
47 ping_ftu_start : IN std_logic;
48 ping_ftu_started : OUT std_logic := '0';
49 ping_ftu_ready : OUT std_logic := '0';
50 ping_ftu_start_ftu : OUT std_logic := '0';
51 ping_ftu_started_ftu : IN std_logic;
52 ping_ftu_ready_ftu : IN std_logic;
53 rates_ftu : OUT std_logic := '0';
54 rates_started_ftu : IN std_logic;
55 rates_ready_ftu : IN std_logic;
56 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
57 dd_send : OUT std_logic := '0';
58 dd_send_ack : IN std_logic;
59 dd_send_ready : IN std_logic;
60 config_start_cc : out std_logic := '0';
61 config_started_cc : in std_logic;
62 config_ready_cc : in std_logic
63 );
64end FTM_central_control;
65
66architecture Behavioral of FTM_central_control is
67
68 signal reset_scaler_sig : std_logic := '0';
69 signal reset_period_sig : std_logic := '0';
70 signal scaler_counts_sig : integer := 0;
71 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
72 signal period_finished_sig : std_logic := '0';
73 signal wait_cnt_sig : integer range 0 to 10 := 0;
74 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
75 signal new_period_sig : std_logic := '0';
76 signal new_period_ack_sig : std_logic := '0';
77 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
78
79 type state_central_proc_type is (CP_INIT,
80 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
81 CP_CONFIG_CC, CP_CONFIG_CC_01,
82 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
83 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
84 CP_IDLE, CP_PING, CP_READ_RATES, CP_READ_RATES_01,
85 CP_SEND_START, CP_SEND_END);
86 signal state_central_proc : state_central_proc_type := CP_INIT;
87
88begin
89
90 central_proc : process (clk, prescaling_FTU01)
91 begin
92 if rising_edge (clk) then
93 case state_central_proc is
94
95 when CP_INIT =>
96 state_central_proc <= CP_CONFIG;
97
98 when CP_CONFIG_START =>
99 if (config_started_ack = '1') then
100 config_started <= '0';
101 state_central_proc <= CP_CONFIG;
102 end if;
103
104 when CP_CONFIG =>
105 config_start_eth <= '1';
106 if (config_started_eth = '1') then
107 config_start_eth <= '0';
108 state_central_proc <= CP_CONFIG_01;
109 end if;
110
111 when CP_CONFIG_01 =>
112 if (config_ready_eth = '1') then
113 state_central_proc <= CP_CONFIG_CC;
114 --state_central_proc <= CP_CONFIG_SCALER;
115 --state_central_proc <= CP_IDLE;
116 end if;
117
118 when CP_CONFIG_CC =>
119 config_start_cc <= '1';
120 if (config_started_cc = '1') then
121 config_start_cc <= '0';
122 state_central_proc <= CP_CONFIG_CC_01;
123 end if;
124
125 when CP_CONFIG_CC_01 =>
126 if (config_ready_cc = '1') then
127 state_central_proc <= CP_CONFIG_FTU;
128 end if;
129
130 when CP_CONFIG_FTU =>
131 config_start_ftu <= '1';
132 if (config_started_ftu = '1') then
133 config_start_ftu <= '0';
134 state_central_proc <= CP_CONFIG_FTU_01;
135 end if;
136
137 when CP_CONFIG_FTU_01 =>
138 if (config_ready_ftu = '1') then
139 state_central_proc <= CP_CONFIG_SCALER;
140 end if;
141
142 when CP_CONFIG_SCALER =>
143 prescaling_FTU01_sig <= prescaling_FTU01;
144 --reset_period_sig <= '1';
145 state_central_proc <= CP_CONFIG_SCALER_01;
146
147 when CP_CONFIG_SCALER_01 =>
148 --reset_period_sig <= '0';
149 if wait_cnt_sig < 5 then
150 wait_cnt_sig <= wait_cnt_sig + 1;
151 reset_scaler_sig <= '1';
152 state_central_proc <= CP_CONFIG_SCALER_01;
153 else
154 wait_cnt_sig <= 0;
155 reset_scaler_sig <= '0';
156 state_central_proc <= CP_IDLE;
157 end if;
158
159 when CP_IDLE =>
160 if (new_config = '1') then
161 config_started <= '1';
162 state_central_proc <= CP_CONFIG_START;
163 elsif (ping_ftu_start = '1') then
164 ping_ftu_start_ftu <= '1';
165 if (ping_ftu_started_ftu = '1') then
166 ping_ftu_start_ftu <= '0';
167 ping_ftu_started <= '1';
168 ping_ftu_ready <= '0';
169 state_central_proc <= CP_PING;
170 end if;
171 --elsif (scaler_counts_sig = scaler_period_sig) then
172 elsif (new_period_sig = '1') then
173 new_period_ack_sig <= '1';
174 rates_ftu <= '1';
175 state_central_proc <= CP_READ_RATES;
176 end if;
177
178 when CP_PING =>
179 if (ping_ftu_ready_ftu = '1') then
180 if (ping_ftu_start = '0') then
181 ping_ftu_started <= '0';
182 ping_ftu_ready <= '1';
183 state_central_proc <= CP_IDLE;
184 end if;
185 end if;
186
187 when CP_READ_RATES =>
188 new_period_ack_sig <= '0';
189 if (rates_started_ftu = '1') then
190 rates_ftu <= '0';
191 state_central_proc <= CP_READ_RATES_01;
192 end if;
193
194 when CP_READ_RATES_01 =>
195 if (rates_ready_ftu = '1') then
196 state_central_proc <= CP_SEND_START;
197 end if;
198
199 when CP_SEND_START =>
200 dd_send <= '1';
201 if (dd_send_ack = '1') then
202 dd_send <= '0';
203 state_central_proc <= CP_SEND_END;
204 end if;
205
206 when CP_SEND_END =>
207 if (dd_send_ready = '1') then
208 state_central_proc <= CP_IDLE;
209 end if;
210
211 end case;
212 end if;
213 end process central_proc;
214
215 scaler_process: process(reset_scaler_sig, clk_scaler)
216 begin
217 if (reset_scaler_sig = '1') then
218 scaler_counts_sig <= 0;
219 period_finished_sig <= '0';
220 elsif rising_edge(clk_scaler) then
221 if (scaler_counts_sig < scaler_period_sig) then
222 scaler_counts_sig <= scaler_counts_sig + 1;
223 period_finished_sig <= '0';
224 else
225 period_finished_sig <= '1';
226 scaler_counts_sig <= 0;
227 end if;
228 end if;
229 end process scaler_process;
230
231-- process(reset_period_sig)
232-- begin
233-- if rising_edge(reset_period_sig) then
234-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
235-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
236-- else
237-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
238-- end if;
239-- end if;
240-- end process;
241
242 process(prescaling_FTU01_sig)
243 begin
244 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
245 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
246 else
247 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
248 end if;
249 end process;
250
251 detect_period_finished: process(clk)
252 begin
253 if rising_edge(clk) then
254 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
255 if(new_period_ack_sig = '1') then
256 new_period_sig <= '0';
257 else
258 if (new_period_sr_sig(1 downto 0) = "01") then
259 new_period_sig <= '1';
260 end if;
261 end if;
262 end if;
263 end process detect_period_finished;
264
265end Behavioral;
Note: See TracBrowser for help on using the repository browser.