1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: ETH Zurich, Institute for Particle Physics |
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3 | -- Engineer: Q. Weitzel |
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4 | -- |
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5 | -- Create Date: 15:56:13 02/28/2011 |
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6 | -- Design Name: |
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7 | -- Module Name: FTM_central_control - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: Central FSM for FTM firmware |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | library IEEE; |
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21 | use IEEE.STD_LOGIC_1164.ALL; |
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22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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24 | |
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25 | library ftm_definitions; |
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26 | USE ftm_definitions.ftm_array_types.all; |
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27 | USE ftm_definitions.ftm_constants.all; |
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28 | |
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29 | ---- Uncomment the following library declaration if instantiating |
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30 | ---- any Xilinx primitives in this code. |
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31 | --library UNISIM; |
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32 | --use UNISIM.VComponents.all; |
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33 | |
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34 | entity FTM_central_control is |
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35 | port( |
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36 | clk : IN std_logic; |
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37 | clk_ready : in std_logic; |
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38 | clk_scaler : IN std_logic; |
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39 | new_config : IN std_logic; |
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40 | config_started : OUT std_logic := '0'; |
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41 | config_started_ack : IN std_logic; |
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42 | config_start_eth : OUT std_logic := '0'; |
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43 | config_started_eth : IN std_logic; |
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44 | config_ready_eth : IN std_logic; |
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45 | config_start_ftu : OUT std_logic := '0'; |
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46 | config_started_ftu : IN std_logic ; |
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47 | config_ready_ftu : IN std_logic ; |
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48 | ping_ftu_start : IN std_logic; |
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49 | ping_ftu_started : OUT std_logic := '0'; |
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50 | ping_ftu_ready : OUT std_logic := '0'; |
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51 | ping_ftu_start_ftu : OUT std_logic := '0'; |
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52 | ping_ftu_started_ftu : IN std_logic; |
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53 | ping_ftu_ready_ftu : IN std_logic; |
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54 | rates_ftu : OUT std_logic := '0'; |
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55 | rates_started_ftu : IN std_logic; |
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56 | rates_ready_ftu : IN std_logic; |
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57 | prescaling_FTU01 : IN std_logic_vector(7 downto 0); |
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58 | dd_send : OUT std_logic := '0'; |
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59 | dd_send_ack : IN std_logic; |
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60 | dd_send_ready : IN std_logic; |
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61 | dd_block_ready_ftu : out std_logic := '0'; |
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62 | dd_block_start_ack_ftu : in std_logic; |
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63 | dd_block_start_ftu : out std_logic := '0'; |
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64 | config_start_cc : out std_logic := '0'; |
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65 | config_started_cc : in std_logic; |
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66 | config_ready_cc : in std_logic; |
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67 | config_trigger : out std_logic := '0'; |
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68 | config_trigger_done : in std_logic; |
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69 | dna_start : out std_logic := '0'; |
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70 | dna_ready : in std_logic; |
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71 | crate_reset : IN std_logic; |
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72 | crate_reset_ack : OUT std_logic := '1'; |
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73 | crate_reset_param : IN std_logic_vector (15 DOWNTO 0); |
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74 | start_run : IN std_logic; |
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75 | start_run_ack : OUT std_logic := '0'; |
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76 | stop_run : IN std_logic; |
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77 | stop_run_ack : OUT std_logic := '0'; |
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78 | current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF"; |
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79 | cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF"; |
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80 | start_run_param : IN std_logic_vector (15 DOWNTO 0); |
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81 | start_run_num_events : IN std_logic_vector (31 DOWNTO 0); |
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82 | trigger_start : out std_logic := '0'; |
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83 | trigger_stop : out std_logic := '1'; |
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84 | enable_ID_sending : out std_logic := '0' |
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85 | ); |
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86 | end FTM_central_control; |
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87 | |
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88 | architecture Behavioral of FTM_central_control is |
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89 | |
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90 | signal reset_scaler_sig : std_logic := '0'; |
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91 | signal reset_period_sig : std_logic := '0'; |
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92 | signal scaler_counts_sig : integer := 0; |
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93 | signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); |
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94 | signal period_finished_sig : std_logic := '0'; |
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95 | signal wait_cnt_sig : integer range 0 to 10 := 0; |
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96 | signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0'); |
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97 | signal new_period_sig : std_logic := '0'; |
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98 | signal new_period_ack_sig : std_logic := '0'; |
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99 | signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; |
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100 | |
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101 | type state_central_proc_type is (CP_INIT, CP_INIT_DNA, |
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102 | CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK, |
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103 | CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, |
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104 | CP_CONFIG_CC, CP_CONFIG_CC_01, |
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105 | CP_CONFIG_FTU, CP_CONFIG_FTU_01, |
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106 | CP_CONFIG_SCALER, CP_CONFIG_SCALER_01, |
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107 | CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01, |
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108 | CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01, |
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109 | CP_SEND_START, CP_SEND_END); |
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110 | signal state_central_proc : state_central_proc_type := CP_INIT; |
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111 | |
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112 | signal after_rates_state : state_central_proc_type := CP_IDLE; |
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113 | signal after_ping_state : state_central_proc_type := CP_IDLE; |
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114 | |
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115 | begin |
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116 | |
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117 | --central_proc : process (clk, prescaling_FTU01) |
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118 | central_proc : process (clk) |
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119 | begin |
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120 | if rising_edge (clk) then |
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121 | case state_central_proc is |
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122 | |
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123 | when CP_INIT => -- wait for DCMs to lock |
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124 | current_cc_state <= X"FFFF"; |
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125 | --cc_state_test <= X"00"; |
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126 | cc_state_test <= X"19"; |
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127 | if (clk_ready = '1') then |
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128 | state_central_proc <= CP_INIT_DNA; |
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129 | end if; |
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130 | |
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131 | when CP_INIT_DNA => -- get FPGA DNA |
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132 | current_cc_state <= X"FFFF"; |
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133 | cc_state_test <= X"01"; |
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134 | if (dna_ready = '1') then |
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135 | state_central_proc <= CP_CONFIG; |
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136 | dna_start <= '0'; |
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137 | else |
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138 | dna_start <= '1'; |
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139 | state_central_proc <= CP_INIT_DNA; |
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140 | end if; |
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141 | |
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142 | when CP_CONFIG_START => |
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143 | current_cc_state <= FTM_STATE_CFG; |
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144 | cc_state_test <= X"02"; |
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145 | if (config_started_ack = '1') then |
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146 | config_started <= '0'; |
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147 | state_central_proc <= CP_CONFIG; |
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148 | end if; |
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149 | |
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150 | when CP_CONFIG => |
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151 | current_cc_state <= FTM_STATE_CFG; |
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152 | cc_state_test <= X"03"; |
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153 | config_start_eth <= '1'; |
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154 | if (config_started_eth = '1') then |
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155 | config_start_eth <= '0'; |
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156 | state_central_proc <= CP_CONFIG_01; |
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157 | end if; |
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158 | |
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159 | when CP_CONFIG_01 => |
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160 | current_cc_state <= FTM_STATE_CFG; |
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161 | cc_state_test <= X"04"; |
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162 | if (config_ready_eth = '1') then |
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163 | state_central_proc <= CP_CONFIG_CC; |
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164 | --state_central_proc <= CP_CONFIG_SCALER; |
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165 | --state_central_proc <= CP_IDLE; |
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166 | end if; |
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167 | |
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168 | when CP_CONFIG_CC => |
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169 | current_cc_state <= FTM_STATE_CFG; |
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170 | cc_state_test <= X"05"; |
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171 | config_start_cc <= '1'; |
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172 | if (config_started_cc = '1') then |
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173 | config_start_cc <= '0'; |
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174 | state_central_proc <= CP_CONFIG_CC_01; |
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175 | end if; |
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176 | |
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177 | when CP_CONFIG_CC_01 => |
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178 | current_cc_state <= FTM_STATE_CFG; |
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179 | cc_state_test <= X"06"; |
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180 | if (config_ready_cc = '1') then |
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181 | state_central_proc <= CP_CONFIG_FTU; |
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182 | end if; |
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183 | |
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184 | when CP_CONFIG_FTU => |
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185 | current_cc_state <= FTM_STATE_CFG; |
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186 | cc_state_test <= X"07"; |
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187 | config_start_ftu <= '1'; |
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188 | if (config_started_ftu = '1') then |
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189 | config_start_ftu <= '0'; |
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190 | state_central_proc <= CP_CONFIG_FTU_01; |
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191 | end if; |
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192 | |
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193 | when CP_CONFIG_FTU_01 => |
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194 | current_cc_state <= FTM_STATE_CFG; |
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195 | cc_state_test <= X"08"; |
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196 | if (config_ready_ftu = '1') then |
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197 | state_central_proc <= CP_CONFIG_SCALER; |
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198 | end if; |
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199 | |
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200 | when CP_CONFIG_SCALER => |
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201 | current_cc_state <= FTM_STATE_CFG; |
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202 | cc_state_test <= X"09"; |
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203 | prescaling_FTU01_sig <= prescaling_FTU01; |
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204 | --reset_period_sig <= '1'; |
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205 | state_central_proc <= CP_CONFIG_SCALER_01; |
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206 | |
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207 | when CP_CONFIG_SCALER_01 => |
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208 | current_cc_state <= FTM_STATE_CFG; |
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209 | cc_state_test <= X"0A"; |
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210 | --reset_period_sig <= '0'; |
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211 | if wait_cnt_sig < 5 then |
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212 | wait_cnt_sig <= wait_cnt_sig + 1; |
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213 | reset_scaler_sig <= '1'; |
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214 | state_central_proc <= CP_CONFIG_SCALER_01; |
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215 | else |
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216 | wait_cnt_sig <= 0; |
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217 | reset_scaler_sig <= '0'; |
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218 | state_central_proc <= CP_CONFIG_TRIGGER; |
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219 | end if; |
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220 | |
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221 | when CP_CONFIG_TRIGGER => |
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222 | current_cc_state <= FTM_STATE_CFG; |
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223 | cc_state_test <= X"0B"; |
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224 | --config trigger_manager block |
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225 | config_trigger <= '1'; |
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226 | state_central_proc <= CP_CONFIG_TRIGGER_01; |
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227 | |
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228 | when CP_CONFIG_TRIGGER_01 => |
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229 | current_cc_state <= FTM_STATE_CFG; |
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230 | cc_state_test <= X"0C"; |
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231 | config_trigger <= '0'; |
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232 | if (config_trigger_done = '1') then |
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233 | state_central_proc <= CP_IDLE; |
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234 | end if; |
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235 | |
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236 | when CP_IDLE => |
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237 | current_cc_state <= FTM_STATE_IDLE; |
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238 | cc_state_test <= X"0D"; |
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239 | stop_run_ack <= '1'; |
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240 | start_run_ack <= '0'; |
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241 | if (new_config = '1') then |
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242 | config_started <= '1'; |
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243 | start_run_ack <= '1'; |
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244 | state_central_proc <= CP_CONFIG_START; |
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245 | elsif (ping_ftu_start = '1') then |
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246 | ping_ftu_start_ftu <= '1'; |
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247 | if (ping_ftu_started_ftu = '1') then |
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248 | ping_ftu_start_ftu <= '0'; |
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249 | ping_ftu_started <= '1'; |
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250 | ping_ftu_ready <= '0'; |
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251 | after_ping_state <= CP_IDLE; |
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252 | state_central_proc <= CP_PING; |
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253 | end if; |
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254 | --elsif (scaler_counts_sig = scaler_period_sig) then |
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255 | elsif (new_period_sig = '1') then |
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256 | new_period_ack_sig <= '1'; |
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257 | --rates_ftu <= '1'; |
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258 | --state_central_proc <= CP_READ_RATES; |
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259 | after_rates_state <= CP_IDLE; |
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260 | state_central_proc <= CP_START_RATES; |
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261 | elsif (start_run = '1') then |
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262 | start_run_ack <= '1'; |
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263 | if (start_run_param = PAR_START_RUN) then |
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264 | state_central_proc <= CP_RUNNING; |
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265 | end if; |
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266 | end if; |
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267 | |
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268 | when CP_RUNNING => |
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269 | current_cc_state <= FTM_STATE_RUN; |
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270 | cc_state_test <= X"0E"; |
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271 | if (start_run = '0') then |
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272 | start_run_ack <= '0'; |
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273 | stop_run_ack <= '0'; |
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274 | state_central_proc <= CP_RUNNING_01; |
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275 | end if; |
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276 | |
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277 | when CP_RUNNING_01 => |
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278 | current_cc_state <= FTM_STATE_RUN; |
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279 | cc_state_test <= X"0F"; |
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280 | start_run_ack <= '1'; |
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281 | trigger_start <= '1'; |
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282 | trigger_stop <= '0'; |
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283 | enable_Id_sending <= '1'; |
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284 | if (new_config = '1') then |
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285 | config_started <= '1'; |
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286 | state_central_proc <= CP_CONFIG_ACK; |
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287 | elsif (ping_ftu_start = '1') then |
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288 | ping_ftu_start_ftu <= '1'; |
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289 | if (ping_ftu_started_ftu = '1') then |
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290 | ping_ftu_start_ftu <= '0'; |
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291 | ping_ftu_started <= '1'; |
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292 | ping_ftu_ready <= '0'; |
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293 | after_ping_state <= CP_RUNNING_01; |
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294 | state_central_proc <= CP_PING; |
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295 | end if; |
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296 | elsif (new_period_sig = '1') then |
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297 | new_period_ack_sig <= '1'; |
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298 | --rates_ftu <= '1'; |
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299 | --state_central_proc <= CP_READ_RATES; |
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300 | after_rates_state <= CP_RUNNING_01; |
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301 | state_central_proc <= CP_START_RATES; |
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302 | elsif (stop_run = '1') then |
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303 | stop_run_ack <= '1'; |
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304 | trigger_start <= '0'; |
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305 | trigger_stop <= '1'; |
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306 | enable_Id_sending <= '0'; |
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307 | state_central_proc <= CP_RUNNING_02; |
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308 | end if; |
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309 | |
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310 | when CP_RUNNING_02 => |
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311 | current_cc_state <= FTM_STATE_RUN; |
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312 | cc_state_test <= X"10"; |
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313 | if (stop_run = '0') then |
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314 | stop_run_ack <= '0'; |
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315 | state_central_proc <= CP_IDLE; |
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316 | end if; |
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317 | |
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318 | when CP_CONFIG_ACK => |
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319 | current_cc_state <= FTM_STATE_CFG; |
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320 | cc_state_test <= X"11"; |
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321 | if (config_started_ack = '1') then |
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322 | config_started <= '0'; |
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323 | state_central_proc <= CP_RUNNING_01; |
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324 | end if; |
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325 | |
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326 | when CP_PING => |
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327 | cc_state_test <= X"12"; |
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328 | if (ping_ftu_ready_ftu = '1') then |
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329 | if (ping_ftu_start = '0') then |
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330 | ping_ftu_started <= '0'; |
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331 | ping_ftu_ready <= '1'; |
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332 | --state_central_proc <= CP_IDLE; |
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333 | state_central_proc <= after_ping_state; |
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334 | end if; |
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335 | end if; |
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336 | |
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337 | when CP_START_RATES => |
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338 | cc_state_test <= X"13"; |
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339 | new_period_ack_sig <= '0'; |
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340 | dd_block_start_ftu <= '1'; |
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341 | dd_block_ready_ftu <= '0'; |
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342 | if (dd_block_start_ack_ftu = '1') then |
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343 | dd_block_start_ftu <= '0'; |
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344 | rates_ftu <= '1'; |
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345 | state_central_proc <= CP_READ_RATES; |
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346 | end if; |
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347 | |
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348 | when CP_READ_RATES => |
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349 | cc_state_test <= X"14"; |
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350 | new_period_ack_sig <= '0'; |
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351 | if (rates_started_ftu = '1') then |
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352 | rates_ftu <= '0'; |
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353 | state_central_proc <= CP_READ_RATES_01; |
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354 | end if; |
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355 | |
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356 | when CP_READ_RATES_01 => |
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357 | cc_state_test <= X"15"; |
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358 | if (rates_ready_ftu = '1') then |
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359 | dd_block_ready_ftu <= '1'; |
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360 | if ( (start_run = '1') or (stop_run = '1') ) then |
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361 | state_central_proc <= after_rates_state; |
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362 | else |
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363 | state_central_proc <= CP_SEND_START; |
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364 | end if; |
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365 | end if; |
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366 | |
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367 | when CP_SEND_START => |
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368 | cc_state_test <= X"16"; |
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369 | dd_send <= '1'; |
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370 | if (dd_send_ack = '1') then |
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371 | dd_send <= '0'; |
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372 | state_central_proc <= CP_SEND_END; |
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373 | end if; |
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374 | |
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375 | when CP_SEND_END => |
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376 | cc_state_test <= X"17"; |
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377 | if (dd_send_ready = '1') then |
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378 | --state_central_proc <= CP_IDLE; |
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379 | state_central_proc <= after_rates_state; |
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380 | end if; |
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381 | |
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382 | when others => |
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383 | cc_state_test <= X"18"; |
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384 | |
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385 | end case; |
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386 | end if; |
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387 | end process central_proc; |
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388 | |
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389 | scaler_process: process(reset_scaler_sig, clk_scaler) |
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390 | begin |
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391 | if (reset_scaler_sig = '1') then |
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392 | scaler_counts_sig <= 0; |
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393 | period_finished_sig <= '0'; |
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394 | elsif rising_edge(clk_scaler) then |
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395 | if (scaler_counts_sig < scaler_period_sig) then |
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396 | scaler_counts_sig <= scaler_counts_sig + 1; |
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397 | period_finished_sig <= '0'; |
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398 | else |
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399 | period_finished_sig <= '1'; |
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400 | scaler_counts_sig <= 0; |
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401 | end if; |
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402 | end if; |
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403 | end process scaler_process; |
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404 | |
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405 | -- process(reset_period_sig) |
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406 | -- begin |
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407 | -- if rising_edge(reset_period_sig) then |
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408 | -- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then |
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409 | -- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); |
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410 | -- else |
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411 | -- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); |
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412 | -- end if; |
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413 | -- end if; |
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414 | -- end process; |
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415 | |
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416 | process(prescaling_FTU01_sig) |
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417 | begin |
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418 | if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then |
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419 | scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); |
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420 | else |
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421 | scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); |
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422 | end if; |
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423 | end process; |
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424 | |
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425 | detect_period_finished: process(clk) |
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426 | begin |
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427 | if rising_edge(clk) then |
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428 | new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig; |
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429 | if(new_period_ack_sig = '1') then |
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430 | new_period_sig <= '0'; |
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431 | else |
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432 | if (new_period_sr_sig(1 downto 0) = "01") then |
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433 | new_period_sig <= '1'; |
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434 | end if; |
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435 | end if; |
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436 | end if; |
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437 | end process detect_period_finished; |
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438 | |
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439 | end Behavioral; |
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