source: firmware/FTM/FTM_central_control.vhd@ 10782

Last change on this file since 10782 was 10779, checked in by weitzel, 14 years ago
some changes in FTM Timing_counter
File size: 16.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_trigger : out std_logic := '0';
68 config_trigger_done : in std_logic;
69 dna_start : out std_logic := '0';
70 dna_ready : in std_logic;
71 crate_reset : IN std_logic;
72 crate_reset_ack : OUT std_logic := '1';
73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
74 start_run : IN std_logic;
75 start_run_ack : OUT std_logic := '0';
76 stop_run : IN std_logic;
77 stop_run_ack : OUT std_logic := '0';
78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
79 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
80 start_run_param : IN std_logic_vector (15 DOWNTO 0);
81 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
82 trigger_start : out std_logic := '0';
83 trigger_stop : out std_logic := '1';
84 enable_ID_sending : out std_logic := '0';
85 reset_timer : out std_logic := '0';
86 crate_res_0 : out std_logic := '1';
87 crate_res_1 : out std_logic := '1';
88 crate_res_2 : out std_logic := '1';
89 crate_res_3 : out std_logic := '1'
90 );
91end FTM_central_control;
92
93architecture Behavioral of FTM_central_control is
94
95 signal reset_scaler_sig : std_logic := '0';
96 signal reset_period_sig : std_logic := '0';
97 signal scaler_counts_sig : integer := 0;
98 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
99 signal period_finished_sig : std_logic := '0';
100 signal wait_cnt_sig : integer range 0 to 10 := 0;
101 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
102 signal new_period_sig : std_logic := '0';
103 signal new_period_ack_sig : std_logic := '0';
104 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
105 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0;
106
107 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
108 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
109 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
110 CP_CONFIG_CC, CP_CONFIG_CC_01,
111 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
112 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
113 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
114 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
115 CP_SEND_START, CP_SEND_END,
116 CP_CRATE_RESET, CP_CRATE_RESET_ACK);
117 signal state_central_proc : state_central_proc_type := CP_INIT;
118
119 signal after_rates_state : state_central_proc_type := CP_IDLE;
120 signal after_ping_state : state_central_proc_type := CP_IDLE;
121
122begin
123
124 --central_proc : process (clk, prescaling_FTU01)
125 central_proc : process (clk)
126 begin
127 if rising_edge (clk) then
128 case state_central_proc is
129
130 when CP_INIT => -- wait for DCMs to lock
131 current_cc_state <= X"FFFF";
132 cc_state_test <= X"01";
133 if (clk_ready = '1') then
134 state_central_proc <= CP_INIT_DNA;
135 end if;
136
137 when CP_INIT_DNA => -- get FPGA DNA
138 current_cc_state <= X"FFFF";
139 cc_state_test <= X"01";
140 if (dna_ready = '1') then
141 state_central_proc <= CP_INIT_TIMER;
142 dna_start <= '0';
143 reset_timer <= '1'; -- reset timer after power-up
144 else
145 dna_start <= '1';
146 state_central_proc <= CP_INIT_DNA;
147 end if;
148
149 when CP_INIT_TIMER =>
150 current_cc_state <= X"FFFF";
151 cc_state_test <= X"01";
152 reset_timer <= '0'; -- finish reset timer after power-up
153 state_central_proc <= CP_CONFIG;
154
155 when CP_CONFIG_START =>
156 current_cc_state <= FTM_STATE_CFG;
157 cc_state_test <= X"02";
158 if (config_started_ack = '1') then
159 config_started <= '0';
160 state_central_proc <= CP_CONFIG;
161 end if;
162
163 when CP_CONFIG =>
164 current_cc_state <= FTM_STATE_CFG;
165 cc_state_test <= X"03";
166 config_start_eth <= '1';
167 if (config_started_eth = '1') then
168 config_start_eth <= '0';
169 state_central_proc <= CP_CONFIG_01;
170 end if;
171
172 when CP_CONFIG_01 =>
173 current_cc_state <= FTM_STATE_CFG;
174 cc_state_test <= X"04";
175 if (config_ready_eth = '1') then
176 state_central_proc <= CP_CONFIG_CC;
177 --state_central_proc <= CP_CONFIG_SCALER;
178 --state_central_proc <= CP_IDLE;
179 end if;
180
181 when CP_CONFIG_CC =>
182 current_cc_state <= FTM_STATE_CFG;
183 cc_state_test <= X"05";
184 config_start_cc <= '1';
185 if (config_started_cc = '1') then
186 config_start_cc <= '0';
187 state_central_proc <= CP_CONFIG_CC_01;
188 end if;
189
190 when CP_CONFIG_CC_01 =>
191 current_cc_state <= FTM_STATE_CFG;
192 cc_state_test <= X"06";
193 if (config_ready_cc = '1') then
194 state_central_proc <= CP_CONFIG_FTU;
195 end if;
196
197 when CP_CONFIG_FTU =>
198 current_cc_state <= FTM_STATE_CFG;
199 cc_state_test <= X"07";
200 config_start_ftu <= '1';
201 if (config_started_ftu = '1') then
202 config_start_ftu <= '0';
203 state_central_proc <= CP_CONFIG_FTU_01;
204 end if;
205
206 when CP_CONFIG_FTU_01 =>
207 current_cc_state <= FTM_STATE_CFG;
208 cc_state_test <= X"08";
209 if (config_ready_ftu = '1') then
210 state_central_proc <= CP_CONFIG_SCALER;
211 end if;
212
213 when CP_CONFIG_SCALER =>
214 current_cc_state <= FTM_STATE_CFG;
215 cc_state_test <= X"09";
216 prescaling_FTU01_sig <= prescaling_FTU01;
217 --reset_period_sig <= '1';
218 state_central_proc <= CP_CONFIG_SCALER_01;
219
220 when CP_CONFIG_SCALER_01 =>
221 current_cc_state <= FTM_STATE_CFG;
222 cc_state_test <= X"0A";
223 --reset_period_sig <= '0';
224 if wait_cnt_sig < 5 then
225 wait_cnt_sig <= wait_cnt_sig + 1;
226 reset_scaler_sig <= '1';
227 state_central_proc <= CP_CONFIG_SCALER_01;
228 else
229 wait_cnt_sig <= 0;
230 reset_scaler_sig <= '0';
231 state_central_proc <= CP_CONFIG_TRIGGER;
232 end if;
233
234 when CP_CONFIG_TRIGGER =>
235 current_cc_state <= FTM_STATE_CFG;
236 cc_state_test <= X"0B";
237 --config trigger_manager block
238 config_trigger <= '1';
239 state_central_proc <= CP_CONFIG_TRIGGER_01;
240
241 when CP_CONFIG_TRIGGER_01 =>
242 current_cc_state <= FTM_STATE_CFG;
243 cc_state_test <= X"0C";
244 config_trigger <= '0';
245 if (config_trigger_done = '1') then
246 state_central_proc <= CP_IDLE;
247 end if;
248
249 when CP_IDLE =>
250 current_cc_state <= FTM_STATE_IDLE;
251 reset_timer <= '0';
252 cc_state_test <= X"0D";
253 stop_run_ack <= '1';
254 start_run_ack <= '0';
255 if (new_config = '1') then
256 config_started <= '1';
257 start_run_ack <= '1'; --remove this line???
258 state_central_proc <= CP_CONFIG_START;
259 elsif (ping_ftu_start = '1') then
260 ping_ftu_start_ftu <= '1';
261 if (ping_ftu_started_ftu = '1') then
262 ping_ftu_start_ftu <= '0';
263 ping_ftu_started <= '1';
264 ping_ftu_ready <= '0';
265 after_ping_state <= CP_IDLE;
266 state_central_proc <= CP_PING;
267 end if;
268 --elsif (scaler_counts_sig = scaler_period_sig) then
269 elsif (new_period_sig = '1') then
270 new_period_ack_sig <= '1';
271 --rates_ftu <= '1';
272 --state_central_proc <= CP_READ_RATES;
273 after_rates_state <= CP_IDLE;
274 state_central_proc <= CP_START_RATES;
275 elsif (start_run = '1') then
276 start_run_ack <= '1';
277 if (start_run_param = PAR_START_RUN) then
278 reset_timer <= '1';
279 state_central_proc <= CP_RUNNING;
280 end if;
281 elsif (crate_reset = '1') then
282 crate_reset_ack <= '1';
283 state_central_proc <= CP_CRATE_RESET;
284 end if;
285
286 when CP_RUNNING =>
287 reset_timer <= '0';
288 current_cc_state <= FTM_STATE_RUN;
289 cc_state_test <= X"0E";
290 if (start_run = '0') then
291 start_run_ack <= '0';
292 stop_run_ack <= '0';
293 state_central_proc <= CP_RUNNING_01;
294 end if;
295
296 when CP_RUNNING_01 =>
297 current_cc_state <= FTM_STATE_RUN;
298 cc_state_test <= X"0F";
299 start_run_ack <= '1';
300 trigger_start <= '1';
301 trigger_stop <= '0';
302 enable_Id_sending <= '1';
303 if (new_config = '1') then
304 config_started <= '1';
305 state_central_proc <= CP_CONFIG_ACK;
306 elsif (ping_ftu_start = '1') then
307 ping_ftu_start_ftu <= '1';
308 if (ping_ftu_started_ftu = '1') then
309 ping_ftu_start_ftu <= '0';
310 ping_ftu_started <= '1';
311 ping_ftu_ready <= '0';
312 after_ping_state <= CP_RUNNING_01;
313 state_central_proc <= CP_PING;
314 end if;
315 elsif (new_period_sig = '1') then
316 new_period_ack_sig <= '1';
317 --rates_ftu <= '1';
318 --state_central_proc <= CP_READ_RATES;
319 after_rates_state <= CP_RUNNING_01;
320 state_central_proc <= CP_START_RATES;
321 elsif (stop_run = '1') then
322 stop_run_ack <= '1';
323 trigger_start <= '0';
324 trigger_stop <= '1';
325 enable_Id_sending <= '0';
326 state_central_proc <= CP_RUNNING_02;
327 elsif (crate_reset = '1') then
328 crate_reset_ack <= '1';
329 state_central_proc <= CP_CRATE_RESET_ACK;
330 end if;
331
332 when CP_RUNNING_02 =>
333 current_cc_state <= FTM_STATE_RUN;
334 cc_state_test <= X"10";
335 if (stop_run = '0') then
336 stop_run_ack <= '0';
337 reset_timer <= '1';
338 state_central_proc <= CP_IDLE;
339 end if;
340
341 when CP_CONFIG_ACK =>
342 cc_state_test <= X"11";
343 if (config_started_ack = '1') then
344 config_started <= '0';
345 state_central_proc <= CP_RUNNING_01;
346 end if;
347
348 when CP_PING =>
349 cc_state_test <= X"12";
350 if (ping_ftu_ready_ftu = '1') then
351 if (ping_ftu_start = '0') then
352 ping_ftu_started <= '0';
353 ping_ftu_ready <= '1';
354 --state_central_proc <= CP_IDLE;
355 state_central_proc <= after_ping_state;
356 end if;
357 end if;
358
359 when CP_START_RATES =>
360 cc_state_test <= X"13";
361 new_period_ack_sig <= '0';
362 dd_block_start_ftu <= '1';
363 dd_block_ready_ftu <= '0';
364 if (dd_block_start_ack_ftu = '1') then
365 dd_block_start_ftu <= '0';
366 rates_ftu <= '1';
367 state_central_proc <= CP_READ_RATES;
368 end if;
369
370 when CP_READ_RATES =>
371 cc_state_test <= X"14";
372 new_period_ack_sig <= '0';
373 if (rates_started_ftu = '1') then
374 rates_ftu <= '0';
375 state_central_proc <= CP_READ_RATES_01;
376 end if;
377
378 when CP_READ_RATES_01 =>
379 cc_state_test <= X"15";
380 if (rates_ready_ftu = '1') then
381 dd_block_ready_ftu <= '1';
382 if ( (start_run = '1') or (stop_run = '1') ) then
383 state_central_proc <= after_rates_state;
384 else
385 state_central_proc <= CP_SEND_START;
386 end if;
387 end if;
388
389 when CP_SEND_START =>
390 cc_state_test <= X"16";
391 dd_send <= '1';
392 if (dd_send_ack = '1') then
393 dd_send <= '0';
394 state_central_proc <= CP_SEND_END;
395 end if;
396
397 when CP_SEND_END =>
398 cc_state_test <= X"17";
399 if (dd_send_ready = '1') then
400 --state_central_proc <= CP_IDLE;
401 state_central_proc <= after_rates_state;
402 end if;
403
404 when CP_CRATE_RESET_ACK =>
405 cc_state_test <= X"18";
406 if (crate_reset = '0') then
407 crate_reset_ack <= '0';
408 state_central_proc <= CP_RUNNING_01;
409 end if;
410
411 when CP_CRATE_RESET =>
412 cc_state_test <= X"19";
413 if (crate_reset = '0') then
414 crate_reset_ack <= '0';
415 state_central_proc <= CP_IDLE;
416 end if;
417
418 when others =>
419 cc_state_test <= X"1A";
420
421 end case;
422 end if;
423 end process central_proc;
424
425 scaler_process: process(reset_scaler_sig, clk_scaler)
426 begin
427 if (reset_scaler_sig = '1') then
428 scaler_counts_sig <= 0;
429 period_finished_sig <= '0';
430 elsif rising_edge(clk_scaler) then
431 if (scaler_counts_sig < (scaler_period_sig - 1)) then
432 scaler_counts_sig <= scaler_counts_sig + 1;
433 period_finished_sig <= '0';
434 else
435 period_finished_sig <= '1';
436 scaler_counts_sig <= 0;
437 end if;
438 end if;
439 end process scaler_process;
440
441-- process(reset_period_sig)
442-- begin
443-- if rising_edge(reset_period_sig) then
444-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
445-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
446-- else
447-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
448-- end if;
449-- end if;
450-- end process;
451
452 process(prescaling_FTU01_sig)
453 begin
454 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
455 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
456 else
457 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
458 end if;
459 end process;
460
461 detect_period_finished: process(clk)
462 begin
463 if rising_edge(clk) then
464 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
465 if(new_period_ack_sig = '1') then
466 new_period_sig <= '0';
467 else
468 if (new_period_sr_sig(1 downto 0) = "01") then
469 new_period_sig <= '1';
470 end if;
471 end if;
472 end if;
473 end process detect_period_finished;
474
475end Behavioral;
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