source: firmware/FTM/FTM_central_control.vhd@ 10846

Last change on this file since 10846 was 10803, checked in by weitzel, 14 years ago
FTM: crate reset implemented
File size: 18.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_trigger : out std_logic := '0';
68 config_trigger_done : in std_logic;
69 dna_start : out std_logic := '0';
70 dna_ready : in std_logic;
71 crate_reset : IN std_logic;
72 crate_reset_ack : OUT std_logic := '0';
73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
74 start_run : IN std_logic;
75 start_run_ack : OUT std_logic := '0';
76 stop_run : IN std_logic;
77 stop_run_ack : OUT std_logic := '0';
78 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
79 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
80 start_run_param : IN std_logic_vector (15 DOWNTO 0);
81 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
82 trigger_start : out std_logic := '0';
83 trigger_stop : out std_logic := '1';
84 enable_ID_sending : out std_logic := '0';
85 reset_timer : out std_logic := '0';
86 crate_res_0 : out std_logic := '1';
87 crate_res_1 : out std_logic := '1';
88 crate_res_2 : out std_logic := '1';
89 crate_res_3 : out std_logic := '1'
90 );
91end FTM_central_control;
92
93architecture Behavioral of FTM_central_control is
94
95 signal reset_scaler_sig : std_logic := '0';
96 signal reset_period_sig : std_logic := '0';
97 signal scaler_counts_sig : integer := 0;
98 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
99 signal period_finished_sig : std_logic := '0';
100 signal wait_cnt_sig : integer range 0 to 10 := 0;
101 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
102 signal new_period_sig : std_logic := '0';
103 signal new_period_ack_sig : std_logic := '0';
104 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
105 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0;
106 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0) := (others => '0');
107
108 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
109 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
110 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
111 CP_CONFIG_CC, CP_CONFIG_CC_01,
112 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
113 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
114 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
115 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
116 CP_SEND_START, CP_SEND_END,
117 CP_CRATE_RESET, CP_CRATE_RESET_01, CP_CRATE_RESET_ACK);
118 signal state_central_proc : state_central_proc_type := CP_INIT;
119
120 signal after_rates_state : state_central_proc_type := CP_IDLE;
121 signal after_ping_state : state_central_proc_type := CP_IDLE;
122
123begin
124
125 --central_proc : process (clk, prescaling_FTU01)
126 central_proc : process (clk)
127 begin
128 if rising_edge (clk) then
129 case state_central_proc is
130
131 when CP_INIT => -- wait for DCMs to lock
132 current_cc_state <= X"FFFF";
133 cc_state_test <= X"01";
134 if (clk_ready = '1') then
135 state_central_proc <= CP_INIT_DNA;
136 end if;
137
138 when CP_INIT_DNA => -- get FPGA DNA
139 current_cc_state <= X"FFFF";
140 cc_state_test <= X"01";
141 if (dna_ready = '1') then
142 state_central_proc <= CP_INIT_TIMER;
143 dna_start <= '0';
144 reset_timer <= '1'; -- reset timer after power-up
145 else
146 dna_start <= '1';
147 state_central_proc <= CP_INIT_DNA;
148 end if;
149
150 when CP_INIT_TIMER =>
151 current_cc_state <= X"FFFF";
152 cc_state_test <= X"01";
153 reset_timer <= '0'; -- finish reset timer after power-up
154 state_central_proc <= CP_CONFIG;
155
156 when CP_CONFIG_START =>
157 current_cc_state <= FTM_STATE_CFG;
158 cc_state_test <= X"02";
159 if (config_started_ack = '1') then
160 config_started <= '0';
161 state_central_proc <= CP_CONFIG;
162 end if;
163
164 when CP_CONFIG =>
165 current_cc_state <= FTM_STATE_CFG;
166 cc_state_test <= X"03";
167 config_start_eth <= '1';
168 if (config_started_eth = '1') then
169 config_start_eth <= '0';
170 state_central_proc <= CP_CONFIG_01;
171 end if;
172
173 when CP_CONFIG_01 =>
174 current_cc_state <= FTM_STATE_CFG;
175 cc_state_test <= X"04";
176 if (config_ready_eth = '1') then
177 state_central_proc <= CP_CONFIG_CC;
178 --state_central_proc <= CP_CONFIG_SCALER;
179 --state_central_proc <= CP_IDLE;
180 --state_central_proc <= CP_CRATE_RESET;
181 end if;
182
183 when CP_CONFIG_CC =>
184 current_cc_state <= FTM_STATE_CFG;
185 cc_state_test <= X"05";
186 config_start_cc <= '1';
187 if (config_started_cc = '1') then
188 config_start_cc <= '0';
189 state_central_proc <= CP_CONFIG_CC_01;
190 end if;
191
192 when CP_CONFIG_CC_01 =>
193 current_cc_state <= FTM_STATE_CFG;
194 cc_state_test <= X"06";
195 if (config_ready_cc = '1') then
196 state_central_proc <= CP_CONFIG_FTU;
197 end if;
198
199 when CP_CONFIG_FTU =>
200 current_cc_state <= FTM_STATE_CFG;
201 cc_state_test <= X"07";
202 config_start_ftu <= '1';
203 if (config_started_ftu = '1') then
204 config_start_ftu <= '0';
205 state_central_proc <= CP_CONFIG_FTU_01;
206 end if;
207
208 when CP_CONFIG_FTU_01 =>
209 current_cc_state <= FTM_STATE_CFG;
210 cc_state_test <= X"08";
211 if (config_ready_ftu = '1') then
212 state_central_proc <= CP_CONFIG_SCALER;
213 end if;
214
215 when CP_CONFIG_SCALER =>
216 current_cc_state <= FTM_STATE_CFG;
217 cc_state_test <= X"09";
218 prescaling_FTU01_sig <= prescaling_FTU01;
219 --reset_period_sig <= '1';
220 state_central_proc <= CP_CONFIG_SCALER_01;
221
222 when CP_CONFIG_SCALER_01 =>
223 current_cc_state <= FTM_STATE_CFG;
224 cc_state_test <= X"0A";
225 --reset_period_sig <= '0';
226 if wait_cnt_sig < 5 then
227 wait_cnt_sig <= wait_cnt_sig + 1;
228 reset_scaler_sig <= '1';
229 state_central_proc <= CP_CONFIG_SCALER_01;
230 else
231 wait_cnt_sig <= 0;
232 reset_scaler_sig <= '0';
233 state_central_proc <= CP_CONFIG_TRIGGER;
234 end if;
235
236 when CP_CONFIG_TRIGGER =>
237 current_cc_state <= FTM_STATE_CFG;
238 cc_state_test <= X"0B";
239 --config trigger_manager block
240 config_trigger <= '1';
241 state_central_proc <= CP_CONFIG_TRIGGER_01;
242
243 when CP_CONFIG_TRIGGER_01 =>
244 current_cc_state <= FTM_STATE_CFG;
245 cc_state_test <= X"0C";
246 config_trigger <= '0';
247 if (config_trigger_done = '1') then
248 state_central_proc <= CP_IDLE;
249 end if;
250
251 when CP_IDLE =>
252 current_cc_state <= FTM_STATE_IDLE;
253 reset_timer <= '0';
254 cc_state_test <= X"0D";
255 stop_run_ack <= '1';
256 start_run_ack <= '0';
257 if (new_config = '1') then
258 config_started <= '1';
259 start_run_ack <= '1'; --remove this line???
260 state_central_proc <= CP_CONFIG_START;
261 elsif (ping_ftu_start = '1') then
262 ping_ftu_start_ftu <= '1';
263 if (ping_ftu_started_ftu = '1') then
264 ping_ftu_start_ftu <= '0';
265 ping_ftu_started <= '1';
266 ping_ftu_ready <= '0';
267 after_ping_state <= CP_IDLE;
268 state_central_proc <= CP_PING;
269 end if;
270 --elsif (scaler_counts_sig = scaler_period_sig) then
271 elsif (new_period_sig = '1') then
272 new_period_ack_sig <= '1';
273 --rates_ftu <= '1';
274 --state_central_proc <= CP_READ_RATES;
275 after_rates_state <= CP_IDLE;
276 state_central_proc <= CP_START_RATES;
277 elsif (start_run = '1') then
278 start_run_ack <= '1';
279 if (start_run_param = PAR_START_RUN) then
280 reset_timer <= '1';
281 state_central_proc <= CP_RUNNING;
282 end if;
283 elsif (crate_reset = '1') then
284 crate_reset_param_sig <= crate_reset_param;
285 crate_reset_ack <= '1';
286 state_central_proc <= CP_CRATE_RESET;
287 end if;
288
289 when CP_RUNNING =>
290 reset_timer <= '0';
291 current_cc_state <= FTM_STATE_RUN;
292 cc_state_test <= X"0E";
293 if (start_run = '0') then
294 start_run_ack <= '0';
295 stop_run_ack <= '0';
296 state_central_proc <= CP_RUNNING_01;
297 end if;
298
299 when CP_RUNNING_01 =>
300 current_cc_state <= FTM_STATE_RUN;
301 cc_state_test <= X"0F";
302 start_run_ack <= '1';
303 trigger_start <= '1';
304 trigger_stop <= '0';
305 enable_Id_sending <= '1';
306 if (new_config = '1') then
307 config_started <= '1';
308 state_central_proc <= CP_CONFIG_ACK;
309 elsif (ping_ftu_start = '1') then
310 ping_ftu_start_ftu <= '1';
311 if (ping_ftu_started_ftu = '1') then
312 ping_ftu_start_ftu <= '0';
313 ping_ftu_started <= '1';
314 ping_ftu_ready <= '0';
315 after_ping_state <= CP_RUNNING_01;
316 state_central_proc <= CP_PING;
317 end if;
318 elsif (new_period_sig = '1') then
319 new_period_ack_sig <= '1';
320 --rates_ftu <= '1';
321 --state_central_proc <= CP_READ_RATES;
322 after_rates_state <= CP_RUNNING_01;
323 state_central_proc <= CP_START_RATES;
324 elsif (stop_run = '1') then
325 stop_run_ack <= '1';
326 trigger_start <= '0';
327 trigger_stop <= '1';
328 enable_Id_sending <= '0';
329 state_central_proc <= CP_RUNNING_02;
330 elsif (crate_reset = '1') then
331 crate_reset_ack <= '1';
332 state_central_proc <= CP_CRATE_RESET_ACK;
333 end if;
334
335 when CP_RUNNING_02 =>
336 current_cc_state <= FTM_STATE_RUN;
337 cc_state_test <= X"10";
338 if (stop_run = '0') then
339 stop_run_ack <= '0';
340 reset_timer <= '1';
341 state_central_proc <= CP_IDLE;
342 end if;
343
344 when CP_CONFIG_ACK =>
345 cc_state_test <= X"11";
346 if (config_started_ack = '1') then
347 config_started <= '0';
348 state_central_proc <= CP_RUNNING_01;
349 end if;
350
351 when CP_PING =>
352 cc_state_test <= X"12";
353 if (ping_ftu_ready_ftu = '1') then
354 if (ping_ftu_start = '0') then
355 ping_ftu_started <= '0';
356 ping_ftu_ready <= '1';
357 --state_central_proc <= CP_IDLE;
358 state_central_proc <= after_ping_state;
359 end if;
360 end if;
361
362 when CP_START_RATES =>
363 cc_state_test <= X"13";
364 new_period_ack_sig <= '0';
365 dd_block_start_ftu <= '1';
366 dd_block_ready_ftu <= '0';
367 if (dd_block_start_ack_ftu = '1') then
368 dd_block_start_ftu <= '0';
369 rates_ftu <= '1';
370 state_central_proc <= CP_READ_RATES;
371 end if;
372
373 when CP_READ_RATES =>
374 cc_state_test <= X"14";
375 new_period_ack_sig <= '0';
376 if (rates_started_ftu = '1') then
377 rates_ftu <= '0';
378 state_central_proc <= CP_READ_RATES_01;
379 end if;
380
381 when CP_READ_RATES_01 =>
382 cc_state_test <= X"15";
383 if (rates_ready_ftu = '1') then
384 dd_block_ready_ftu <= '1';
385 if ( (start_run = '1') or (stop_run = '1') ) then
386 state_central_proc <= after_rates_state;
387 else
388 state_central_proc <= CP_SEND_START;
389 end if;
390 end if;
391
392 when CP_SEND_START =>
393 cc_state_test <= X"16";
394 dd_send <= '1';
395 if (dd_send_ack = '1') then
396 dd_send <= '0';
397 state_central_proc <= CP_SEND_END;
398 end if;
399
400 when CP_SEND_END =>
401 cc_state_test <= X"17";
402 if (dd_send_ready = '1') then
403 --state_central_proc <= CP_IDLE;
404 state_central_proc <= after_rates_state;
405 end if;
406
407 when CP_CRATE_RESET_ACK =>
408 cc_state_test <= X"18";
409 if (crate_reset = '0') then
410 crate_reset_ack <= '0';
411 state_central_proc <= CP_RUNNING_01;
412 end if;
413
414 when CP_CRATE_RESET =>
415 cc_state_test <= X"19";
416 if (crate_reset = '0') then
417 crate_reset_ack <= '0';
418 state_central_proc <= CP_CRATE_RESET_01;
419 end if;
420
421 when CP_CRATE_RESET_01 =>
422 cc_state_test <= X"1A";
423 if (reset_cnt_sig < RESET_TIME) then
424 reset_cnt_sig <= reset_cnt_sig + 1;
425 if (crate_reset_param_sig = "0000000000000001") then
426 crate_res_0 <= '0';
427 elsif (crate_reset_param_sig = "0000000000000010") then
428 crate_res_1 <= '0';
429 elsif (crate_reset_param_sig = "0000000000000100") then
430 crate_res_2 <= '0';
431 elsif (crate_reset_param_sig = "0000000000001000") then
432 crate_res_3 <= '0';
433 end if;
434 else
435 reset_cnt_sig <= 0;
436 crate_res_0 <= '1';
437 crate_res_1 <= '1';
438 crate_res_2 <= '1';
439 crate_res_3 <= '1';
440 state_central_proc <= CP_IDLE;
441 end if;
442
443 when others =>
444 cc_state_test <= X"1B";
445
446 end case;
447 end if;
448 end process central_proc;
449
450 scaler_process: process(reset_scaler_sig, clk_scaler)
451 begin
452 if (reset_scaler_sig = '1') then
453 scaler_counts_sig <= 0;
454 period_finished_sig <= '0';
455 elsif rising_edge(clk_scaler) then
456 if (scaler_counts_sig < (scaler_period_sig - 1)) then
457 scaler_counts_sig <= scaler_counts_sig + 1;
458 period_finished_sig <= '0';
459 else
460 period_finished_sig <= '1';
461 scaler_counts_sig <= 0;
462 end if;
463 end if;
464 end process scaler_process;
465
466-- process(reset_period_sig)
467-- begin
468-- if rising_edge(reset_period_sig) then
469-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
470-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
471-- else
472-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
473-- end if;
474-- end if;
475-- end process;
476
477 process(prescaling_FTU01_sig)
478 begin
479 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
480 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
481 else
482 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
483 end if;
484 end process;
485
486 detect_period_finished: process(clk)
487 begin
488 if rising_edge(clk) then
489 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
490 if(new_period_ack_sig = '1') then
491 new_period_sig <= '0';
492 else
493 if (new_period_sr_sig(1 downto 0) = "01") then
494 new_period_sig <= '1';
495 end if;
496 end if;
497 end if;
498 end process detect_period_finished;
499
500end Behavioral;
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