source: firmware/FTM/FTM_central_control.vhd@ 11154

Last change on this file since 11154 was 10879, checked in by weitzel, 14 years ago
FTM: new light pulser interface, new timing constraint in .ucf file
File size: 18.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 15:56:13 02/28/2011
6-- Design Name:
7-- Module Name: FTM_central_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Central FSM for FTM firmware
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_central_control is
35 port(
36 clk : IN std_logic;
37 clk_ready : in std_logic;
38 clk_scaler : IN std_logic;
39 new_config : IN std_logic;
40 config_started : OUT std_logic := '0';
41 config_started_ack : IN std_logic;
42 config_start_eth : OUT std_logic := '0';
43 config_started_eth : IN std_logic;
44 config_ready_eth : IN std_logic;
45 config_start_ftu : OUT std_logic := '0';
46 config_started_ftu : IN std_logic ;
47 config_ready_ftu : IN std_logic ;
48 ping_ftu_start : IN std_logic;
49 ping_ftu_started : OUT std_logic := '0';
50 ping_ftu_ready : OUT std_logic := '0';
51 ping_ftu_start_ftu : OUT std_logic := '0';
52 ping_ftu_started_ftu : IN std_logic;
53 ping_ftu_ready_ftu : IN std_logic;
54 rates_ftu : OUT std_logic := '0';
55 rates_started_ftu : IN std_logic;
56 rates_ready_ftu : IN std_logic;
57 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
58 dd_send : OUT std_logic := '0';
59 dd_send_ack : IN std_logic;
60 dd_send_ready : IN std_logic;
61 dd_block_ready_ftu : out std_logic := '0';
62 dd_block_start_ack_ftu : in std_logic;
63 dd_block_start_ftu : out std_logic := '0';
64 config_start_cc : out std_logic := '0';
65 config_started_cc : in std_logic;
66 config_ready_cc : in std_logic;
67 config_start_lp : out std_logic := '0';
68 config_started_lp : in std_logic;
69 config_ready_lp : in std_logic;
70 config_trigger : out std_logic := '0';
71 config_trigger_done : in std_logic;
72 dna_start : out std_logic := '0';
73 dna_ready : in std_logic;
74 crate_reset : IN std_logic;
75 crate_reset_ack : OUT std_logic := '0';
76 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
77 start_run : IN std_logic;
78 start_run_ack : OUT std_logic := '0';
79 stop_run : IN std_logic;
80 stop_run_ack : OUT std_logic := '0';
81 current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
82 cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF";
83 start_run_param : IN std_logic_vector (15 DOWNTO 0);
84 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
85 trigger_start : out std_logic := '0';
86 trigger_stop : out std_logic := '1';
87 enable_ID_sending : out std_logic := '0';
88 reset_timer : out std_logic := '0';
89 crate_res_0 : out std_logic := '1';
90 crate_res_1 : out std_logic := '1';
91 crate_res_2 : out std_logic := '1';
92 crate_res_3 : out std_logic := '1'
93 );
94end FTM_central_control;
95
96architecture Behavioral of FTM_central_control is
97
98 signal reset_scaler_sig : std_logic := '0';
99 signal reset_period_sig : std_logic := '0';
100 signal scaler_counts_sig : integer := 0;
101 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
102 signal period_finished_sig : std_logic := '0';
103 signal wait_cnt_sig : integer range 0 to 10 := 0;
104 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0');
105 signal new_period_sig : std_logic := '0';
106 signal new_period_ack_sig : std_logic := '0';
107 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
108 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0;
109 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0) := (others => '0');
110
111 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
112 CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK,
113 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
114 CP_CONFIG_CC, CP_CONFIG_CC_01,
115 CP_CONFIG_LP, CP_CONFIG_LP_01,
116 CP_CONFIG_FTU, CP_CONFIG_FTU_01,
117 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
118 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
119 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
120 CP_SEND_START, CP_SEND_END,
121 CP_CRATE_RESET, CP_CRATE_RESET_01, CP_CRATE_RESET_ACK);
122 signal state_central_proc : state_central_proc_type := CP_INIT;
123
124 signal after_rates_state : state_central_proc_type := CP_IDLE;
125 signal after_ping_state : state_central_proc_type := CP_IDLE;
126
127begin
128
129 --central_proc : process (clk, prescaling_FTU01)
130 central_proc : process (clk)
131 begin
132 if rising_edge (clk) then
133 case state_central_proc is
134
135 when CP_INIT => -- wait for DCMs to lock
136 current_cc_state <= X"FFFF";
137 cc_state_test <= X"01";
138 if (clk_ready = '1') then
139 state_central_proc <= CP_INIT_DNA;
140 end if;
141
142 when CP_INIT_DNA => -- get FPGA DNA
143 current_cc_state <= X"FFFF";
144 cc_state_test <= X"01";
145 if (dna_ready = '1') then
146 state_central_proc <= CP_INIT_TIMER;
147 dna_start <= '0';
148 reset_timer <= '1'; -- reset timer after power-up
149 else
150 dna_start <= '1';
151 state_central_proc <= CP_INIT_DNA;
152 end if;
153
154 when CP_INIT_TIMER =>
155 current_cc_state <= X"FFFF";
156 cc_state_test <= X"01";
157 reset_timer <= '0'; -- finish reset timer after power-up
158 state_central_proc <= CP_CONFIG;
159
160 when CP_CONFIG_START =>
161 current_cc_state <= FTM_STATE_CFG;
162 cc_state_test <= X"02";
163 if (config_started_ack = '1') then
164 config_started <= '0';
165 state_central_proc <= CP_CONFIG;
166 end if;
167
168 when CP_CONFIG =>
169 current_cc_state <= FTM_STATE_CFG;
170 cc_state_test <= X"03";
171 config_start_eth <= '1';
172 if (config_started_eth = '1') then
173 config_start_eth <= '0';
174 state_central_proc <= CP_CONFIG_01;
175 end if;
176
177 when CP_CONFIG_01 =>
178 current_cc_state <= FTM_STATE_CFG;
179 cc_state_test <= X"04";
180 if (config_ready_eth = '1') then
181 state_central_proc <= CP_CONFIG_CC;
182 --state_central_proc <= CP_CONFIG_SCALER;
183 --state_central_proc <= CP_IDLE;
184 --state_central_proc <= CP_CRATE_RESET;
185 end if;
186
187 when CP_CONFIG_CC =>
188 current_cc_state <= FTM_STATE_CFG;
189 cc_state_test <= X"05";
190 config_start_cc <= '1';
191 if (config_started_cc = '1') then
192 config_start_cc <= '0';
193 state_central_proc <= CP_CONFIG_CC_01;
194 end if;
195
196 when CP_CONFIG_CC_01 =>
197 current_cc_state <= FTM_STATE_CFG;
198 cc_state_test <= X"06";
199 if (config_ready_cc = '1') then
200 state_central_proc <= CP_CONFIG_LP;
201 --state_central_proc <= CP_CONFIG_FTU;
202 end if;
203
204 when CP_CONFIG_LP =>
205 current_cc_state <= FTM_STATE_CFG;
206 cc_state_test <= X"1C";
207 config_start_lp <= '1';
208 if (config_started_lp = '1') then
209 config_start_lp <= '0';
210 state_central_proc <= CP_CONFIG_LP_01;
211 end if;
212
213 when CP_CONFIG_LP_01 =>
214 current_cc_state <= FTM_STATE_CFG;
215 cc_state_test <= X"1D";
216 if (config_ready_lp = '1') then
217 state_central_proc <= CP_CONFIG_FTU;
218 end if;
219
220 when CP_CONFIG_FTU =>
221 current_cc_state <= FTM_STATE_CFG;
222 cc_state_test <= X"07";
223 config_start_ftu <= '1';
224 if (config_started_ftu = '1') then
225 config_start_ftu <= '0';
226 state_central_proc <= CP_CONFIG_FTU_01;
227 end if;
228
229 when CP_CONFIG_FTU_01 =>
230 current_cc_state <= FTM_STATE_CFG;
231 cc_state_test <= X"08";
232 if (config_ready_ftu = '1') then
233 state_central_proc <= CP_CONFIG_SCALER;
234 end if;
235
236 when CP_CONFIG_SCALER =>
237 current_cc_state <= FTM_STATE_CFG;
238 cc_state_test <= X"09";
239 prescaling_FTU01_sig <= prescaling_FTU01;
240 --reset_period_sig <= '1';
241 state_central_proc <= CP_CONFIG_SCALER_01;
242
243 when CP_CONFIG_SCALER_01 =>
244 current_cc_state <= FTM_STATE_CFG;
245 cc_state_test <= X"0A";
246 --reset_period_sig <= '0';
247 if wait_cnt_sig < 5 then
248 wait_cnt_sig <= wait_cnt_sig + 1;
249 reset_scaler_sig <= '1';
250 state_central_proc <= CP_CONFIG_SCALER_01;
251 else
252 wait_cnt_sig <= 0;
253 reset_scaler_sig <= '0';
254 state_central_proc <= CP_CONFIG_TRIGGER;
255 end if;
256
257 when CP_CONFIG_TRIGGER =>
258 current_cc_state <= FTM_STATE_CFG;
259 cc_state_test <= X"0B";
260 --config trigger_manager block
261 config_trigger <= '1';
262 state_central_proc <= CP_CONFIG_TRIGGER_01;
263
264 when CP_CONFIG_TRIGGER_01 =>
265 current_cc_state <= FTM_STATE_CFG;
266 cc_state_test <= X"0C";
267 config_trigger <= '0';
268 if (config_trigger_done = '1') then
269 state_central_proc <= CP_IDLE;
270 end if;
271
272 when CP_IDLE =>
273 current_cc_state <= FTM_STATE_IDLE;
274 reset_timer <= '0';
275 cc_state_test <= X"0D";
276 stop_run_ack <= '1';
277 start_run_ack <= '0';
278 if (new_config = '1') then
279 config_started <= '1';
280 start_run_ack <= '1'; --remove this line???
281 state_central_proc <= CP_CONFIG_START;
282 elsif (ping_ftu_start = '1') then
283 ping_ftu_start_ftu <= '1';
284 if (ping_ftu_started_ftu = '1') then
285 ping_ftu_start_ftu <= '0';
286 ping_ftu_started <= '1';
287 ping_ftu_ready <= '0';
288 after_ping_state <= CP_IDLE;
289 state_central_proc <= CP_PING;
290 end if;
291 --elsif (scaler_counts_sig = scaler_period_sig) then
292 elsif (new_period_sig = '1') then
293 new_period_ack_sig <= '1';
294 --rates_ftu <= '1';
295 --state_central_proc <= CP_READ_RATES;
296 after_rates_state <= CP_IDLE;
297 state_central_proc <= CP_START_RATES;
298 elsif (start_run = '1') then
299 start_run_ack <= '1';
300 if (start_run_param = PAR_START_RUN) then
301 reset_timer <= '1';
302 state_central_proc <= CP_RUNNING;
303 end if;
304 elsif (crate_reset = '1') then
305 crate_reset_param_sig <= crate_reset_param;
306 crate_reset_ack <= '1';
307 state_central_proc <= CP_CRATE_RESET;
308 end if;
309
310 when CP_RUNNING =>
311 reset_timer <= '0';
312 current_cc_state <= FTM_STATE_RUN;
313 cc_state_test <= X"0E";
314 if (start_run = '0') then
315 start_run_ack <= '0';
316 stop_run_ack <= '0';
317 state_central_proc <= CP_RUNNING_01;
318 end if;
319
320 when CP_RUNNING_01 =>
321 current_cc_state <= FTM_STATE_RUN;
322 cc_state_test <= X"0F";
323 start_run_ack <= '1';
324 trigger_start <= '1';
325 trigger_stop <= '0';
326 enable_Id_sending <= '1';
327 if (new_config = '1') then
328 config_started <= '1';
329 state_central_proc <= CP_CONFIG_ACK;
330 elsif (ping_ftu_start = '1') then
331 ping_ftu_start_ftu <= '1';
332 if (ping_ftu_started_ftu = '1') then
333 ping_ftu_start_ftu <= '0';
334 ping_ftu_started <= '1';
335 ping_ftu_ready <= '0';
336 after_ping_state <= CP_RUNNING_01;
337 state_central_proc <= CP_PING;
338 end if;
339 elsif (new_period_sig = '1') then
340 new_period_ack_sig <= '1';
341 --rates_ftu <= '1';
342 --state_central_proc <= CP_READ_RATES;
343 after_rates_state <= CP_RUNNING_01;
344 state_central_proc <= CP_START_RATES;
345 elsif (stop_run = '1') then
346 stop_run_ack <= '1';
347 trigger_start <= '0';
348 trigger_stop <= '1';
349 enable_Id_sending <= '0';
350 state_central_proc <= CP_RUNNING_02;
351 elsif (crate_reset = '1') then
352 crate_reset_ack <= '1';
353 state_central_proc <= CP_CRATE_RESET_ACK;
354 end if;
355
356 when CP_RUNNING_02 =>
357 current_cc_state <= FTM_STATE_RUN;
358 cc_state_test <= X"10";
359 if (stop_run = '0') then
360 stop_run_ack <= '0';
361 reset_timer <= '1';
362 state_central_proc <= CP_IDLE;
363 end if;
364
365 when CP_CONFIG_ACK =>
366 cc_state_test <= X"11";
367 if (config_started_ack = '1') then
368 config_started <= '0';
369 state_central_proc <= CP_RUNNING_01;
370 end if;
371
372 when CP_PING =>
373 cc_state_test <= X"12";
374 if (ping_ftu_ready_ftu = '1') then
375 if (ping_ftu_start = '0') then
376 ping_ftu_started <= '0';
377 ping_ftu_ready <= '1';
378 --state_central_proc <= CP_IDLE;
379 state_central_proc <= after_ping_state;
380 end if;
381 end if;
382
383 when CP_START_RATES =>
384 cc_state_test <= X"13";
385 new_period_ack_sig <= '0';
386 dd_block_start_ftu <= '1';
387 dd_block_ready_ftu <= '0';
388 if (dd_block_start_ack_ftu = '1') then
389 dd_block_start_ftu <= '0';
390 rates_ftu <= '1';
391 state_central_proc <= CP_READ_RATES;
392 end if;
393
394 when CP_READ_RATES =>
395 cc_state_test <= X"14";
396 new_period_ack_sig <= '0';
397 if (rates_started_ftu = '1') then
398 rates_ftu <= '0';
399 state_central_proc <= CP_READ_RATES_01;
400 end if;
401
402 when CP_READ_RATES_01 =>
403 cc_state_test <= X"15";
404 if (rates_ready_ftu = '1') then
405 dd_block_ready_ftu <= '1';
406 if ( (start_run = '1') or (stop_run = '1') ) then
407 state_central_proc <= after_rates_state;
408 else
409 state_central_proc <= CP_SEND_START;
410 end if;
411 end if;
412
413 when CP_SEND_START =>
414 cc_state_test <= X"16";
415 dd_send <= '1';
416 if (dd_send_ack = '1') then
417 dd_send <= '0';
418 state_central_proc <= CP_SEND_END;
419 end if;
420
421 when CP_SEND_END =>
422 cc_state_test <= X"17";
423 if (dd_send_ready = '1') then
424 --state_central_proc <= CP_IDLE;
425 state_central_proc <= after_rates_state;
426 end if;
427
428 when CP_CRATE_RESET_ACK =>
429 cc_state_test <= X"18";
430 if (crate_reset = '0') then
431 crate_reset_ack <= '0';
432 state_central_proc <= CP_RUNNING_01;
433 end if;
434
435 when CP_CRATE_RESET =>
436 cc_state_test <= X"19";
437 if (crate_reset = '0') then
438 crate_reset_ack <= '0';
439 state_central_proc <= CP_CRATE_RESET_01;
440 end if;
441
442 when CP_CRATE_RESET_01 =>
443 cc_state_test <= X"1A";
444 if (reset_cnt_sig < RESET_TIME) then
445 reset_cnt_sig <= reset_cnt_sig + 1;
446 if (crate_reset_param_sig = "0000000000000001") then
447 crate_res_0 <= '0';
448 elsif (crate_reset_param_sig = "0000000000000010") then
449 crate_res_1 <= '0';
450 elsif (crate_reset_param_sig = "0000000000000100") then
451 crate_res_2 <= '0';
452 elsif (crate_reset_param_sig = "0000000000001000") then
453 crate_res_3 <= '0';
454 end if;
455 else
456 reset_cnt_sig <= 0;
457 crate_res_0 <= '1';
458 crate_res_1 <= '1';
459 crate_res_2 <= '1';
460 crate_res_3 <= '1';
461 state_central_proc <= CP_IDLE;
462 end if;
463
464 when others =>
465 cc_state_test <= X"1B";
466
467 end case;
468 end if;
469 end process central_proc;
470
471 scaler_process: process(reset_scaler_sig, clk_scaler)
472 begin
473 if (reset_scaler_sig = '1') then
474 scaler_counts_sig <= 0;
475 period_finished_sig <= '0';
476 elsif rising_edge(clk_scaler) then
477 if (scaler_counts_sig < (scaler_period_sig - 1)) then
478 scaler_counts_sig <= scaler_counts_sig + 1;
479 period_finished_sig <= '0';
480 else
481 period_finished_sig <= '1';
482 scaler_counts_sig <= 0;
483 end if;
484 end if;
485 end process scaler_process;
486
487-- process(reset_period_sig)
488-- begin
489-- if rising_edge(reset_period_sig) then
490-- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then
491-- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
492-- else
493-- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
494-- end if;
495-- end if;
496-- end process;
497
498 process(prescaling_FTU01_sig)
499 begin
500 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then
501 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER)));
502 else
503 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
504 end if;
505 end process;
506
507 detect_period_finished: process(clk)
508 begin
509 if rising_edge(clk) then
510 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig;
511 if(new_period_ack_sig = '1') then
512 new_period_sig <= '0';
513 else
514 if (new_period_sr_sig(1 downto 0) = "01") then
515 new_period_sig <= '1';
516 end if;
517 end if;
518 end if;
519 end process detect_period_finished;
520
521end Behavioral;
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