source: firmware/FTM/FTM_top.vhd@ 11267

Last change on this file since 11267 was 10929, checked in by weitzel, 14 years ago
FTM: patch in LP interface to correct for swapped channels; change in FTUcontrol to fix first-board-bug
File size: 55.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 Bus2_TxD_0 : out STD_LOGIC;
153
154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 Bus2_TxD_1 : out STD_LOGIC;
156
157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 Bus2_TxD_2 : out STD_LOGIC;
159
160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 Crate_Res0 : out STD_LOGIC;
180 Crate_Res1 : out STD_LOGIC;
181 Crate_Res2 : out STD_LOGIC;
182 Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 RES_p : out STD_LOGIC; -- RES+ Reset
215 RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 Cal_0_p : out STD_LOGIC;
233 Cal_0_n : out STD_LOGIC;
234 Cal_1_p : out STD_LOGIC;
235 Cal_1_n : out STD_LOGIC;
236 Cal_2_p : out STD_LOGIC;
237 Cal_2_n : out STD_LOGIC;
238 Cal_3_p : out STD_LOGIC;
239 Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 Cal_4_p : out STD_LOGIC;
244 Cal_4_n : out STD_LOGIC;
245 Cal_5_p : out STD_LOGIC;
246 Cal_5_n : out STD_LOGIC;
247 Cal_6_p : out STD_LOGIC;
248 Cal_6_n : out STD_LOGIC;
249 Cal_7_p : out STD_LOGIC;
250 Cal_7_n : out STD_LOGIC;
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 TP : inout STD_LOGIC_VECTOR(32 downto 0)
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_ftu_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_ftu_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic; -- initialized in central control
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352
353 signal config_start_lp_sig : std_logic; -- initialized in central control
354 signal config_started_lp_sig : std_logic; -- initialized in light pulser interface
355 signal config_ready_lp_sig : std_logic; -- initialized in light pulser interface
356
357 signal config_trigger_sig : std_logic;
358 signal config_trigger_done_sig : std_logic;
359
360 signal clk_buf_sig : std_logic;
361 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
362 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
363 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
364 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
365 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
366
367 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager
368 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager
369 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast
370
371 signal trigger_active_sig : std_logic; -- initialized in trigger manager
372
373 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
374
375 signal trigger_signal_sig : std_logic := '0';
376 signal TIM_signal_sig : std_logic := '0';
377
378 --signals for FPGA DNA identifier
379 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen
380 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control
381 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen
382
383 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
384
385 signal get_ot_counter_sig : std_logic;
386 signal get_ot_counter_started_sig : std_logic;
387 signal get_ot_counter_ready_sig : std_logic;
388 signal on_time_counter_sig : std_logic_vector(47 downto 0);
389
390 signal get_ts_counter_sig : std_logic;
391 signal get_ts_counter_started_sig : std_logic;
392 signal get_ts_counter_ready_sig : std_logic;
393 signal timestamp_counter_sig : std_logic_vector(47 downto 0);
394
395 signal crate_reset_sig : std_logic;
396 signal crate_reset_ack_sig : std_logic;
397 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0);
398 signal start_run_sig : std_logic;
399 signal start_run_ack_sig : std_logic;
400 signal stop_run_sig : std_logic;
401 signal stop_run_ack_sig : std_logic;
402 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0);
403 signal cc_state_test_sig : std_logic_vector ( 7 downto 0);
404 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0);
405 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0);
406
407 signal trigger_start_sig : std_logic;
408 signal trigger_stop_sig : std_logic;
409
410 signal enable_ID_sending_sig : std_logic;
411 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control
412
413 signal crate_res0_sig : std_logic; -- initialized in FTM_central_control
414 signal crate_res1_sig : std_logic; -- initialized in FTM_central_control
415 signal crate_res2_sig : std_logic; -- initialized in FTM_central_control
416 signal crate_res3_sig : std_logic; -- initialized in FTM_central_control
417
418 signal LP1_pulse_sig : std_logic := '0';
419 signal LP2_pulse_sig : std_logic := '0';
420
421-- component FTM_clk_gen
422-- port(
423-- clk : IN STD_LOGIC;
424-- rst : IN STD_LOGIC;
425-- clk_1 : OUT STD_LOGIC;
426-- clk_50 : OUT STD_LOGIC;
427-- clk_250 : OUT STD_LOGIC;
428-- clk_250_ps : OUT STD_LOGIC;
429-- ready : OUT STD_LOGIC
430-- );
431-- end component;
432
433 component FTM_clk_gen_2
434 port(
435 clk : IN STD_LOGIC;
436 rst : IN STD_LOGIC;
437 clk_1 : OUT STD_LOGIC;
438 clk_50 : OUT STD_LOGIC;
439 clk_250 : OUT STD_LOGIC;
440 clk_250_ps : OUT STD_LOGIC;
441 ready : OUT STD_LOGIC
442 );
443 end component;
444
445 component FTM_dna_gen
446 port(
447 clk : IN STD_LOGIC;
448 start : IN STD_LOGIC;
449 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
450 ready : OUT STD_LOGIC
451 );
452 end component;
453
454 component trigger_manager
455 port(
456 --clocks
457 clk_50MHz : in std_logic;
458 clk_250MHz : in std_logic;
459 clk_250MHz_180 : in std_logic;
460 --trigger primitives from FTUs
461 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
462 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
463 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
464 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
465 --external signals
466 ext_trig_1 : in std_logic;
467 ext_trig_2 : in std_logic;
468 ext_veto : in std_logic;
469 FAD_busy_0 : in std_logic; --crate 0
470 FAD_busy_1 : in std_logic; --crate 1
471 FAD_busy_2 : in std_logic; --crate 2
472 FAD_busy_3 : in std_logic; --crate 3
473 --control signals from e.g. main control
474 start_run : in std_logic; --enable trigger output
475 stop_run : in std_logic; --disable trigger output
476 new_config : in std_logic;
477 --settings register (see FTM Firmware Specifications)
478 general_settings : in std_logic_vector(15 downto 0);
479 LP_and_PED_freq : in std_logic_vector(15 downto 0);
480 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
481 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
482 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
483 trigger_delay : in std_logic_vector(15 downto 0);
484 TIM_delay : in std_logic_vector(15 downto 0);
485 dead_time : in std_logic_vector(15 downto 0);
486 coinc_window_phys : in std_logic_vector(15 downto 0);
487 coinc_window_calib : in std_logic_vector(15 downto 0);
488 active_FTU_list_0 : in std_logic_vector(15 downto 0);
489 active_FTU_list_1 : in std_logic_vector(15 downto 0);
490 active_FTU_list_2 : in std_logic_vector(15 downto 0);
491 active_FTU_list_3 : in std_logic_vector(15 downto 0);
492 --control signals or information for other entities
493 trigger_ID_read : in std_logic;
494 trig_cnt_copy_read : in std_logic;
495 trigger_ID_ready : out std_logic;
496 trigger_ID : out std_logic_vector(55 downto 0);
497 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
498 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
499 trigger_active : out std_logic; --phys triggers are enabled/active
500 config_done : out std_logic;
501 LP1_pulse : out std_logic; --send start signal to light pulser 1
502 LP2_pulse : out std_logic; --send start signal to light pulser 2
503 --trigger and time marker output signals to FADs
504 trigger_signal : out std_logic;
505 TIM_signal : out std_logic
506 );
507 end component;
508
509 component Clock_cond_interface is
510 port(
511 clk : IN STD_LOGIC;
512 CLK_Clk_Cond : out STD_LOGIC;
513 LE_Clk_Cond : out STD_LOGIC;
514 DATA_Clk_Cond : out STD_LOGIC;
515 SYNC_Clk_Cond : out STD_LOGIC;
516 LD_Clk_Cond : in STD_LOGIC;
517 TIM_Sel : out STD_LOGIC;
518 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
519 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
520 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
521 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
522 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
523 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
524 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
525 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
526 start_config : in STD_LOGIC;
527 config_started : out STD_LOGIC;
528 config_done : out STD_LOGIC;
529 timemarker_select: in STD_LOGIC
530 );
531 end component;
532
533 component FTM_central_control
534 port(
535 clk : IN std_logic;
536 clk_ready : in std_logic;
537 clk_scaler : IN std_logic;
538 new_config : IN std_logic;
539 config_started : OUT std_logic := '0';
540 config_started_ack : IN std_logic;
541 config_start_eth : OUT std_logic := '0';
542 config_started_eth : IN std_logic;
543 config_ready_eth : IN std_logic;
544 config_start_ftu : OUT std_logic := '0';
545 config_started_ftu : IN std_logic;
546 config_ready_ftu : IN std_logic;
547 ping_ftu_start : IN std_logic;
548 ping_ftu_started : OUT std_logic := '0';
549 ping_ftu_ready : OUT std_logic := '0';
550 ping_ftu_start_ftu : OUT std_logic := '0';
551 ping_ftu_started_ftu : IN std_logic;
552 ping_ftu_ready_ftu : IN std_logic;
553 rates_ftu : OUT std_logic := '0';
554 rates_started_ftu : IN std_logic;
555 rates_ready_ftu : IN std_logic;
556 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
557 dd_send : OUT std_logic := '0';
558 dd_send_ack : IN std_logic;
559 dd_send_ready : IN std_logic;
560 dd_block_ready_ftu : out std_logic := '0';
561 dd_block_start_ack_ftu : in std_logic;
562 dd_block_start_ftu : out std_logic := '0';
563 config_start_cc : out std_logic := '0';
564 config_started_cc : in std_logic;
565 config_ready_cc : in std_logic;
566 config_start_lp : out std_logic := '0';
567 config_started_lp : in std_logic;
568 config_ready_lp : in std_logic;
569 config_trigger : out std_logic;
570 config_trigger_done : in std_logic;
571 dna_start : out std_logic;
572 dna_ready : in std_logic;
573 crate_reset : IN std_logic;
574 crate_reset_ack : OUT std_logic;
575 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
576 start_run : IN std_logic;
577 start_run_ack : OUT std_logic;
578 stop_run : IN std_logic;
579 stop_run_ack : OUT std_logic;
580 current_cc_state : OUT std_logic_vector (15 DOWNTO 0);
581 cc_state_test : OUT std_logic_vector ( 7 downto 0);
582 start_run_param : IN std_logic_vector (15 DOWNTO 0);
583 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
584 trigger_start : out std_logic;
585 trigger_stop : out std_logic;
586 enable_ID_sending : out std_logic;
587 reset_timer : out std_logic;
588 crate_res_0 : out std_logic;
589 crate_res_1 : out std_logic;
590 crate_res_2 : out std_logic;
591 crate_res_3 : out std_logic
592 );
593 end component;
594
595 component FTM_ftu_control
596 port(
597 clk_50MHz : in std_logic;
598 rx_en : out STD_LOGIC;
599 tx_en : out STD_LOGIC;
600 rx_d_0 : in STD_LOGIC;
601 tx_d_0 : out STD_LOGIC;
602 rx_d_1 : in STD_LOGIC;
603 tx_d_1 : out STD_LOGIC;
604 rx_d_2 : in STD_LOGIC;
605 tx_d_2 : out STD_LOGIC;
606 rx_d_3 : in STD_LOGIC;
607 tx_d_3 : out STD_LOGIC;
608 new_config : in std_logic;
609 ping_all : in std_logic;
610 read_rates : in std_logic;
611 read_rates_started : out std_logic := '0';
612 read_rates_done : out std_logic := '0';
613 new_config_started : out std_logic := '0';
614 new_config_done : out std_logic := '0';
615 ping_all_started : out std_logic := '0';
616 ping_all_done : out std_logic := '0';
617 ftu_active_cr0 : in std_logic_vector (15 downto 0);
618 ftu_active_cr1 : in std_logic_vector (15 downto 0);
619 ftu_active_cr2 : in std_logic_vector (15 downto 0);
620 ftu_active_cr3 : in std_logic_vector (15 downto 0);
621 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
622 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
623 ftu_error_send : out std_logic := '0';
624 ftu_error_send_ack : in std_logic;
625 ftu_error_send_ready : in std_logic;
626 static_RAM_busy : in std_logic;
627 static_RAM_started : in std_logic;
628 static_RAM_ready : in std_logic;
629 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
630 read_static_RAM : out std_logic := '0';
631 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
632 dynamic_RAM_busy : in std_logic;
633 dynamic_RAM_started : in std_logic;
634 dynamic_RAM_ready : in std_logic;
635 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
636 write_dynamic_RAM : out std_logic := '0';
637 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
638 FTUlist_RAM_busy : in std_logic;
639 FTUlist_RAM_started : in std_logic;
640 FTUlist_RAM_ready : in std_logic;
641 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
642 write_FTUlist_RAM : out std_logic := '0';
643 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
644 );
645 end component;
646
647 component FTM_fad_broadcast
648 port(
649 clk_50MHz : in std_logic;
650 rx_en : out STD_LOGIC;
651 tx_en : out STD_LOGIC;
652 rx_d_0 : in STD_LOGIC;
653 tx_d_0 : out STD_LOGIC;
654 rx_d_1 : in STD_LOGIC;
655 tx_d_1 : out STD_LOGIC;
656 rx_d_2 : in STD_LOGIC;
657 tx_d_2 : out STD_LOGIC;
658 rx_d_3 : in STD_LOGIC;
659 tx_d_3 : out STD_LOGIC;
660 enable_ID_sending : in std_logic;
661 TIM_source : in std_logic;
662 LP_settings : in std_logic_vector(3 downto 0);
663 trigger_ID_ready : in std_logic;
664 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
665 trigger_ID_read : out std_logic
666 );
667 end component;
668
669 component ethernet_modul
670 port(
671 wiz_reset : OUT std_logic := '1';
672 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
673 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
674 wiz_cs : OUT std_logic := '1';
675 wiz_wr : OUT std_logic := '1';
676 wiz_rd : OUT std_logic := '1';
677 wiz_int : IN std_logic ;
678 clk : IN std_logic ;
679 sd_ready : OUT std_logic ;
680 sd_busy : OUT std_logic ;
681 led : OUT std_logic_vector (7 DOWNTO 0);
682 sd_read_ftu : IN std_logic ;
683 sd_started_ftu : OUT std_logic := '0';
684 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
685 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
686 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
687 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
688 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
689 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
690 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
691 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
692 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
693 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
694 dead_time : OUT std_logic_vector (15 DOWNTO 0);
695 general_settings : OUT std_logic_vector (15 DOWNTO 0);
696 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
697 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
698 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
699 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
700 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
701 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
702 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
703 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
704 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
705 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
706 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
707 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
708 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
709 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
710 new_config : OUT std_logic := '0';
711 config_started : IN std_logic ;
712 config_start_eth : IN std_logic ;
713 config_started_eth : OUT std_logic := '0';
714 config_ready_eth : OUT std_logic := '0';
715 config_started_ack : OUT std_logic := '0';
716 fl_busy : OUT std_logic ;
717 fl_ready : OUT std_logic ;
718 fl_write_ftu : IN std_logic ;
719 fl_started_ftu : OUT std_logic := '0';
720 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
721 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
722 ping_ftu_start : OUT std_logic := '0';
723 ping_ftu_started : IN std_logic ;
724 ping_ftu_ready : IN std_logic ;
725 dd_write_ftu : IN std_logic ;
726 dd_started_ftu : OUT std_logic := '0';
727 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
728 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
729 dd_busy : OUT std_logic ;
730 dd_ready : OUT std_logic ;
731 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
732 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
733 --new stuff
734 dd_block_ready_ftu : IN std_logic;
735 dd_block_start_ack_ftu : OUT std_logic := '0';
736 dd_block_start_ftu : IN std_logic;
737 dd_send : IN std_logic;
738 dd_send_ack : OUT std_logic := '1';
739 dd_send_ready : OUT std_logic := '1';
740 --very new stuff
741 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
742 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
743 ftu_error_send : IN std_logic;
744 ftu_error_send_ack : OUT std_logic := '1';
745 ftu_error_send_ready : OUT std_logic := '1';
746 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
747 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
748 trigger_counter_read : OUT std_logic := '0';
749 trigger_counter_valid : IN std_logic;
750 --newest stuff
751 board_id : IN std_logic_vector (63 DOWNTO 0);
752 get_ts_counter : OUT std_logic := '0';
753 get_ts_counter_ready : IN std_logic;
754 get_ts_counter_started : IN std_logic;
755 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
756 get_ot_counter : OUT std_logic := '0';
757 get_ot_counter_ready : IN std_logic;
758 get_ot_counter_started : IN std_logic;
759 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
760 temp_sensor_array : IN sensor_array_type;
761 temp_sensor_ready : IN std_logic;
762 crate_reset : OUT std_logic := '0';
763 crate_reset_ack : IN std_logic;
764 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
765 start_run : OUT std_logic := '0';
766 start_run_ack : IN std_logic;
767 stop_run : OUT std_logic := '0';
768 stop_run_ack : IN std_logic;
769 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
770 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
771 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0')
772 );
773 end component;
774
775-- component counter_dummy IS
776-- PORT(
777-- clk : IN std_logic;
778-- get_counter : IN std_logic;
779-- get_counter_started : OUT std_logic := '0';
780-- get_counter_ready : OUT std_logic := '0';
781-- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
782-- );
783-- end component;
784
785 component Timing_counter is
786 port(
787 clk : in STD_LOGIC; -- 50 MHz system clock
788 enable : in STD_LOGIC; -- enable counter
789 reset : in Std_LOGIC; -- reset counter
790 read_counter : in STD_LOGIC; -- read counter
791 reading_started : out STD_LOGIC;
792 reading_valid : out STD_LOGIC; -- counter reading at output ready
793 counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0)
794 );
795 end component;
796
797 component Lightpulser_interface_Basic is
798 port(
799 clk_50 : IN STD_LOGIC;
800 --clk_250 : IN STD_LOGIC;
801 Cal_0_p : out STD_LOGIC := '0';
802 Cal_0_n : out STD_LOGIC := '1';
803 Cal_1_p : out STD_LOGIC := '0';
804 Cal_1_n : out STD_LOGIC := '1';
805 Cal_2_p : out STD_LOGIC := '0';
806 Cal_2_n : out STD_LOGIC := '1';
807 Cal_3_p : out STD_LOGIC := '0';
808 Cal_3_n : out STD_LOGIC := '1';
809 Cal_4_p : out STD_LOGIC := '0';
810 Cal_4_n : out STD_LOGIC := '1';
811 Cal_5_p : out STD_LOGIC := '0';
812 Cal_5_n : out STD_LOGIC := '1';
813 Cal_6_p : out STD_LOGIC := '0';
814 Cal_6_n : out STD_LOGIC := '1';
815 Cal_7_p : out STD_LOGIC := '0';
816 Cal_7_n : out STD_LOGIC := '1';
817 LP1_ampl : in std_logic_vector (15 downto 0);
818 LP2_ampl : in std_logic_vector (15 downto 0);
819 --LP1_delay : in std_logic_vector (15 downto 0);
820 --LP2_delay : in std_logic_vector (15 downto 0);
821 LP1_pulse : in std_logic;
822 LP2_pulse : in std_logic;
823 start_config : in std_logic;
824 config_started : out std_logic := '0';
825 config_done : out std_logic := '0'
826 );
827 end component;
828
829begin
830
831-- -- IBUFG: Single-ended global clock input buffer
832-- -- Spartan-3A
833-- -- Xilinx HDL Language Template, version 11.4
834
835-- IBUFG_inst : IBUFG
836-- generic map (
837-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
838-- -- "0"-"16"
839-- IOSTANDARD => "DEFAULT")
840-- port map (
841-- O => clk_buf_sig, -- Clock buffer output
842-- I => clk -- Clock buffer input (connect directly to top-level port)
843-- );
844
845-- Inst_FTM_clk_gen : FTM_clk_gen
846-- port map(
847-- clk => clk_buf_sig,
848-- rst => reset_sig,
849-- clk_1 => clk_1M_sig,
850-- clk_50 => clk_50M_sig,
851-- clk_250 => clk_250M_sig,
852-- clk_250_ps => clk_250M_ps_sig,
853-- ready => clk_ready_sig
854-- );
855
856 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
857 port map(
858 clk => clk,
859 rst => reset_sig,
860 clk_1 => clk_1M_sig,
861 clk_50 => clk_50M_sig,
862 clk_250 => clk_250M_sig,
863 clk_250_ps => clk_250M_ps_sig,
864 ready => clk_ready_sig
865 );
866
867 Inst_FTM_dna_gen : FTM_dna_gen
868 port map(
869 clk => clk_50M_sig,
870 start => dna_start_sig,
871 dna => dna_sig,
872 ready => dna_ready_sig
873 );
874
875 --differential output buffer for trigger signal
876 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
877 port map(
878 O => TRG_p,
879 OB => TRG_n,
880 I => trigger_signal_sig
881 );
882
883 --differential output buffer for TIM signal
884 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
885 port map(
886 O => TIM_Run_p,
887 OB => TIM_Run_n,
888 I => TIM_signal_sig
889 );
890
891 --differential output buffer for fast reset signal
892 OBUFDS_LVDS_33_RES : OBUFDS_LVDS_33
893 port map(
894 O => RES_p,
895 OB => RES_n,
896 I => '0'
897 );
898
899 Inst_trigger_manager : trigger_manager
900 port map(
901 --clocks
902 clk_50MHz => clk_50M_sig,
903 clk_250MHz => clk_250M_sig,
904 clk_250MHz_180 => clk_250M_ps_sig,
905 --trigger primitives from FTUs
906 trig_prim_0 => Trig_Prim_A, --crate 0
907 trig_prim_1 => Trig_Prim_B, --crate 1
908 trig_prim_2 => Trig_Prim_C, --crate 2
909 trig_prim_3 => Trig_Prim_D, --crate 3
910 --external signals
911 ext_trig_1 => ext_Trig(1),
912 ext_trig_2 => ext_Trig(2),
913 ext_veto => Veto,
914 FAD_busy_0 => Busy0, --crate 0
915 FAD_busy_1 => Busy1, --crate 1
916 FAD_busy_2 => Busy2, --crate 2
917 FAD_busy_3 => Busy3, --crate 3
918 --control signals from e.g. main control
919 start_run => trigger_start_sig, --enable trigger output
920 stop_run => trigger_stop_sig, --disable trigger output
921 new_config => config_trigger_sig,
922 --settings register (see FTM Firmware Specifications)
923 general_settings => general_settings_sig,
924 LP_and_PED_freq => lp_pt_freq_sig,
925 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
926 maj_coinc_n_phys => coin_n_p_sig,
927 maj_coinc_n_calib => coin_n_c_sig,
928 trigger_delay => trigger_delay_sig,
929 TIM_delay => timemarker_delay_sig,
930 dead_time => dead_time_sig,
931 coinc_window_phys => coin_win_p_sig,
932 coinc_window_calib => coin_win_c_sig,
933 active_FTU_list_0 => ftu_active_cr0_sig,
934 active_FTU_list_1 => ftu_active_cr1_sig,
935 active_FTU_list_2 => ftu_active_cr2_sig,
936 active_FTU_list_3 => ftu_active_cr3_sig,
937 --control signals or information for other entities
938 trigger_ID_read => trigger_ID_read_sig,
939 trig_cnt_copy_read => trigger_counter_read_sig,
940 trigger_ID_ready => trigger_ID_ready_sig,
941 trigger_ID => trigger_ID_sig,
942 trig_cnt_copy => trigger_counter_sig, --counter reading
943 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
944 trigger_active => trigger_active_sig, --phys triggers are enabled/active
945 config_done => config_trigger_done_sig,
946 LP1_pulse => LP1_pulse_sig, --send start signal to light pulser 1
947 LP2_pulse => LP2_pulse_sig, --send start signal to light pulser 2
948 --trigger and time marker output signals to FADs
949 trigger_signal => trigger_signal_sig,
950 TIM_signal => TIM_signal_sig
951 );
952
953 Inst_Clock_cond_interface : Clock_cond_interface
954 port map(
955 clk => clk_50M_sig,
956 CLK_Clk_Cond => CLK_Clk_Cond,
957 LE_Clk_Cond => LE_Clk_Cond,
958 DATA_Clk_Cond => DATA_Clk_Cond,
959 SYNC_Clk_Cond => SYNC_Clk_Cond,
960 LD_Clk_Cond => LD_Clk_Cond,
961 TIM_Sel => TIM_Sel,
962 cc_R0 => cc_R0_sig,
963 cc_R1 => cc_R1_sig,
964 cc_R8 => cc_R8_sig,
965 cc_R9 => cc_R9_sig,
966 cc_R11 => cc_R11_sig,
967 cc_R13 => cc_R13_sig,
968 cc_R14 => cc_R14_sig,
969 cc_R15 => cc_R15_sig,
970 start_config => config_start_cc_sig,
971 config_started => config_started_cc_sig,
972 config_done => config_ready_cc_sig,
973 timemarker_select => general_settings_sig(0)
974 );
975
976 Inst_FTM_central_control : FTM_central_control
977 port map(
978 clk => clk_50M_sig,
979 clk_ready => clk_ready_sig,
980 clk_scaler => clk_1M_sig,
981 new_config => new_config_sig,
982 config_started => config_started_sig,
983 config_started_ack => config_started_ack_sig,
984 config_start_eth => config_start_eth_sig,
985 config_started_eth => config_started_eth_sig,
986 config_ready_eth => config_ready_eth_sig,
987 config_start_ftu => config_start_ftu_sig,
988 config_started_ftu => config_started_ftu_sig,
989 config_ready_ftu => config_ready_ftu_sig,
990 ping_ftu_start => ping_ftu_start_sig,
991 ping_ftu_started => ping_ftu_started_sig,
992 ping_ftu_ready => ping_ftu_ready_sig,
993 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
994 ping_ftu_started_ftu => ping_ftu_started1_sig,
995 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
996 rates_ftu => rates_ftu_start_sig,
997 rates_started_ftu => rates_ftu_started_sig,
998 rates_ready_ftu => rates_ftu_ready_sig,
999 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
1000 dd_send => dd_send_sig,
1001 dd_send_ack => dd_send_ack_sig,
1002 dd_send_ready => dd_send_ready_sig,
1003 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1004 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1005 dd_block_start_ftu => dd_block_start_ftu_sig,
1006 config_start_cc => config_start_cc_sig,
1007 config_started_cc => config_started_cc_sig,
1008 config_ready_cc => config_ready_cc_sig,
1009 config_start_lp => config_start_lp_sig,
1010 config_started_lp => config_started_lp_sig,
1011 config_ready_lp => config_ready_lp_sig,
1012 config_trigger => config_trigger_sig,
1013 config_trigger_done => config_trigger_done_sig,
1014 dna_start => dna_start_sig,
1015 dna_ready => dna_ready_sig,
1016 crate_reset => crate_reset_sig,
1017 crate_reset_ack => crate_reset_ack_sig,
1018 crate_reset_param => crate_reset_param_sig,
1019 start_run => start_run_sig,
1020 start_run_ack => start_run_ack_sig,
1021 stop_run => stop_run_sig,
1022 stop_run_ack => stop_run_ack_sig,
1023 current_cc_state => current_cc_state_sig,
1024 cc_state_test => cc_state_test_sig,
1025 start_run_param => start_run_param_sig,
1026 start_run_num_events => start_run_num_events_sig,
1027 trigger_start => trigger_start_sig,
1028 trigger_stop => trigger_stop_sig,
1029 enable_ID_sending => enable_ID_sending_sig,
1030 reset_timer => reset_timer_sig,
1031 crate_res_0 => crate_res0_sig,
1032 crate_res_1 => crate_res1_sig,
1033 crate_res_2 => crate_res2_sig,
1034 crate_res_3 => crate_res3_sig
1035 );
1036
1037 Inst_FTM_ftu_control : FTM_ftu_control
1038 port map(
1039 clk_50MHz => clk_50M_sig,
1040 rx_en => Bus1_Rx_En,
1041 tx_en => Bus1_Tx_En,
1042 rx_d_0 => Bus1_RxD_0,
1043 tx_d_0 => Bus1_TxD_0,
1044 rx_d_1 => Bus1_RxD_1,
1045 tx_d_1 => Bus1_TxD_1,
1046 rx_d_2 => Bus1_RxD_2,
1047 tx_d_2 => Bus1_TxD_2,
1048 rx_d_3 => Bus1_RxD_3,
1049 tx_d_3 => Bus1_TxD_3,
1050 new_config => config_start_ftu_sig,
1051 ping_all => ping_ftu_start_ftu_sig,
1052 read_rates => rates_ftu_start_sig,
1053 read_rates_started => rates_ftu_started_sig,
1054 read_rates_done => rates_ftu_ready_sig,
1055 new_config_started => config_started_ftu_sig,
1056 new_config_done => config_ready_ftu_sig,
1057 ping_all_started => ping_ftu_started1_sig,
1058 ping_all_done => ping_ftu_ready1_sig,
1059 ftu_active_cr0 => ftu_active_cr0_sig,
1060 ftu_active_cr1 => ftu_active_cr1_sig,
1061 ftu_active_cr2 => ftu_active_cr2_sig,
1062 ftu_active_cr3 => ftu_active_cr3_sig,
1063 ftu_error_calls => ftu_error_calls_sig,
1064 ftu_error_data => ftu_error_data_sig,
1065 ftu_error_send => ftu_error_send_sig,
1066 ftu_error_send_ack => ftu_error_send_ack_sig,
1067 ftu_error_send_ready=> ftu_error_send_ready_sig,
1068 static_RAM_busy => sd_busy_sig,
1069 static_RAM_started => sd_started_ftu_sig,
1070 static_RAM_ready => sd_ready_sig,
1071 data_static_RAM => sd_data_out_ftu_sig,
1072 read_static_RAM => sd_read_ftu_sig,
1073 addr_static_RAM => sd_addr_ftu_sig,
1074 dynamic_RAM_busy => dd_busy_sig,
1075 dynamic_RAM_started => dd_started_ftu_sig,
1076 dynamic_RAM_ready => dd_ready_sig,
1077 data_dynamic_RAM => dd_data_sig,
1078 write_dynamic_RAM => dd_write_sig,
1079 addr_dynamic_RAM => dd_addr_sig,
1080 FTUlist_RAM_busy => fl_busy_sig,
1081 FTUlist_RAM_started => fl_started_ftu_sig,
1082 FTUlist_RAM_ready => fl_ready_sig,
1083 data_FTUlist_RAM => fl_data_sig,
1084 write_FTUlist_RAM => fl_write_sig,
1085 addr_FTUlist_RAM => fl_addr_sig
1086 );
1087
1088 Inst_FTM_fad_broadcast : FTM_fad_broadcast
1089 port map(
1090 clk_50MHz => clk_50M_sig,
1091 rx_en => Bus2_Rx_En,
1092 tx_en => Bus2_Tx_En,
1093 rx_d_0 => Bus2_RxD_0,
1094 tx_d_0 => Bus2_TxD_0,
1095 rx_d_1 => Bus2_RxD_1,
1096 tx_d_1 => Bus2_TxD_1,
1097 rx_d_2 => Bus2_RxD_2,
1098 tx_d_2 => Bus2_TxD_2,
1099 rx_d_3 => Bus2_RxD_3,
1100 tx_d_3 => Bus2_TxD_3,
1101 enable_ID_sending => enable_ID_sending_sig,
1102 TIM_source => general_settings_sig(0),
1103 LP_settings => "0000",
1104 trigger_ID_ready => trigger_ID_ready_sig,
1105 trigger_ID => trigger_ID_sig,
1106 trigger_ID_read => trigger_ID_read_sig
1107 );
1108
1109 Inst_ethernet_modul : ethernet_modul
1110 port map(
1111 wiz_reset => W_RES,
1112 wiz_addr => W_A,
1113 wiz_data => W_D,
1114 wiz_cs => W_CS,
1115 wiz_wr => W_WR,
1116 wiz_rd => W_RD,
1117 wiz_int => W_INT,
1118 clk => clk_50M_sig,
1119 sd_ready => sd_ready_sig,
1120 sd_busy => sd_busy_sig,
1121 led => led_sig,
1122 sd_read_ftu => sd_read_ftu_sig,
1123 sd_started_ftu => sd_started_ftu_sig,
1124 cc_R0 => cc_R0_sig,
1125 cc_R1 => cc_R1_sig,
1126 cc_R11 => cc_R11_sig,
1127 cc_R13 => cc_R13_sig,
1128 cc_R14 => cc_R14_sig,
1129 cc_R15 => cc_R15_sig,
1130 cc_R8 => cc_R8_sig,
1131 cc_R9 => cc_R9_sig,
1132 coin_n_c => coin_n_c_sig,
1133 coin_n_p => coin_n_p_sig,
1134 dead_time => dead_time_sig,
1135 general_settings => general_settings_sig,
1136 lp1_amplitude => lp1_amplitude_sig,
1137 lp1_delay => lp1_delay_sig,
1138 lp2_amplitude => lp2_amplitude_sig,
1139 lp2_delay => lp2_delay_sig,
1140 lp_pt_freq => lp_pt_freq_sig,
1141 lp_pt_ratio => lp_pt_ratio_sig,
1142 timemarker_delay => timemarker_delay_sig,
1143 trigger_delay => trigger_delay_sig,
1144 sd_addr_ftu => sd_addr_ftu_sig,
1145 sd_data_out_ftu => sd_data_out_ftu_sig,
1146 ftu_active_cr0 => ftu_active_cr0_sig,
1147 ftu_active_cr1 => ftu_active_cr1_sig,
1148 ftu_active_cr2 => ftu_active_cr2_sig,
1149 ftu_active_cr3 => ftu_active_cr3_sig,
1150 new_config => new_config_sig,
1151 config_started => config_started_sig,
1152 config_start_eth => config_start_eth_sig,
1153 config_started_eth => config_started_eth_sig,
1154 config_ready_eth => config_ready_eth_sig,
1155 config_started_ack => config_started_ack_sig,
1156 fl_busy => fl_busy_sig,
1157 fl_ready => fl_ready_sig,
1158 fl_write_ftu => fl_write_sig,
1159 fl_started_ftu => fl_started_ftu_sig,
1160 fl_addr_ftu => fl_addr_sig,
1161 fl_data_in_ftu => fl_data_sig,
1162 ping_ftu_start => ping_ftu_start_sig,
1163 ping_ftu_started => ping_ftu_started_sig,
1164 ping_ftu_ready => ping_ftu_ready_sig,
1165 dd_write_ftu => dd_write_sig,
1166 dd_started_ftu => dd_started_ftu_sig,
1167 dd_data_in_ftu => dd_data_sig,
1168 dd_addr_ftu => dd_addr_sig,
1169 dd_busy => dd_busy_sig,
1170 dd_ready => dd_ready_sig,
1171 coin_win_c => coin_win_c_sig,
1172 coin_win_p => coin_win_p_sig,
1173 --new stuff
1174 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1175 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1176 dd_block_start_ftu => dd_block_start_ftu_sig,
1177 dd_send => dd_send_sig,
1178 dd_send_ack => dd_send_ack_sig,
1179 dd_send_ready => dd_send_ready_sig,
1180 --very new stuff
1181 ftu_error_calls => ftu_error_calls_sig,
1182 ftu_error_data => ftu_error_data_sig,
1183 ftu_error_send => ftu_error_send_sig,
1184 ftu_error_send_ack => ftu_error_send_ack_sig,
1185 ftu_error_send_ready => ftu_error_send_ready_sig,
1186 prescaling_FTU01 => prescaling_FTU01_sig,
1187 trigger_counter => trigger_counter_sig,
1188 trigger_counter_read => trigger_counter_read_sig,
1189 trigger_counter_valid => trigger_counter_valid_sig,
1190 --newest stuff
1191 board_id => dna_sig,
1192 get_ts_counter => get_ts_counter_sig,
1193 get_ts_counter_ready => get_ts_counter_ready_sig,
1194 get_ts_counter_started => get_ts_counter_started_sig,
1195 timestamp_counter => timestamp_counter_sig,
1196 get_ot_counter => get_ot_counter_sig,
1197 get_ot_counter_ready => get_ot_counter_ready_sig,
1198 get_ot_counter_started => get_ot_counter_started_sig,
1199 on_time_counter => on_time_counter_sig,
1200 temp_sensor_array => (35, 45, 55, 65),
1201 temp_sensor_ready => '1',
1202 crate_reset => crate_reset_sig,
1203 crate_reset_ack => crate_reset_ack_sig,
1204 crate_reset_param => crate_reset_param_sig,
1205 start_run => start_run_sig,
1206 start_run_ack => start_run_ack_sig,
1207 stop_run => stop_run_sig,
1208 stop_run_ack => stop_run_ack_sig,
1209 current_cc_state => current_cc_state_sig,
1210 start_run_param => start_run_param_sig,
1211 start_run_num_events => start_run_num_events_sig
1212 );
1213
1214-- Inst_counter_dummy_ts : counter_dummy
1215-- port map(
1216-- clk => clk_50M_sig,
1217-- get_counter => get_ts_counter_sig,
1218-- get_counter_started => get_ts_counter_started_sig,
1219-- get_counter_ready => get_ts_counter_ready_sig,
1220-- counter => timestamp_counter_sig
1221-- );
1222
1223-- Inst_counter_dummy_ot : counter_dummy
1224-- port map(
1225-- clk => clk_50M_sig,
1226-- get_counter => get_ot_counter_sig,
1227-- get_counter_started => get_ot_counter_started_sig,
1228-- get_counter_ready => get_ot_counter_ready_sig,
1229-- counter => on_time_counter_sig
1230-- );
1231
1232 Inst_Timing_counter_ts : Timing_counter
1233 port map(
1234 clk => clk_50M_sig,
1235 enable => '1',
1236 reset => reset_timer_sig,
1237 read_counter => get_ts_counter_sig,
1238 reading_started => get_ts_counter_started_sig,
1239 reading_valid => get_ts_counter_ready_sig,
1240 counter_reading => timestamp_counter_sig
1241 );
1242
1243 Inst_Timing_counter_ot : Timing_counter
1244 port map(
1245 clk => clk_50M_sig,
1246 enable => trigger_active_sig,
1247 reset => reset_timer_sig,
1248 read_counter => get_ot_counter_sig,
1249 reading_started => get_ot_counter_started_sig,
1250 reading_valid => get_ot_counter_ready_sig,
1251 counter_reading => on_time_counter_sig
1252 );
1253
1254 Inst_Lightpulser_interface_Basic : Lightpulser_interface_Basic
1255 port map (
1256 clk_50 => clk_50M_sig,
1257 --clk_250 => clk_250M_sig,
1258 Cal_0_p => Cal_2_p, --swapped with Cal_2_p due to connector on FLD board
1259 Cal_0_n => Cal_2_n, --swapped with Cal_2_n due to connector on FLD board
1260 Cal_1_p => Cal_1_p,
1261 Cal_1_n => Cal_1_n,
1262 Cal_2_p => Cal_0_p, --swapped with Cal_0_p due to connector on FLD board
1263 Cal_2_n => Cal_0_n, --swapped with Cal_0_n due to connector on FLD board
1264 Cal_3_p => Cal_3_p,
1265 Cal_3_n => Cal_3_n,
1266 Cal_4_p => Cal_6_p, --swapped with Cal_6_p due to connector on FLD board
1267 Cal_4_n => Cal_6_n, --swapped with Cal_6_n due to connector on FLD board
1268 Cal_5_p => Cal_5_p,
1269 Cal_5_n => Cal_5_n,
1270 Cal_6_p => Cal_4_p, --swapped with Cal_4_p due to connector on FLD board
1271 Cal_6_n => Cal_4_n, --swapped with Cal_4_n due to connector on FLD board
1272 Cal_7_p => Cal_7_p,
1273 Cal_7_n => Cal_7_n,
1274 LP1_ampl => lp1_amplitude_sig,
1275 LP2_ampl => lp2_amplitude_sig,
1276 --LP1_delay => lp1_delay_sig,
1277 --LP2_delay => lp2_delay_sig,
1278 LP1_pulse => LP1_pulse_sig,
1279 LP2_pulse => LP2_pulse_sig,
1280 start_config => config_start_lp_sig,
1281 config_started => config_started_lp_sig,
1282 config_done => config_ready_lp_sig
1283 );
1284
1285 LED_red <= led_sig(3 downto 0);
1286 LED_ye <= led_sig(5 downto 4);
1287 LED_gn <= led_sig(7 downto 6);
1288
1289 TP(32 downto 8) <= (others => '0');
1290 --TP(8) <= clk_50M_sig;
1291 TP( 7 downto 0) <= cc_state_test_sig;
1292
1293 Crate_Res0 <= crate_res0_sig;
1294 Crate_Res1 <= crate_res1_sig;
1295 Crate_Res2 <= crate_res2_sig;
1296 Crate_Res3 <= crate_res3_sig;
1297
1298end Behavioral;
1299
1300
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