source: firmware/FTM/FTM_top.vhd@ 11547

Last change on this file since 11547 was 11485, checked in by weitzel, 13 years ago
FTM firmware features now the config_single_FTU command (to be tested); also some defaults were changed
File size: 56.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 Bus2_TxD_0 : out STD_LOGIC;
153
154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 Bus2_TxD_1 : out STD_LOGIC;
156
157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 Bus2_TxD_2 : out STD_LOGIC;
159
160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 Crate_Res0 : out STD_LOGIC;
180 Crate_Res1 : out STD_LOGIC;
181 Crate_Res2 : out STD_LOGIC;
182 Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 RES_p : out STD_LOGIC; -- RES+ Reset
215 RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 Cal_0_p : out STD_LOGIC;
233 Cal_0_n : out STD_LOGIC;
234 Cal_1_p : out STD_LOGIC;
235 Cal_1_n : out STD_LOGIC;
236 Cal_2_p : out STD_LOGIC;
237 Cal_2_n : out STD_LOGIC;
238 Cal_3_p : out STD_LOGIC;
239 Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 Cal_4_p : out STD_LOGIC;
244 Cal_4_n : out STD_LOGIC;
245 Cal_5_p : out STD_LOGIC;
246 Cal_5_n : out STD_LOGIC;
247 Cal_6_p : out STD_LOGIC;
248 Cal_6_n : out STD_LOGIC;
249 Cal_7_p : out STD_LOGIC;
250 Cal_7_n : out STD_LOGIC;
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 TP : inout STD_LOGIC_VECTOR(32 downto 0)
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_ftu_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_ftu_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic; -- initialized in central control
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352
353 signal config_start_lp_sig : std_logic; -- initialized in central control
354 signal config_started_lp_sig : std_logic; -- initialized in light pulser interface
355 signal config_ready_lp_sig : std_logic; -- initialized in light pulser interface
356
357 signal config_trigger_sig : std_logic;
358 signal config_trigger_done_sig : std_logic;
359
360 signal clk_buf_sig : std_logic;
361 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
362 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
363 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
364 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
365 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
366
367 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager
368 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager
369 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast
370
371 signal trigger_active_sig : std_logic; -- initialized in trigger manager
372
373 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
374
375 signal trigger_signal_sig : std_logic := '0';
376 signal TIM_signal_sig : std_logic := '0';
377
378 --signals for FPGA DNA identifier
379 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen
380 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control
381 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen
382
383 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
384
385 signal get_ot_counter_sig : std_logic;
386 signal get_ot_counter_started_sig : std_logic;
387 signal get_ot_counter_ready_sig : std_logic;
388 signal on_time_counter_sig : std_logic_vector(47 downto 0);
389
390 signal get_ts_counter_sig : std_logic;
391 signal get_ts_counter_started_sig : std_logic;
392 signal get_ts_counter_ready_sig : std_logic;
393 signal timestamp_counter_sig : std_logic_vector(47 downto 0);
394
395 signal crate_reset_sig : std_logic;
396 signal crate_reset_ack_sig : std_logic;
397 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0);
398 signal start_run_sig : std_logic;
399 signal start_run_ack_sig : std_logic;
400 signal stop_run_sig : std_logic;
401 signal stop_run_ack_sig : std_logic;
402 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0);
403 signal cc_state_test_sig : std_logic_vector ( 7 downto 0);
404 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0);
405 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0);
406
407 signal trigger_start_sig : std_logic;
408 signal trigger_stop_sig : std_logic;
409
410 signal enable_ID_sending_sig : std_logic;
411 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control
412
413 signal crate_res0_sig : std_logic; -- initialized in FTM_central_control
414 signal crate_res1_sig : std_logic; -- initialized in FTM_central_control
415 signal crate_res2_sig : std_logic; -- initialized in FTM_central_control
416 signal crate_res3_sig : std_logic; -- initialized in FTM_central_control
417
418 signal LP1_pulse_sig : std_logic := '0';
419 signal LP2_pulse_sig : std_logic := '0';
420
421 signal new_config_ftu_sig : std_logic; -- initialized in ethernet_modul
422 signal new_config_ftu_ack_sig : std_logic; -- initialized in FTM_central_control
423 signal new_config_ftu_param_sig : std_logic_vector (15 DOWNTO 0); -- initialized in ethernet_modul
424
425 signal config_single_FTU_sig : std_logic; -- initialized in FTM_central_control
426 signal config_single_FTU_started_sig : std_logic; -- initialized in FTM_ftu_control
427 signal config_single_FTU_done_sig : std_logic; -- initialized in FTM_ftu_control
428
429-- component FTM_clk_gen
430-- port(
431-- clk : IN STD_LOGIC;
432-- rst : IN STD_LOGIC;
433-- clk_1 : OUT STD_LOGIC;
434-- clk_50 : OUT STD_LOGIC;
435-- clk_250 : OUT STD_LOGIC;
436-- clk_250_ps : OUT STD_LOGIC;
437-- ready : OUT STD_LOGIC
438-- );
439-- end component;
440
441 component FTM_clk_gen_2
442 port(
443 clk : IN STD_LOGIC;
444 rst : IN STD_LOGIC;
445 clk_1 : OUT STD_LOGIC;
446 clk_50 : OUT STD_LOGIC;
447 clk_250 : OUT STD_LOGIC;
448 clk_250_ps : OUT STD_LOGIC;
449 ready : OUT STD_LOGIC
450 );
451 end component;
452
453 component FTM_dna_gen
454 port(
455 clk : IN STD_LOGIC;
456 start : IN STD_LOGIC;
457 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
458 ready : OUT STD_LOGIC
459 );
460 end component;
461
462 component trigger_manager
463 port(
464 --clocks
465 clk_50MHz : in std_logic;
466 clk_250MHz : in std_logic;
467 clk_250MHz_180 : in std_logic;
468 --trigger primitives from FTUs
469 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
470 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
471 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
472 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
473 --external signals
474 ext_trig_1 : in std_logic;
475 ext_trig_2 : in std_logic;
476 ext_veto : in std_logic;
477 FAD_busy_0 : in std_logic; --crate 0
478 FAD_busy_1 : in std_logic; --crate 1
479 FAD_busy_2 : in std_logic; --crate 2
480 FAD_busy_3 : in std_logic; --crate 3
481 --control signals from e.g. main control
482 start_run : in std_logic; --enable trigger output
483 stop_run : in std_logic; --disable trigger output
484 new_config : in std_logic;
485 --settings register (see FTM Firmware Specifications)
486 general_settings : in std_logic_vector(15 downto 0);
487 LP_and_PED_freq : in std_logic_vector(15 downto 0);
488 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
489 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
490 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
491 trigger_delay : in std_logic_vector(15 downto 0);
492 TIM_delay : in std_logic_vector(15 downto 0);
493 dead_time : in std_logic_vector(15 downto 0);
494 coinc_window_phys : in std_logic_vector(15 downto 0);
495 coinc_window_calib : in std_logic_vector(15 downto 0);
496 active_FTU_list_0 : in std_logic_vector(15 downto 0);
497 active_FTU_list_1 : in std_logic_vector(15 downto 0);
498 active_FTU_list_2 : in std_logic_vector(15 downto 0);
499 active_FTU_list_3 : in std_logic_vector(15 downto 0);
500 --control signals or information for other entities
501 trigger_ID_read : in std_logic;
502 trig_cnt_copy_read : in std_logic;
503 trigger_ID_ready : out std_logic;
504 trigger_ID : out std_logic_vector(55 downto 0);
505 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
506 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
507 trigger_active : out std_logic; --phys triggers are enabled/active
508 config_done : out std_logic;
509 LP1_pulse : out std_logic; --send start signal to light pulser 1
510 LP2_pulse : out std_logic; --send start signal to light pulser 2
511 --trigger and time marker output signals to FADs
512 trigger_signal : out std_logic;
513 TIM_signal : out std_logic
514 );
515 end component;
516
517 component Clock_cond_interface is
518 port(
519 clk : IN STD_LOGIC;
520 CLK_Clk_Cond : out STD_LOGIC;
521 LE_Clk_Cond : out STD_LOGIC;
522 DATA_Clk_Cond : out STD_LOGIC;
523 SYNC_Clk_Cond : out STD_LOGIC;
524 LD_Clk_Cond : in STD_LOGIC;
525 TIM_Sel : out STD_LOGIC;
526 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
527 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
528 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
529 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
530 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
531 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
532 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
533 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
534 start_config : in STD_LOGIC;
535 config_started : out STD_LOGIC;
536 config_done : out STD_LOGIC;
537 timemarker_select: in STD_LOGIC
538 );
539 end component;
540
541 component FTM_central_control
542 port(
543 clk : IN std_logic;
544 clk_ready : in std_logic;
545 clk_scaler : IN std_logic;
546 new_config : IN std_logic;
547 config_started : OUT std_logic := '0';
548 config_started_ack : IN std_logic;
549 config_start_eth : OUT std_logic := '0';
550 config_started_eth : IN std_logic;
551 config_ready_eth : IN std_logic;
552 config_start_ftu : OUT std_logic := '0';
553 config_started_ftu : IN std_logic;
554 config_ready_ftu : IN std_logic;
555 ping_ftu_start : IN std_logic;
556 ping_ftu_started : OUT std_logic := '0';
557 ping_ftu_ready : OUT std_logic := '0';
558 ping_ftu_start_ftu : OUT std_logic := '0';
559 ping_ftu_started_ftu : IN std_logic;
560 ping_ftu_ready_ftu : IN std_logic;
561 rates_ftu : OUT std_logic := '0';
562 rates_started_ftu : IN std_logic;
563 rates_ready_ftu : IN std_logic;
564 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
565 dd_send : OUT std_logic := '0';
566 dd_send_ack : IN std_logic;
567 dd_send_ready : IN std_logic;
568 dd_block_ready_ftu : out std_logic := '0';
569 dd_block_start_ack_ftu : in std_logic;
570 dd_block_start_ftu : out std_logic := '0';
571 config_start_cc : out std_logic := '0';
572 config_started_cc : in std_logic;
573 config_ready_cc : in std_logic;
574 config_start_lp : out std_logic := '0';
575 config_started_lp : in std_logic;
576 config_ready_lp : in std_logic;
577 config_trigger : out std_logic;
578 config_trigger_done : in std_logic;
579 dna_start : out std_logic;
580 dna_ready : in std_logic;
581 crate_reset : IN std_logic;
582 crate_reset_ack : OUT std_logic;
583 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
584 start_run : IN std_logic;
585 start_run_ack : OUT std_logic;
586 stop_run : IN std_logic;
587 stop_run_ack : OUT std_logic;
588 current_cc_state : OUT std_logic_vector (15 DOWNTO 0);
589 cc_state_test : OUT std_logic_vector ( 7 downto 0);
590 start_run_param : IN std_logic_vector (15 DOWNTO 0);
591 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
592 trigger_start : out std_logic;
593 trigger_stop : out std_logic;
594 enable_ID_sending : out std_logic;
595 reset_timer : out std_logic;
596 crate_res_0 : out std_logic;
597 crate_res_1 : out std_logic;
598 crate_res_2 : out std_logic;
599 crate_res_3 : out std_logic;
600 new_config_ftu : in std_logic;
601 new_config_ftu_ack : out std_logic := '0';
602 config_single_FTU : out std_logic := '0';
603 config_single_FTU_started : in std_logic;
604 config_single_FTU_done : in std_logic
605 );
606 end component;
607
608 component FTM_ftu_control
609 port(
610 clk_50MHz : in std_logic;
611 rx_en : out STD_LOGIC;
612 tx_en : out STD_LOGIC;
613 rx_d_0 : in STD_LOGIC;
614 tx_d_0 : out STD_LOGIC;
615 rx_d_1 : in STD_LOGIC;
616 tx_d_1 : out STD_LOGIC;
617 rx_d_2 : in STD_LOGIC;
618 tx_d_2 : out STD_LOGIC;
619 rx_d_3 : in STD_LOGIC;
620 tx_d_3 : out STD_LOGIC;
621 new_config : in std_logic;
622 ping_all : in std_logic;
623 read_rates : in std_logic;
624 config_single_FTU : in std_logic;
625 read_rates_started : out std_logic := '0';
626 read_rates_done : out std_logic := '0';
627 new_config_started : out std_logic := '0';
628 new_config_done : out std_logic := '0';
629 ping_all_started : out std_logic := '0';
630 ping_all_done : out std_logic := '0';
631 config_single_FTU_started : out std_logic := '0';
632 config_single_FTU_done : out std_logic := '0';
633 ftu_active_cr0 : in std_logic_vector (15 downto 0);
634 ftu_active_cr1 : in std_logic_vector (15 downto 0);
635 ftu_active_cr2 : in std_logic_vector (15 downto 0);
636 ftu_active_cr3 : in std_logic_vector (15 downto 0);
637 config_single_FTU_param : in std_logic_vector (15 DOWNTO 0);
638 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
639 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
640 ftu_error_send : out std_logic := '0';
641 ftu_error_send_ack : in std_logic;
642 ftu_error_send_ready : in std_logic;
643 static_RAM_busy : in std_logic;
644 static_RAM_started : in std_logic;
645 static_RAM_ready : in std_logic;
646 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
647 read_static_RAM : out std_logic := '0';
648 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
649 dynamic_RAM_busy : in std_logic;
650 dynamic_RAM_started : in std_logic;
651 dynamic_RAM_ready : in std_logic;
652 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
653 write_dynamic_RAM : out std_logic := '0';
654 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
655 FTUlist_RAM_busy : in std_logic;
656 FTUlist_RAM_started : in std_logic;
657 FTUlist_RAM_ready : in std_logic;
658 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
659 write_FTUlist_RAM : out std_logic := '0';
660 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
661 );
662 end component;
663
664 component FTM_fad_broadcast
665 port(
666 clk_50MHz : in std_logic;
667 rx_en : out STD_LOGIC;
668 tx_en : out STD_LOGIC;
669 rx_d_0 : in STD_LOGIC;
670 tx_d_0 : out STD_LOGIC;
671 rx_d_1 : in STD_LOGIC;
672 tx_d_1 : out STD_LOGIC;
673 rx_d_2 : in STD_LOGIC;
674 tx_d_2 : out STD_LOGIC;
675 rx_d_3 : in STD_LOGIC;
676 tx_d_3 : out STD_LOGIC;
677 enable_ID_sending : in std_logic;
678 TIM_source : in std_logic;
679 LP_settings : in std_logic_vector(3 downto 0);
680 trigger_ID_ready : in std_logic;
681 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
682 trigger_ID_read : out std_logic
683 );
684 end component;
685
686 component ethernet_modul
687 port(
688 wiz_reset : OUT std_logic := '1';
689 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
690 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
691 wiz_cs : OUT std_logic := '1';
692 wiz_wr : OUT std_logic := '1';
693 wiz_rd : OUT std_logic := '1';
694 wiz_int : IN std_logic ;
695 clk : IN std_logic ;
696 sd_ready : OUT std_logic ;
697 sd_busy : OUT std_logic ;
698 led : OUT std_logic_vector (7 DOWNTO 0);
699 sd_read_ftu : IN std_logic ;
700 sd_started_ftu : OUT std_logic := '0';
701 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
702 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
703 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
704 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
705 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
706 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
707 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
708 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
709 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
710 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
711 dead_time : OUT std_logic_vector (15 DOWNTO 0);
712 general_settings : OUT std_logic_vector (15 DOWNTO 0);
713 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
714 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
715 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
716 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
717 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
718 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
719 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
720 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
721 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
722 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
723 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
724 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
725 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
726 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
727 new_config : OUT std_logic := '0';
728 config_started : IN std_logic ;
729 config_start_eth : IN std_logic ;
730 config_started_eth : OUT std_logic := '0';
731 config_ready_eth : OUT std_logic := '0';
732 config_started_ack : OUT std_logic := '0';
733 fl_busy : OUT std_logic ;
734 fl_ready : OUT std_logic ;
735 fl_write_ftu : IN std_logic ;
736 fl_started_ftu : OUT std_logic := '0';
737 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
738 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
739 ping_ftu_start : OUT std_logic := '0';
740 ping_ftu_started : IN std_logic ;
741 ping_ftu_ready : IN std_logic ;
742 dd_write_ftu : IN std_logic ;
743 dd_started_ftu : OUT std_logic := '0';
744 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
745 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
746 dd_busy : OUT std_logic ;
747 dd_ready : OUT std_logic ;
748 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
749 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
750 --new stuff
751 dd_block_ready_ftu : IN std_logic;
752 dd_block_start_ack_ftu : OUT std_logic := '0';
753 dd_block_start_ftu : IN std_logic;
754 dd_send : IN std_logic;
755 dd_send_ack : OUT std_logic := '1';
756 dd_send_ready : OUT std_logic := '1';
757 --very new stuff
758 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
759 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
760 ftu_error_send : IN std_logic;
761 ftu_error_send_ack : OUT std_logic := '1';
762 ftu_error_send_ready : OUT std_logic := '1';
763 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
764 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
765 trigger_counter_read : OUT std_logic := '0';
766 trigger_counter_valid : IN std_logic;
767 --newest stuff
768 board_id : IN std_logic_vector (63 DOWNTO 0);
769 get_ts_counter : OUT std_logic := '0';
770 get_ts_counter_ready : IN std_logic;
771 get_ts_counter_started : IN std_logic;
772 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
773 get_ot_counter : OUT std_logic := '0';
774 get_ot_counter_ready : IN std_logic;
775 get_ot_counter_started : IN std_logic;
776 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
777 temp_sensor_array : IN sensor_array_type;
778 temp_sensor_ready : IN std_logic;
779 crate_reset : OUT std_logic := '0';
780 crate_reset_ack : IN std_logic;
781 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
782 start_run : OUT std_logic := '0';
783 start_run_ack : IN std_logic;
784 stop_run : OUT std_logic := '0';
785 stop_run_ack : IN std_logic;
786 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
787 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
788 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
789 new_config_ftu : OUT std_logic := '0';
790 new_config_ftu_ack : IN std_logic;
791 new_config_ftu_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
792 );
793 end component;
794
795-- component counter_dummy IS
796-- PORT(
797-- clk : IN std_logic;
798-- get_counter : IN std_logic;
799-- get_counter_started : OUT std_logic := '0';
800-- get_counter_ready : OUT std_logic := '0';
801-- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
802-- );
803-- end component;
804
805 component Timing_counter is
806 port(
807 clk : in STD_LOGIC; -- 50 MHz system clock
808 enable : in STD_LOGIC; -- enable counter
809 reset : in Std_LOGIC; -- reset counter
810 read_counter : in STD_LOGIC; -- read counter
811 reading_started : out STD_LOGIC;
812 reading_valid : out STD_LOGIC; -- counter reading at output ready
813 counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0)
814 );
815 end component;
816
817 component Lightpulser_interface_Basic is
818 port(
819 clk_50 : IN STD_LOGIC;
820 --clk_250 : IN STD_LOGIC;
821 Cal_0_p : out STD_LOGIC := '0';
822 Cal_0_n : out STD_LOGIC := '1';
823 Cal_1_p : out STD_LOGIC := '0';
824 Cal_1_n : out STD_LOGIC := '1';
825 Cal_2_p : out STD_LOGIC := '0';
826 Cal_2_n : out STD_LOGIC := '1';
827 Cal_3_p : out STD_LOGIC := '0';
828 Cal_3_n : out STD_LOGIC := '1';
829 Cal_4_p : out STD_LOGIC := '0';
830 Cal_4_n : out STD_LOGIC := '1';
831 Cal_5_p : out STD_LOGIC := '0';
832 Cal_5_n : out STD_LOGIC := '1';
833 Cal_6_p : out STD_LOGIC := '0';
834 Cal_6_n : out STD_LOGIC := '1';
835 Cal_7_p : out STD_LOGIC := '0';
836 Cal_7_n : out STD_LOGIC := '1';
837 LP1_ampl : in std_logic_vector (15 downto 0);
838 LP2_ampl : in std_logic_vector (15 downto 0);
839 --LP1_delay : in std_logic_vector (15 downto 0);
840 --LP2_delay : in std_logic_vector (15 downto 0);
841 LP1_pulse : in std_logic;
842 LP2_pulse : in std_logic;
843 start_config : in std_logic;
844 config_started : out std_logic := '0';
845 config_done : out std_logic := '0'
846 );
847 end component;
848
849begin
850
851-- -- IBUFG: Single-ended global clock input buffer
852-- -- Spartan-3A
853-- -- Xilinx HDL Language Template, version 11.4
854
855-- IBUFG_inst : IBUFG
856-- generic map (
857-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
858-- -- "0"-"16"
859-- IOSTANDARD => "DEFAULT")
860-- port map (
861-- O => clk_buf_sig, -- Clock buffer output
862-- I => clk -- Clock buffer input (connect directly to top-level port)
863-- );
864
865-- Inst_FTM_clk_gen : FTM_clk_gen
866-- port map(
867-- clk => clk_buf_sig,
868-- rst => reset_sig,
869-- clk_1 => clk_1M_sig,
870-- clk_50 => clk_50M_sig,
871-- clk_250 => clk_250M_sig,
872-- clk_250_ps => clk_250M_ps_sig,
873-- ready => clk_ready_sig
874-- );
875
876 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
877 port map(
878 clk => clk,
879 rst => reset_sig,
880 clk_1 => clk_1M_sig,
881 clk_50 => clk_50M_sig,
882 clk_250 => clk_250M_sig,
883 clk_250_ps => clk_250M_ps_sig,
884 ready => clk_ready_sig
885 );
886
887 Inst_FTM_dna_gen : FTM_dna_gen
888 port map(
889 clk => clk_50M_sig,
890 start => dna_start_sig,
891 dna => dna_sig,
892 ready => dna_ready_sig
893 );
894
895 --differential output buffer for trigger signal
896 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
897 port map(
898 O => TRG_p,
899 OB => TRG_n,
900 I => trigger_signal_sig
901 );
902
903 --differential output buffer for TIM signal
904 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
905 port map(
906 O => TIM_Run_p,
907 OB => TIM_Run_n,
908 I => TIM_signal_sig
909 );
910
911 --differential output buffer for fast reset signal
912 OBUFDS_LVDS_33_RES : OBUFDS_LVDS_33
913 port map(
914 O => RES_p,
915 OB => RES_n,
916 I => '0'
917 );
918
919 Inst_trigger_manager : trigger_manager
920 port map(
921 --clocks
922 clk_50MHz => clk_50M_sig,
923 clk_250MHz => clk_250M_sig,
924 clk_250MHz_180 => clk_250M_ps_sig,
925 --trigger primitives from FTUs
926 trig_prim_0 => Trig_Prim_A, --crate 0
927 trig_prim_1 => Trig_Prim_B, --crate 1
928 trig_prim_2 => Trig_Prim_C, --crate 2
929 trig_prim_3 => Trig_Prim_D, --crate 3
930 --external signals
931 ext_trig_1 => ext_Trig(1),
932 ext_trig_2 => ext_Trig(2),
933 ext_veto => Veto,
934 FAD_busy_0 => Busy0, --crate 0
935 FAD_busy_1 => Busy1, --crate 1
936 FAD_busy_2 => Busy2, --crate 2
937 FAD_busy_3 => Busy3, --crate 3
938 --control signals from e.g. main control
939 start_run => trigger_start_sig, --enable trigger output
940 stop_run => trigger_stop_sig, --disable trigger output
941 new_config => config_trigger_sig,
942 --settings register (see FTM Firmware Specifications)
943 general_settings => general_settings_sig,
944 LP_and_PED_freq => lp_pt_freq_sig,
945 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
946 maj_coinc_n_phys => coin_n_p_sig,
947 maj_coinc_n_calib => coin_n_c_sig,
948 trigger_delay => trigger_delay_sig,
949 TIM_delay => timemarker_delay_sig,
950 dead_time => dead_time_sig,
951 coinc_window_phys => coin_win_p_sig,
952 coinc_window_calib => coin_win_c_sig,
953 active_FTU_list_0 => ftu_active_cr0_sig,
954 active_FTU_list_1 => ftu_active_cr1_sig,
955 active_FTU_list_2 => ftu_active_cr2_sig,
956 active_FTU_list_3 => ftu_active_cr3_sig,
957 --control signals or information for other entities
958 trigger_ID_read => trigger_ID_read_sig,
959 trig_cnt_copy_read => trigger_counter_read_sig,
960 trigger_ID_ready => trigger_ID_ready_sig,
961 trigger_ID => trigger_ID_sig,
962 trig_cnt_copy => trigger_counter_sig, --counter reading
963 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
964 trigger_active => trigger_active_sig, --phys triggers are enabled/active
965 config_done => config_trigger_done_sig,
966 LP1_pulse => LP1_pulse_sig, --send start signal to light pulser 1
967 LP2_pulse => LP2_pulse_sig, --send start signal to light pulser 2
968 --trigger and time marker output signals to FADs
969 trigger_signal => trigger_signal_sig,
970 TIM_signal => TIM_signal_sig
971 );
972
973 Inst_Clock_cond_interface : Clock_cond_interface
974 port map(
975 clk => clk_50M_sig,
976 CLK_Clk_Cond => CLK_Clk_Cond,
977 LE_Clk_Cond => LE_Clk_Cond,
978 DATA_Clk_Cond => DATA_Clk_Cond,
979 SYNC_Clk_Cond => SYNC_Clk_Cond,
980 LD_Clk_Cond => LD_Clk_Cond,
981 TIM_Sel => TIM_Sel,
982 cc_R0 => cc_R0_sig,
983 cc_R1 => cc_R1_sig,
984 cc_R8 => cc_R8_sig,
985 cc_R9 => cc_R9_sig,
986 cc_R11 => cc_R11_sig,
987 cc_R13 => cc_R13_sig,
988 cc_R14 => cc_R14_sig,
989 cc_R15 => cc_R15_sig,
990 start_config => config_start_cc_sig,
991 config_started => config_started_cc_sig,
992 config_done => config_ready_cc_sig,
993 timemarker_select => general_settings_sig(0)
994 );
995
996 Inst_FTM_central_control : FTM_central_control
997 port map(
998 clk => clk_50M_sig,
999 clk_ready => clk_ready_sig,
1000 clk_scaler => clk_1M_sig,
1001 new_config => new_config_sig,
1002 config_started => config_started_sig,
1003 config_started_ack => config_started_ack_sig,
1004 config_start_eth => config_start_eth_sig,
1005 config_started_eth => config_started_eth_sig,
1006 config_ready_eth => config_ready_eth_sig,
1007 config_start_ftu => config_start_ftu_sig,
1008 config_started_ftu => config_started_ftu_sig,
1009 config_ready_ftu => config_ready_ftu_sig,
1010 ping_ftu_start => ping_ftu_start_sig,
1011 ping_ftu_started => ping_ftu_started_sig,
1012 ping_ftu_ready => ping_ftu_ready_sig,
1013 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
1014 ping_ftu_started_ftu => ping_ftu_started1_sig,
1015 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
1016 rates_ftu => rates_ftu_start_sig,
1017 rates_started_ftu => rates_ftu_started_sig,
1018 rates_ready_ftu => rates_ftu_ready_sig,
1019 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
1020 dd_send => dd_send_sig,
1021 dd_send_ack => dd_send_ack_sig,
1022 dd_send_ready => dd_send_ready_sig,
1023 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1024 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1025 dd_block_start_ftu => dd_block_start_ftu_sig,
1026 config_start_cc => config_start_cc_sig,
1027 config_started_cc => config_started_cc_sig,
1028 config_ready_cc => config_ready_cc_sig,
1029 config_start_lp => config_start_lp_sig,
1030 config_started_lp => config_started_lp_sig,
1031 config_ready_lp => config_ready_lp_sig,
1032 config_trigger => config_trigger_sig,
1033 config_trigger_done => config_trigger_done_sig,
1034 dna_start => dna_start_sig,
1035 dna_ready => dna_ready_sig,
1036 crate_reset => crate_reset_sig,
1037 crate_reset_ack => crate_reset_ack_sig,
1038 crate_reset_param => crate_reset_param_sig,
1039 start_run => start_run_sig,
1040 start_run_ack => start_run_ack_sig,
1041 stop_run => stop_run_sig,
1042 stop_run_ack => stop_run_ack_sig,
1043 current_cc_state => current_cc_state_sig,
1044 cc_state_test => cc_state_test_sig,
1045 start_run_param => start_run_param_sig,
1046 start_run_num_events => start_run_num_events_sig,
1047 trigger_start => trigger_start_sig,
1048 trigger_stop => trigger_stop_sig,
1049 enable_ID_sending => enable_ID_sending_sig,
1050 reset_timer => reset_timer_sig,
1051 crate_res_0 => crate_res0_sig,
1052 crate_res_1 => crate_res1_sig,
1053 crate_res_2 => crate_res2_sig,
1054 crate_res_3 => crate_res3_sig,
1055 new_config_ftu => new_config_ftu_sig,
1056 new_config_ftu_ack => new_config_ftu_ack_sig,
1057 config_single_FTU => config_single_FTU_sig,
1058 config_single_FTU_started => config_single_FTU_started_sig,
1059 config_single_FTU_done => config_single_FTU_done_sig
1060 );
1061
1062 Inst_FTM_ftu_control : FTM_ftu_control
1063 port map(
1064 clk_50MHz => clk_50M_sig,
1065 rx_en => Bus1_Rx_En,
1066 tx_en => Bus1_Tx_En,
1067 rx_d_0 => Bus1_RxD_0,
1068 tx_d_0 => Bus1_TxD_0,
1069 rx_d_1 => Bus1_RxD_1,
1070 tx_d_1 => Bus1_TxD_1,
1071 rx_d_2 => Bus1_RxD_2,
1072 tx_d_2 => Bus1_TxD_2,
1073 rx_d_3 => Bus1_RxD_3,
1074 tx_d_3 => Bus1_TxD_3,
1075 new_config => config_start_ftu_sig,
1076 ping_all => ping_ftu_start_ftu_sig,
1077 read_rates => rates_ftu_start_sig,
1078 config_single_FTU => config_single_FTU_sig,
1079 read_rates_started => rates_ftu_started_sig,
1080 read_rates_done => rates_ftu_ready_sig,
1081 new_config_started => config_started_ftu_sig,
1082 new_config_done => config_ready_ftu_sig,
1083 ping_all_started => ping_ftu_started1_sig,
1084 ping_all_done => ping_ftu_ready1_sig,
1085 config_single_FTU_started => config_single_FTU_started_sig,
1086 config_single_FTU_done => config_single_FTU_done_sig,
1087 ftu_active_cr0 => ftu_active_cr0_sig,
1088 ftu_active_cr1 => ftu_active_cr1_sig,
1089 ftu_active_cr2 => ftu_active_cr2_sig,
1090 ftu_active_cr3 => ftu_active_cr3_sig,
1091 config_single_FTU_param => new_config_ftu_param_sig,
1092 ftu_error_calls => ftu_error_calls_sig,
1093 ftu_error_data => ftu_error_data_sig,
1094 ftu_error_send => ftu_error_send_sig,
1095 ftu_error_send_ack => ftu_error_send_ack_sig,
1096 ftu_error_send_ready=> ftu_error_send_ready_sig,
1097 static_RAM_busy => sd_busy_sig,
1098 static_RAM_started => sd_started_ftu_sig,
1099 static_RAM_ready => sd_ready_sig,
1100 data_static_RAM => sd_data_out_ftu_sig,
1101 read_static_RAM => sd_read_ftu_sig,
1102 addr_static_RAM => sd_addr_ftu_sig,
1103 dynamic_RAM_busy => dd_busy_sig,
1104 dynamic_RAM_started => dd_started_ftu_sig,
1105 dynamic_RAM_ready => dd_ready_sig,
1106 data_dynamic_RAM => dd_data_sig,
1107 write_dynamic_RAM => dd_write_sig,
1108 addr_dynamic_RAM => dd_addr_sig,
1109 FTUlist_RAM_busy => fl_busy_sig,
1110 FTUlist_RAM_started => fl_started_ftu_sig,
1111 FTUlist_RAM_ready => fl_ready_sig,
1112 data_FTUlist_RAM => fl_data_sig,
1113 write_FTUlist_RAM => fl_write_sig,
1114 addr_FTUlist_RAM => fl_addr_sig
1115 );
1116
1117 Inst_FTM_fad_broadcast : FTM_fad_broadcast
1118 port map(
1119 clk_50MHz => clk_50M_sig,
1120 rx_en => Bus2_Rx_En,
1121 tx_en => Bus2_Tx_En,
1122 rx_d_0 => Bus2_RxD_0,
1123 tx_d_0 => Bus2_TxD_0,
1124 rx_d_1 => Bus2_RxD_1,
1125 tx_d_1 => Bus2_TxD_1,
1126 rx_d_2 => Bus2_RxD_2,
1127 tx_d_2 => Bus2_TxD_2,
1128 rx_d_3 => Bus2_RxD_3,
1129 tx_d_3 => Bus2_TxD_3,
1130 enable_ID_sending => enable_ID_sending_sig,
1131 TIM_source => general_settings_sig(0),
1132 LP_settings => "0000",
1133 trigger_ID_ready => trigger_ID_ready_sig,
1134 trigger_ID => trigger_ID_sig,
1135 trigger_ID_read => trigger_ID_read_sig
1136 );
1137
1138 Inst_ethernet_modul : ethernet_modul
1139 port map(
1140 wiz_reset => W_RES,
1141 wiz_addr => W_A,
1142 wiz_data => W_D,
1143 wiz_cs => W_CS,
1144 wiz_wr => W_WR,
1145 wiz_rd => W_RD,
1146 wiz_int => W_INT,
1147 clk => clk_50M_sig,
1148 sd_ready => sd_ready_sig,
1149 sd_busy => sd_busy_sig,
1150 led => led_sig,
1151 sd_read_ftu => sd_read_ftu_sig,
1152 sd_started_ftu => sd_started_ftu_sig,
1153 cc_R0 => cc_R0_sig,
1154 cc_R1 => cc_R1_sig,
1155 cc_R11 => cc_R11_sig,
1156 cc_R13 => cc_R13_sig,
1157 cc_R14 => cc_R14_sig,
1158 cc_R15 => cc_R15_sig,
1159 cc_R8 => cc_R8_sig,
1160 cc_R9 => cc_R9_sig,
1161 coin_n_c => coin_n_c_sig,
1162 coin_n_p => coin_n_p_sig,
1163 dead_time => dead_time_sig,
1164 general_settings => general_settings_sig,
1165 lp1_amplitude => lp1_amplitude_sig,
1166 lp1_delay => lp1_delay_sig,
1167 lp2_amplitude => lp2_amplitude_sig,
1168 lp2_delay => lp2_delay_sig,
1169 lp_pt_freq => lp_pt_freq_sig,
1170 lp_pt_ratio => lp_pt_ratio_sig,
1171 timemarker_delay => timemarker_delay_sig,
1172 trigger_delay => trigger_delay_sig,
1173 sd_addr_ftu => sd_addr_ftu_sig,
1174 sd_data_out_ftu => sd_data_out_ftu_sig,
1175 ftu_active_cr0 => ftu_active_cr0_sig,
1176 ftu_active_cr1 => ftu_active_cr1_sig,
1177 ftu_active_cr2 => ftu_active_cr2_sig,
1178 ftu_active_cr3 => ftu_active_cr3_sig,
1179 new_config => new_config_sig,
1180 config_started => config_started_sig,
1181 config_start_eth => config_start_eth_sig,
1182 config_started_eth => config_started_eth_sig,
1183 config_ready_eth => config_ready_eth_sig,
1184 config_started_ack => config_started_ack_sig,
1185 fl_busy => fl_busy_sig,
1186 fl_ready => fl_ready_sig,
1187 fl_write_ftu => fl_write_sig,
1188 fl_started_ftu => fl_started_ftu_sig,
1189 fl_addr_ftu => fl_addr_sig,
1190 fl_data_in_ftu => fl_data_sig,
1191 ping_ftu_start => ping_ftu_start_sig,
1192 ping_ftu_started => ping_ftu_started_sig,
1193 ping_ftu_ready => ping_ftu_ready_sig,
1194 dd_write_ftu => dd_write_sig,
1195 dd_started_ftu => dd_started_ftu_sig,
1196 dd_data_in_ftu => dd_data_sig,
1197 dd_addr_ftu => dd_addr_sig,
1198 dd_busy => dd_busy_sig,
1199 dd_ready => dd_ready_sig,
1200 coin_win_c => coin_win_c_sig,
1201 coin_win_p => coin_win_p_sig,
1202 --new stuff
1203 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1204 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1205 dd_block_start_ftu => dd_block_start_ftu_sig,
1206 dd_send => dd_send_sig,
1207 dd_send_ack => dd_send_ack_sig,
1208 dd_send_ready => dd_send_ready_sig,
1209 --very new stuff
1210 ftu_error_calls => ftu_error_calls_sig,
1211 ftu_error_data => ftu_error_data_sig,
1212 ftu_error_send => ftu_error_send_sig,
1213 ftu_error_send_ack => ftu_error_send_ack_sig,
1214 ftu_error_send_ready => ftu_error_send_ready_sig,
1215 prescaling_FTU01 => prescaling_FTU01_sig,
1216 trigger_counter => trigger_counter_sig,
1217 trigger_counter_read => trigger_counter_read_sig,
1218 trigger_counter_valid => trigger_counter_valid_sig,
1219 --newest stuff
1220 board_id => dna_sig,
1221 get_ts_counter => get_ts_counter_sig,
1222 get_ts_counter_ready => get_ts_counter_ready_sig,
1223 get_ts_counter_started => get_ts_counter_started_sig,
1224 timestamp_counter => timestamp_counter_sig,
1225 get_ot_counter => get_ot_counter_sig,
1226 get_ot_counter_ready => get_ot_counter_ready_sig,
1227 get_ot_counter_started => get_ot_counter_started_sig,
1228 on_time_counter => on_time_counter_sig,
1229 temp_sensor_array => (35, 45, 55, 65),
1230 temp_sensor_ready => '1',
1231 crate_reset => crate_reset_sig,
1232 crate_reset_ack => crate_reset_ack_sig,
1233 crate_reset_param => crate_reset_param_sig,
1234 start_run => start_run_sig,
1235 start_run_ack => start_run_ack_sig,
1236 stop_run => stop_run_sig,
1237 stop_run_ack => stop_run_ack_sig,
1238 current_cc_state => current_cc_state_sig,
1239 start_run_param => start_run_param_sig,
1240 start_run_num_events => start_run_num_events_sig,
1241 new_config_ftu => new_config_ftu_sig,
1242 new_config_ftu_ack => new_config_ftu_ack_sig,
1243 new_config_ftu_param => new_config_ftu_param_sig
1244 );
1245
1246-- Inst_counter_dummy_ts : counter_dummy
1247-- port map(
1248-- clk => clk_50M_sig,
1249-- get_counter => get_ts_counter_sig,
1250-- get_counter_started => get_ts_counter_started_sig,
1251-- get_counter_ready => get_ts_counter_ready_sig,
1252-- counter => timestamp_counter_sig
1253-- );
1254
1255-- Inst_counter_dummy_ot : counter_dummy
1256-- port map(
1257-- clk => clk_50M_sig,
1258-- get_counter => get_ot_counter_sig,
1259-- get_counter_started => get_ot_counter_started_sig,
1260-- get_counter_ready => get_ot_counter_ready_sig,
1261-- counter => on_time_counter_sig
1262-- );
1263
1264 Inst_Timing_counter_ts : Timing_counter
1265 port map(
1266 clk => clk_50M_sig,
1267 enable => '1',
1268 reset => reset_timer_sig,
1269 read_counter => get_ts_counter_sig,
1270 reading_started => get_ts_counter_started_sig,
1271 reading_valid => get_ts_counter_ready_sig,
1272 counter_reading => timestamp_counter_sig
1273 );
1274
1275 Inst_Timing_counter_ot : Timing_counter
1276 port map(
1277 clk => clk_50M_sig,
1278 enable => trigger_active_sig,
1279 reset => reset_timer_sig,
1280 read_counter => get_ot_counter_sig,
1281 reading_started => get_ot_counter_started_sig,
1282 reading_valid => get_ot_counter_ready_sig,
1283 counter_reading => on_time_counter_sig
1284 );
1285
1286 Inst_Lightpulser_interface_Basic : Lightpulser_interface_Basic
1287 port map (
1288 clk_50 => clk_50M_sig,
1289 --clk_250 => clk_250M_sig,
1290 Cal_0_p => Cal_2_p, --swapped with Cal_2_p due to connector on FLD board
1291 Cal_0_n => Cal_2_n, --swapped with Cal_2_n due to connector on FLD board
1292 Cal_1_p => Cal_1_p,
1293 Cal_1_n => Cal_1_n,
1294 Cal_2_p => Cal_0_p, --swapped with Cal_0_p due to connector on FLD board
1295 Cal_2_n => Cal_0_n, --swapped with Cal_0_n due to connector on FLD board
1296 Cal_3_p => Cal_3_p,
1297 Cal_3_n => Cal_3_n,
1298 Cal_4_p => Cal_6_p, --swapped with Cal_6_p due to connector on FLD board
1299 Cal_4_n => Cal_6_n, --swapped with Cal_6_n due to connector on FLD board
1300 Cal_5_p => Cal_5_p,
1301 Cal_5_n => Cal_5_n,
1302 Cal_6_p => Cal_4_p, --swapped with Cal_4_p due to connector on FLD board
1303 Cal_6_n => Cal_4_n, --swapped with Cal_4_n due to connector on FLD board
1304 Cal_7_p => Cal_7_p,
1305 Cal_7_n => Cal_7_n,
1306 LP1_ampl => lp1_amplitude_sig,
1307 LP2_ampl => lp2_amplitude_sig,
1308 --LP1_delay => lp1_delay_sig,
1309 --LP2_delay => lp2_delay_sig,
1310 LP1_pulse => LP1_pulse_sig,
1311 LP2_pulse => LP2_pulse_sig,
1312 start_config => config_start_lp_sig,
1313 config_started => config_started_lp_sig,
1314 config_done => config_ready_lp_sig
1315 );
1316
1317 LED_red <= led_sig(3 downto 0);
1318 LED_ye <= led_sig(5 downto 4);
1319 LED_gn <= led_sig(7 downto 6);
1320
1321 TP(32 downto 8) <= (others => '0');
1322 --TP(8) <= clk_50M_sig;
1323 TP( 7 downto 0) <= cc_state_test_sig;
1324
1325 Crate_Res0 <= crate_res0_sig;
1326 Crate_Res1 <= crate_res1_sig;
1327 Crate_Res2 <= crate_res2_sig;
1328 Crate_Res3 <= crate_res3_sig;
1329
1330end Behavioral;
1331
1332
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