source: firmware/FTM/FTM_top.vhd@ 12018

Last change on this file since 12018 was 11654, checked in by weitzel, 13 years ago
two new status states introduced for FTM to indicate lock status of clock conditioner
File size: 57.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 Bus2_TxD_0 : out STD_LOGIC;
153
154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 Bus2_TxD_1 : out STD_LOGIC;
156
157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 Bus2_TxD_2 : out STD_LOGIC;
159
160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 Crate_Res0 : out STD_LOGIC;
180 Crate_Res1 : out STD_LOGIC;
181 Crate_Res2 : out STD_LOGIC;
182 Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 RES_p : out STD_LOGIC; -- RES+ Reset
215 RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 Cal_0_p : out STD_LOGIC;
233 Cal_0_n : out STD_LOGIC;
234 Cal_1_p : out STD_LOGIC;
235 Cal_1_n : out STD_LOGIC;
236 Cal_2_p : out STD_LOGIC;
237 Cal_2_n : out STD_LOGIC;
238 Cal_3_p : out STD_LOGIC;
239 Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 Cal_4_p : out STD_LOGIC;
244 Cal_4_n : out STD_LOGIC;
245 Cal_5_p : out STD_LOGIC;
246 Cal_5_n : out STD_LOGIC;
247 Cal_6_p : out STD_LOGIC;
248 Cal_6_n : out STD_LOGIC;
249 Cal_7_p : out STD_LOGIC;
250 Cal_7_n : out STD_LOGIC;
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 TP : inout STD_LOGIC_VECTOR(32 downto 0)
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_ftu_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_ftu_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic; -- initialized in central control
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352 signal cc_locked_sig : std_logic := '0';
353
354 signal config_start_lp_sig : std_logic; -- initialized in central control
355 signal config_started_lp_sig : std_logic; -- initialized in light pulser interface
356 signal config_ready_lp_sig : std_logic; -- initialized in light pulser interface
357
358 signal config_trigger_sig : std_logic;
359 signal config_trigger_done_sig : std_logic;
360
361 signal clk_buf_sig : std_logic;
362 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
363 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
364 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
365 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
366 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
367
368 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager
369 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager
370 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast
371
372 signal trigger_active_sig : std_logic; -- initialized in trigger manager
373
374 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
375
376 signal trigger_signal_sig : std_logic := '0';
377 signal TIM_signal_sig : std_logic := '0';
378
379 --signals for FPGA DNA identifier
380 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen
381 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control
382 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen
383
384 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
385
386 signal get_ot_counter_sig : std_logic;
387 signal get_ot_counter_started_sig : std_logic;
388 signal get_ot_counter_ready_sig : std_logic;
389 signal on_time_counter_sig : std_logic_vector(47 downto 0);
390
391 signal get_ts_counter_sig : std_logic;
392 signal get_ts_counter_started_sig : std_logic;
393 signal get_ts_counter_ready_sig : std_logic;
394 signal timestamp_counter_sig : std_logic_vector(47 downto 0);
395
396 signal crate_reset_sig : std_logic;
397 signal crate_reset_ack_sig : std_logic;
398 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0);
399 signal start_run_sig : std_logic;
400 signal start_run_ack_sig : std_logic;
401 signal stop_run_sig : std_logic;
402 signal stop_run_ack_sig : std_logic;
403 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0);
404 signal cc_state_test_sig : std_logic_vector ( 7 downto 0);
405 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0);
406 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0);
407
408 signal trigger_start_sig : std_logic;
409 signal trigger_stop_sig : std_logic;
410
411 signal enable_ID_sending_sig : std_logic;
412 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control
413
414 signal crate_res0_sig : std_logic; -- initialized in FTM_central_control
415 signal crate_res1_sig : std_logic; -- initialized in FTM_central_control
416 signal crate_res2_sig : std_logic; -- initialized in FTM_central_control
417 signal crate_res3_sig : std_logic; -- initialized in FTM_central_control
418
419 signal LP1_pulse_sig : std_logic := '0';
420 signal LP2_pulse_sig : std_logic := '0';
421
422 signal new_config_ftu_sig : std_logic; -- initialized in ethernet_modul
423 signal new_config_ftu_ack_sig : std_logic; -- initialized in FTM_central_control
424 signal new_config_ftu_param_sig : std_logic_vector (15 DOWNTO 0); -- initialized in ethernet_modul
425
426 signal config_single_FTU_sig : std_logic; -- initialized in FTM_central_control
427 signal config_single_FTU_started_sig : std_logic; -- initialized in FTM_ftu_control
428 signal config_single_FTU_done_sig : std_logic; -- initialized in FTM_ftu_control
429
430-- component FTM_clk_gen
431-- port(
432-- clk : IN STD_LOGIC;
433-- rst : IN STD_LOGIC;
434-- clk_1 : OUT STD_LOGIC;
435-- clk_50 : OUT STD_LOGIC;
436-- clk_250 : OUT STD_LOGIC;
437-- clk_250_ps : OUT STD_LOGIC;
438-- ready : OUT STD_LOGIC
439-- );
440-- end component;
441
442 component FTM_clk_gen_2
443 port(
444 clk : IN STD_LOGIC;
445 rst : IN STD_LOGIC;
446 clk_1 : OUT STD_LOGIC;
447 clk_50 : OUT STD_LOGIC;
448 clk_250 : OUT STD_LOGIC;
449 clk_250_ps : OUT STD_LOGIC;
450 ready : OUT STD_LOGIC
451 );
452 end component;
453
454 component FTM_dna_gen
455 port(
456 clk : IN STD_LOGIC;
457 start : IN STD_LOGIC;
458 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
459 ready : OUT STD_LOGIC
460 );
461 end component;
462
463 component trigger_manager
464 port(
465 --clocks
466 clk_50MHz : in std_logic;
467 clk_250MHz : in std_logic;
468 clk_250MHz_180 : in std_logic;
469 --trigger primitives from FTUs
470 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
471 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
472 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
473 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
474 --external signals
475 ext_trig_1 : in std_logic;
476 ext_trig_2 : in std_logic;
477 ext_veto : in std_logic;
478 FAD_busy_0 : in std_logic; --crate 0
479 FAD_busy_1 : in std_logic; --crate 1
480 FAD_busy_2 : in std_logic; --crate 2
481 FAD_busy_3 : in std_logic; --crate 3
482 --control signals from e.g. main control
483 start_run : in std_logic; --enable trigger output
484 stop_run : in std_logic; --disable trigger output
485 new_config : in std_logic;
486 --settings register (see FTM Firmware Specifications)
487 general_settings : in std_logic_vector(15 downto 0);
488 LP_and_PED_freq : in std_logic_vector(15 downto 0);
489 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
490 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
491 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
492 trigger_delay : in std_logic_vector(15 downto 0);
493 TIM_delay : in std_logic_vector(15 downto 0);
494 dead_time : in std_logic_vector(15 downto 0);
495 coinc_window_phys : in std_logic_vector(15 downto 0);
496 coinc_window_calib : in std_logic_vector(15 downto 0);
497 active_FTU_list_0 : in std_logic_vector(15 downto 0);
498 active_FTU_list_1 : in std_logic_vector(15 downto 0);
499 active_FTU_list_2 : in std_logic_vector(15 downto 0);
500 active_FTU_list_3 : in std_logic_vector(15 downto 0);
501 --control signals or information for other entities
502 trigger_ID_read : in std_logic;
503 trig_cnt_copy_read : in std_logic;
504 trigger_ID_ready : out std_logic;
505 trigger_ID : out std_logic_vector(55 downto 0);
506 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
507 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
508 trigger_active : out std_logic; --phys triggers are enabled/active
509 config_done : out std_logic;
510 LP1_pulse : out std_logic; --send start signal to light pulser 1
511 LP2_pulse : out std_logic; --send start signal to light pulser 2
512 --trigger and time marker output signals to FADs
513 trigger_signal : out std_logic;
514 TIM_signal : out std_logic
515 );
516 end component;
517
518 component Clock_cond_interface is
519 port(
520 clk : IN STD_LOGIC;
521 CLK_Clk_Cond : out STD_LOGIC;
522 LE_Clk_Cond : out STD_LOGIC;
523 DATA_Clk_Cond : out STD_LOGIC;
524 SYNC_Clk_Cond : out STD_LOGIC;
525 LD_Clk_Cond : in STD_LOGIC;
526 TIM_Sel : out STD_LOGIC;
527 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
528 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
529 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
530 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
531 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
532 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
533 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
534 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
535 start_config : in STD_LOGIC;
536 config_started : out STD_LOGIC;
537 config_done : out STD_LOGIC;
538 locked : out STD_LOGIC;
539 timemarker_select : in STD_LOGIC
540 );
541 end component;
542
543 component FTM_central_control
544 port(
545 clk : IN std_logic;
546 clk_ready : in std_logic;
547 clk_scaler : IN std_logic;
548 new_config : IN std_logic;
549 config_started : OUT std_logic := '0';
550 config_started_ack : IN std_logic;
551 config_start_eth : OUT std_logic := '0';
552 config_started_eth : IN std_logic;
553 config_ready_eth : IN std_logic;
554 config_start_ftu : OUT std_logic := '0';
555 config_started_ftu : IN std_logic;
556 config_ready_ftu : IN std_logic;
557 ping_ftu_start : IN std_logic;
558 ping_ftu_started : OUT std_logic := '0';
559 ping_ftu_ready : OUT std_logic := '0';
560 ping_ftu_start_ftu : OUT std_logic := '0';
561 ping_ftu_started_ftu : IN std_logic;
562 ping_ftu_ready_ftu : IN std_logic;
563 rates_ftu : OUT std_logic := '0';
564 rates_started_ftu : IN std_logic;
565 rates_ready_ftu : IN std_logic;
566 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
567 dd_send : OUT std_logic := '0';
568 dd_send_ack : IN std_logic;
569 dd_send_ready : IN std_logic;
570 dd_block_ready_ftu : out std_logic := '0';
571 dd_block_start_ack_ftu : in std_logic;
572 dd_block_start_ftu : out std_logic := '0';
573 config_start_cc : out std_logic := '0';
574 config_started_cc : in std_logic;
575 config_ready_cc : in std_logic;
576 cc_locked : in std_logic;
577 config_start_lp : out std_logic := '0';
578 config_started_lp : in std_logic;
579 config_ready_lp : in std_logic;
580 config_trigger : out std_logic;
581 config_trigger_done : in std_logic;
582 dna_start : out std_logic;
583 dna_ready : in std_logic;
584 crate_reset : IN std_logic;
585 crate_reset_ack : OUT std_logic;
586 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
587 start_run : IN std_logic;
588 start_run_ack : OUT std_logic;
589 stop_run : IN std_logic;
590 stop_run_ack : OUT std_logic;
591 current_cc_state : OUT std_logic_vector (15 DOWNTO 0);
592 cc_state_test : OUT std_logic_vector ( 7 downto 0);
593 start_run_param : IN std_logic_vector (15 DOWNTO 0);
594 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
595 trigger_start : out std_logic;
596 trigger_stop : out std_logic;
597 enable_ID_sending : out std_logic;
598 reset_timer : out std_logic;
599 crate_res_0 : out std_logic;
600 crate_res_1 : out std_logic;
601 crate_res_2 : out std_logic;
602 crate_res_3 : out std_logic;
603 new_config_ftu : in std_logic;
604 new_config_ftu_ack : out std_logic := '0';
605 config_single_FTU : out std_logic := '0';
606 config_single_FTU_started : in std_logic;
607 config_single_FTU_done : in std_logic
608 );
609 end component;
610
611 component FTM_ftu_control
612 port(
613 clk_50MHz : in std_logic;
614 rx_en : out STD_LOGIC;
615 tx_en : out STD_LOGIC;
616 rx_d_0 : in STD_LOGIC;
617 tx_d_0 : out STD_LOGIC;
618 rx_d_1 : in STD_LOGIC;
619 tx_d_1 : out STD_LOGIC;
620 rx_d_2 : in STD_LOGIC;
621 tx_d_2 : out STD_LOGIC;
622 rx_d_3 : in STD_LOGIC;
623 tx_d_3 : out STD_LOGIC;
624 new_config : in std_logic;
625 ping_all : in std_logic;
626 read_rates : in std_logic;
627 config_single_FTU : in std_logic;
628 read_rates_started : out std_logic := '0';
629 read_rates_done : out std_logic := '0';
630 new_config_started : out std_logic := '0';
631 new_config_done : out std_logic := '0';
632 ping_all_started : out std_logic := '0';
633 ping_all_done : out std_logic := '0';
634 config_single_FTU_started : out std_logic := '0';
635 config_single_FTU_done : out std_logic := '0';
636 ftu_active_cr0 : in std_logic_vector (15 downto 0);
637 ftu_active_cr1 : in std_logic_vector (15 downto 0);
638 ftu_active_cr2 : in std_logic_vector (15 downto 0);
639 ftu_active_cr3 : in std_logic_vector (15 downto 0);
640 config_single_FTU_param : in std_logic_vector (15 DOWNTO 0);
641 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
642 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
643 ftu_error_send : out std_logic := '0';
644 ftu_error_send_ack : in std_logic;
645 ftu_error_send_ready : in std_logic;
646 static_RAM_busy : in std_logic;
647 static_RAM_started : in std_logic;
648 static_RAM_ready : in std_logic;
649 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
650 read_static_RAM : out std_logic := '0';
651 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
652 dynamic_RAM_busy : in std_logic;
653 dynamic_RAM_started : in std_logic;
654 dynamic_RAM_ready : in std_logic;
655 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
656 write_dynamic_RAM : out std_logic := '0';
657 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
658 FTUlist_RAM_busy : in std_logic;
659 FTUlist_RAM_started : in std_logic;
660 FTUlist_RAM_ready : in std_logic;
661 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
662 write_FTUlist_RAM : out std_logic := '0';
663 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
664 );
665 end component;
666
667 component FTM_fad_broadcast
668 port(
669 clk_50MHz : in std_logic;
670 rx_en : out STD_LOGIC;
671 tx_en : out STD_LOGIC;
672 rx_d_0 : in STD_LOGIC;
673 tx_d_0 : out STD_LOGIC;
674 rx_d_1 : in STD_LOGIC;
675 tx_d_1 : out STD_LOGIC;
676 rx_d_2 : in STD_LOGIC;
677 tx_d_2 : out STD_LOGIC;
678 rx_d_3 : in STD_LOGIC;
679 tx_d_3 : out STD_LOGIC;
680 enable_ID_sending : in std_logic;
681 TIM_source : in std_logic;
682 LP_settings : in std_logic_vector(3 downto 0);
683 trigger_ID_ready : in std_logic;
684 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
685 trigger_ID_read : out std_logic
686 );
687 end component;
688
689 component ethernet_modul
690 port(
691 wiz_reset : OUT std_logic := '1';
692 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
693 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
694 wiz_cs : OUT std_logic := '1';
695 wiz_wr : OUT std_logic := '1';
696 wiz_rd : OUT std_logic := '1';
697 wiz_int : IN std_logic ;
698 clk : IN std_logic ;
699 sd_ready : OUT std_logic ;
700 sd_busy : OUT std_logic ;
701 led : OUT std_logic_vector (7 DOWNTO 0);
702 sd_read_ftu : IN std_logic ;
703 sd_started_ftu : OUT std_logic := '0';
704 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
705 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
706 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
707 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
708 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
709 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
710 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
711 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
712 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
713 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
714 dead_time : OUT std_logic_vector (15 DOWNTO 0);
715 general_settings : OUT std_logic_vector (15 DOWNTO 0);
716 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
717 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
718 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
719 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
720 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
721 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
722 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
723 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
724 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
725 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
726 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
727 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
728 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
729 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
730 new_config : OUT std_logic := '0';
731 config_started : IN std_logic ;
732 config_start_eth : IN std_logic ;
733 config_started_eth : OUT std_logic := '0';
734 config_ready_eth : OUT std_logic := '0';
735 config_started_ack : OUT std_logic := '0';
736 fl_busy : OUT std_logic ;
737 fl_ready : OUT std_logic ;
738 fl_write_ftu : IN std_logic ;
739 fl_started_ftu : OUT std_logic := '0';
740 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
741 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
742 ping_ftu_start : OUT std_logic := '0';
743 ping_ftu_started : IN std_logic ;
744 ping_ftu_ready : IN std_logic ;
745 dd_write_ftu : IN std_logic ;
746 dd_started_ftu : OUT std_logic := '0';
747 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
748 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
749 dd_busy : OUT std_logic ;
750 dd_ready : OUT std_logic ;
751 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
752 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
753 --new stuff
754 dd_block_ready_ftu : IN std_logic;
755 dd_block_start_ack_ftu : OUT std_logic := '0';
756 dd_block_start_ftu : IN std_logic;
757 dd_send : IN std_logic;
758 dd_send_ack : OUT std_logic := '1';
759 dd_send_ready : OUT std_logic := '1';
760 --very new stuff
761 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
762 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
763 ftu_error_send : IN std_logic;
764 ftu_error_send_ack : OUT std_logic := '1';
765 ftu_error_send_ready : OUT std_logic := '1';
766 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
767 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
768 trigger_counter_read : OUT std_logic := '0';
769 trigger_counter_valid : IN std_logic;
770 --newest stuff
771 board_id : IN std_logic_vector (63 DOWNTO 0);
772 get_ts_counter : OUT std_logic := '0';
773 get_ts_counter_ready : IN std_logic;
774 get_ts_counter_started : IN std_logic;
775 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
776 get_ot_counter : OUT std_logic := '0';
777 get_ot_counter_ready : IN std_logic;
778 get_ot_counter_started : IN std_logic;
779 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
780 temp_sensor_array : IN sensor_array_type;
781 temp_sensor_ready : IN std_logic;
782 crate_reset : OUT std_logic := '0';
783 crate_reset_ack : IN std_logic;
784 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
785 start_run : OUT std_logic := '0';
786 start_run_ack : IN std_logic;
787 stop_run : OUT std_logic := '0';
788 stop_run_ack : IN std_logic;
789 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
790 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
791 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
792 new_config_ftu : OUT std_logic := '0';
793 new_config_ftu_ack : IN std_logic;
794 new_config_ftu_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
795 );
796 end component;
797
798-- component counter_dummy IS
799-- PORT(
800-- clk : IN std_logic;
801-- get_counter : IN std_logic;
802-- get_counter_started : OUT std_logic := '0';
803-- get_counter_ready : OUT std_logic := '0';
804-- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
805-- );
806-- end component;
807
808 component Timing_counter is
809 port(
810 clk : in STD_LOGIC; -- 50 MHz system clock
811 enable : in STD_LOGIC; -- enable counter
812 reset : in Std_LOGIC; -- reset counter
813 read_counter : in STD_LOGIC; -- read counter
814 reading_started : out STD_LOGIC;
815 reading_valid : out STD_LOGIC; -- counter reading at output ready
816 counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0)
817 );
818 end component;
819
820 component Lightpulser_interface_Basic is
821 port(
822 clk_50 : IN STD_LOGIC;
823 --clk_250 : IN STD_LOGIC;
824 Cal_0_p : out STD_LOGIC := '0';
825 Cal_0_n : out STD_LOGIC := '1';
826 Cal_1_p : out STD_LOGIC := '0';
827 Cal_1_n : out STD_LOGIC := '1';
828 Cal_2_p : out STD_LOGIC := '0';
829 Cal_2_n : out STD_LOGIC := '1';
830 Cal_3_p : out STD_LOGIC := '0';
831 Cal_3_n : out STD_LOGIC := '1';
832 Cal_4_p : out STD_LOGIC := '0';
833 Cal_4_n : out STD_LOGIC := '1';
834 Cal_5_p : out STD_LOGIC := '0';
835 Cal_5_n : out STD_LOGIC := '1';
836 Cal_6_p : out STD_LOGIC := '0';
837 Cal_6_n : out STD_LOGIC := '1';
838 Cal_7_p : out STD_LOGIC := '0';
839 Cal_7_n : out STD_LOGIC := '1';
840 LP1_ampl : in std_logic_vector (15 downto 0);
841 LP2_ampl : in std_logic_vector (15 downto 0);
842 --LP1_delay : in std_logic_vector (15 downto 0);
843 --LP2_delay : in std_logic_vector (15 downto 0);
844 LP1_pulse : in std_logic;
845 LP2_pulse : in std_logic;
846 start_config : in std_logic;
847 config_started : out std_logic := '0';
848 config_done : out std_logic := '0'
849 );
850 end component;
851
852begin
853
854-- -- IBUFG: Single-ended global clock input buffer
855-- -- Spartan-3A
856-- -- Xilinx HDL Language Template, version 11.4
857
858-- IBUFG_inst : IBUFG
859-- generic map (
860-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
861-- -- "0"-"16"
862-- IOSTANDARD => "DEFAULT")
863-- port map (
864-- O => clk_buf_sig, -- Clock buffer output
865-- I => clk -- Clock buffer input (connect directly to top-level port)
866-- );
867
868-- Inst_FTM_clk_gen : FTM_clk_gen
869-- port map(
870-- clk => clk_buf_sig,
871-- rst => reset_sig,
872-- clk_1 => clk_1M_sig,
873-- clk_50 => clk_50M_sig,
874-- clk_250 => clk_250M_sig,
875-- clk_250_ps => clk_250M_ps_sig,
876-- ready => clk_ready_sig
877-- );
878
879 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
880 port map(
881 clk => clk,
882 rst => reset_sig,
883 clk_1 => clk_1M_sig,
884 clk_50 => clk_50M_sig,
885 clk_250 => clk_250M_sig,
886 clk_250_ps => clk_250M_ps_sig,
887 ready => clk_ready_sig
888 );
889
890 Inst_FTM_dna_gen : FTM_dna_gen
891 port map(
892 clk => clk_50M_sig,
893 start => dna_start_sig,
894 dna => dna_sig,
895 ready => dna_ready_sig
896 );
897
898 --differential output buffer for trigger signal
899 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
900 port map(
901 O => TRG_p,
902 OB => TRG_n,
903 I => trigger_signal_sig
904 );
905
906 --differential output buffer for TIM signal
907 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
908 port map(
909 O => TIM_Run_p,
910 OB => TIM_Run_n,
911 I => TIM_signal_sig
912 );
913
914 --differential output buffer for fast reset signal
915 OBUFDS_LVDS_33_RES : OBUFDS_LVDS_33
916 port map(
917 O => RES_p,
918 OB => RES_n,
919 I => '0'
920 );
921
922 Inst_trigger_manager : trigger_manager
923 port map(
924 --clocks
925 clk_50MHz => clk_50M_sig,
926 clk_250MHz => clk_250M_sig,
927 clk_250MHz_180 => clk_250M_ps_sig,
928 --trigger primitives from FTUs
929 trig_prim_0 => Trig_Prim_A, --crate 0
930 trig_prim_1 => Trig_Prim_B, --crate 1
931 trig_prim_2 => Trig_Prim_C, --crate 2
932 trig_prim_3 => Trig_Prim_D, --crate 3
933 --external signals
934 ext_trig_1 => ext_Trig(1),
935 ext_trig_2 => ext_Trig(2),
936 ext_veto => Veto,
937 FAD_busy_0 => Busy0, --crate 0
938 FAD_busy_1 => Busy1, --crate 1
939 FAD_busy_2 => Busy2, --crate 2
940 FAD_busy_3 => Busy3, --crate 3
941 --control signals from e.g. main control
942 start_run => trigger_start_sig, --enable trigger output
943 stop_run => trigger_stop_sig, --disable trigger output
944 new_config => config_trigger_sig,
945 --settings register (see FTM Firmware Specifications)
946 general_settings => general_settings_sig,
947 LP_and_PED_freq => lp_pt_freq_sig,
948 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
949 maj_coinc_n_phys => coin_n_p_sig,
950 maj_coinc_n_calib => coin_n_c_sig,
951 trigger_delay => trigger_delay_sig,
952 TIM_delay => timemarker_delay_sig,
953 dead_time => dead_time_sig,
954 coinc_window_phys => coin_win_p_sig,
955 coinc_window_calib => coin_win_c_sig,
956 active_FTU_list_0 => ftu_active_cr0_sig,
957 active_FTU_list_1 => ftu_active_cr1_sig,
958 active_FTU_list_2 => ftu_active_cr2_sig,
959 active_FTU_list_3 => ftu_active_cr3_sig,
960 --control signals or information for other entities
961 trigger_ID_read => trigger_ID_read_sig,
962 trig_cnt_copy_read => trigger_counter_read_sig,
963 trigger_ID_ready => trigger_ID_ready_sig,
964 trigger_ID => trigger_ID_sig,
965 trig_cnt_copy => trigger_counter_sig, --counter reading
966 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
967 trigger_active => trigger_active_sig, --phys triggers are enabled/active
968 config_done => config_trigger_done_sig,
969 LP1_pulse => LP1_pulse_sig, --send start signal to light pulser 1
970 LP2_pulse => LP2_pulse_sig, --send start signal to light pulser 2
971 --trigger and time marker output signals to FADs
972 trigger_signal => trigger_signal_sig,
973 TIM_signal => TIM_signal_sig
974 );
975
976 Inst_Clock_cond_interface : Clock_cond_interface
977 port map(
978 clk => clk_50M_sig,
979 CLK_Clk_Cond => CLK_Clk_Cond,
980 LE_Clk_Cond => LE_Clk_Cond,
981 DATA_Clk_Cond => DATA_Clk_Cond,
982 SYNC_Clk_Cond => SYNC_Clk_Cond,
983 LD_Clk_Cond => LD_Clk_Cond,
984 TIM_Sel => TIM_Sel,
985 cc_R0 => cc_R0_sig,
986 cc_R1 => cc_R1_sig,
987 cc_R8 => cc_R8_sig,
988 cc_R9 => cc_R9_sig,
989 cc_R11 => cc_R11_sig,
990 cc_R13 => cc_R13_sig,
991 cc_R14 => cc_R14_sig,
992 cc_R15 => cc_R15_sig,
993 start_config => config_start_cc_sig,
994 config_started => config_started_cc_sig,
995 config_done => config_ready_cc_sig,
996 locked => cc_locked_sig,
997 timemarker_select => general_settings_sig(0)
998 );
999
1000 Inst_FTM_central_control : FTM_central_control
1001 port map(
1002 clk => clk_50M_sig,
1003 clk_ready => clk_ready_sig,
1004 clk_scaler => clk_1M_sig,
1005 new_config => new_config_sig,
1006 config_started => config_started_sig,
1007 config_started_ack => config_started_ack_sig,
1008 config_start_eth => config_start_eth_sig,
1009 config_started_eth => config_started_eth_sig,
1010 config_ready_eth => config_ready_eth_sig,
1011 config_start_ftu => config_start_ftu_sig,
1012 config_started_ftu => config_started_ftu_sig,
1013 config_ready_ftu => config_ready_ftu_sig,
1014 ping_ftu_start => ping_ftu_start_sig,
1015 ping_ftu_started => ping_ftu_started_sig,
1016 ping_ftu_ready => ping_ftu_ready_sig,
1017 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
1018 ping_ftu_started_ftu => ping_ftu_started1_sig,
1019 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
1020 rates_ftu => rates_ftu_start_sig,
1021 rates_started_ftu => rates_ftu_started_sig,
1022 rates_ready_ftu => rates_ftu_ready_sig,
1023 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
1024 dd_send => dd_send_sig,
1025 dd_send_ack => dd_send_ack_sig,
1026 dd_send_ready => dd_send_ready_sig,
1027 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1028 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1029 dd_block_start_ftu => dd_block_start_ftu_sig,
1030 config_start_cc => config_start_cc_sig,
1031 config_started_cc => config_started_cc_sig,
1032 config_ready_cc => config_ready_cc_sig,
1033 cc_locked => cc_locked_sig,
1034 config_start_lp => config_start_lp_sig,
1035 config_started_lp => config_started_lp_sig,
1036 config_ready_lp => config_ready_lp_sig,
1037 config_trigger => config_trigger_sig,
1038 config_trigger_done => config_trigger_done_sig,
1039 dna_start => dna_start_sig,
1040 dna_ready => dna_ready_sig,
1041 crate_reset => crate_reset_sig,
1042 crate_reset_ack => crate_reset_ack_sig,
1043 crate_reset_param => crate_reset_param_sig,
1044 start_run => start_run_sig,
1045 start_run_ack => start_run_ack_sig,
1046 stop_run => stop_run_sig,
1047 stop_run_ack => stop_run_ack_sig,
1048 current_cc_state => current_cc_state_sig,
1049 cc_state_test => cc_state_test_sig,
1050 start_run_param => start_run_param_sig,
1051 start_run_num_events => start_run_num_events_sig,
1052 trigger_start => trigger_start_sig,
1053 trigger_stop => trigger_stop_sig,
1054 enable_ID_sending => enable_ID_sending_sig,
1055 reset_timer => reset_timer_sig,
1056 crate_res_0 => crate_res0_sig,
1057 crate_res_1 => crate_res1_sig,
1058 crate_res_2 => crate_res2_sig,
1059 crate_res_3 => crate_res3_sig,
1060 new_config_ftu => new_config_ftu_sig,
1061 new_config_ftu_ack => new_config_ftu_ack_sig,
1062 config_single_FTU => config_single_FTU_sig,
1063 config_single_FTU_started => config_single_FTU_started_sig,
1064 config_single_FTU_done => config_single_FTU_done_sig
1065 );
1066
1067 Inst_FTM_ftu_control : FTM_ftu_control
1068 port map(
1069 clk_50MHz => clk_50M_sig,
1070 rx_en => Bus1_Rx_En,
1071 tx_en => Bus1_Tx_En,
1072 rx_d_0 => Bus1_RxD_0,
1073 tx_d_0 => Bus1_TxD_0,
1074 rx_d_1 => Bus1_RxD_1,
1075 tx_d_1 => Bus1_TxD_1,
1076 rx_d_2 => Bus1_RxD_2,
1077 tx_d_2 => Bus1_TxD_2,
1078 rx_d_3 => Bus1_RxD_3,
1079 tx_d_3 => Bus1_TxD_3,
1080 new_config => config_start_ftu_sig,
1081 ping_all => ping_ftu_start_ftu_sig,
1082 read_rates => rates_ftu_start_sig,
1083 config_single_FTU => config_single_FTU_sig,
1084 read_rates_started => rates_ftu_started_sig,
1085 read_rates_done => rates_ftu_ready_sig,
1086 new_config_started => config_started_ftu_sig,
1087 new_config_done => config_ready_ftu_sig,
1088 ping_all_started => ping_ftu_started1_sig,
1089 ping_all_done => ping_ftu_ready1_sig,
1090 config_single_FTU_started => config_single_FTU_started_sig,
1091 config_single_FTU_done => config_single_FTU_done_sig,
1092 ftu_active_cr0 => ftu_active_cr0_sig,
1093 ftu_active_cr1 => ftu_active_cr1_sig,
1094 ftu_active_cr2 => ftu_active_cr2_sig,
1095 ftu_active_cr3 => ftu_active_cr3_sig,
1096 config_single_FTU_param => new_config_ftu_param_sig,
1097 ftu_error_calls => ftu_error_calls_sig,
1098 ftu_error_data => ftu_error_data_sig,
1099 ftu_error_send => ftu_error_send_sig,
1100 ftu_error_send_ack => ftu_error_send_ack_sig,
1101 ftu_error_send_ready=> ftu_error_send_ready_sig,
1102 static_RAM_busy => sd_busy_sig,
1103 static_RAM_started => sd_started_ftu_sig,
1104 static_RAM_ready => sd_ready_sig,
1105 data_static_RAM => sd_data_out_ftu_sig,
1106 read_static_RAM => sd_read_ftu_sig,
1107 addr_static_RAM => sd_addr_ftu_sig,
1108 dynamic_RAM_busy => dd_busy_sig,
1109 dynamic_RAM_started => dd_started_ftu_sig,
1110 dynamic_RAM_ready => dd_ready_sig,
1111 data_dynamic_RAM => dd_data_sig,
1112 write_dynamic_RAM => dd_write_sig,
1113 addr_dynamic_RAM => dd_addr_sig,
1114 FTUlist_RAM_busy => fl_busy_sig,
1115 FTUlist_RAM_started => fl_started_ftu_sig,
1116 FTUlist_RAM_ready => fl_ready_sig,
1117 data_FTUlist_RAM => fl_data_sig,
1118 write_FTUlist_RAM => fl_write_sig,
1119 addr_FTUlist_RAM => fl_addr_sig
1120 );
1121
1122 Inst_FTM_fad_broadcast : FTM_fad_broadcast
1123 port map(
1124 clk_50MHz => clk_50M_sig,
1125 rx_en => Bus2_Rx_En,
1126 tx_en => Bus2_Tx_En,
1127 rx_d_0 => Bus2_RxD_0,
1128 tx_d_0 => Bus2_TxD_0,
1129 rx_d_1 => Bus2_RxD_1,
1130 tx_d_1 => Bus2_TxD_1,
1131 rx_d_2 => Bus2_RxD_2,
1132 tx_d_2 => Bus2_TxD_2,
1133 rx_d_3 => Bus2_RxD_3,
1134 tx_d_3 => Bus2_TxD_3,
1135 enable_ID_sending => enable_ID_sending_sig,
1136 TIM_source => general_settings_sig(0),
1137 LP_settings => "0000",
1138 trigger_ID_ready => trigger_ID_ready_sig,
1139 trigger_ID => trigger_ID_sig,
1140 trigger_ID_read => trigger_ID_read_sig
1141 );
1142
1143 Inst_ethernet_modul : ethernet_modul
1144 port map(
1145 wiz_reset => W_RES,
1146 wiz_addr => W_A,
1147 wiz_data => W_D,
1148 wiz_cs => W_CS,
1149 wiz_wr => W_WR,
1150 wiz_rd => W_RD,
1151 wiz_int => W_INT,
1152 clk => clk_50M_sig,
1153 sd_ready => sd_ready_sig,
1154 sd_busy => sd_busy_sig,
1155 led => led_sig,
1156 sd_read_ftu => sd_read_ftu_sig,
1157 sd_started_ftu => sd_started_ftu_sig,
1158 cc_R0 => cc_R0_sig,
1159 cc_R1 => cc_R1_sig,
1160 cc_R11 => cc_R11_sig,
1161 cc_R13 => cc_R13_sig,
1162 cc_R14 => cc_R14_sig,
1163 cc_R15 => cc_R15_sig,
1164 cc_R8 => cc_R8_sig,
1165 cc_R9 => cc_R9_sig,
1166 coin_n_c => coin_n_c_sig,
1167 coin_n_p => coin_n_p_sig,
1168 dead_time => dead_time_sig,
1169 general_settings => general_settings_sig,
1170 lp1_amplitude => lp1_amplitude_sig,
1171 lp1_delay => lp1_delay_sig,
1172 lp2_amplitude => lp2_amplitude_sig,
1173 lp2_delay => lp2_delay_sig,
1174 lp_pt_freq => lp_pt_freq_sig,
1175 lp_pt_ratio => lp_pt_ratio_sig,
1176 timemarker_delay => timemarker_delay_sig,
1177 trigger_delay => trigger_delay_sig,
1178 sd_addr_ftu => sd_addr_ftu_sig,
1179 sd_data_out_ftu => sd_data_out_ftu_sig,
1180 ftu_active_cr0 => ftu_active_cr0_sig,
1181 ftu_active_cr1 => ftu_active_cr1_sig,
1182 ftu_active_cr2 => ftu_active_cr2_sig,
1183 ftu_active_cr3 => ftu_active_cr3_sig,
1184 new_config => new_config_sig,
1185 config_started => config_started_sig,
1186 config_start_eth => config_start_eth_sig,
1187 config_started_eth => config_started_eth_sig,
1188 config_ready_eth => config_ready_eth_sig,
1189 config_started_ack => config_started_ack_sig,
1190 fl_busy => fl_busy_sig,
1191 fl_ready => fl_ready_sig,
1192 fl_write_ftu => fl_write_sig,
1193 fl_started_ftu => fl_started_ftu_sig,
1194 fl_addr_ftu => fl_addr_sig,
1195 fl_data_in_ftu => fl_data_sig,
1196 ping_ftu_start => ping_ftu_start_sig,
1197 ping_ftu_started => ping_ftu_started_sig,
1198 ping_ftu_ready => ping_ftu_ready_sig,
1199 dd_write_ftu => dd_write_sig,
1200 dd_started_ftu => dd_started_ftu_sig,
1201 dd_data_in_ftu => dd_data_sig,
1202 dd_addr_ftu => dd_addr_sig,
1203 dd_busy => dd_busy_sig,
1204 dd_ready => dd_ready_sig,
1205 coin_win_c => coin_win_c_sig,
1206 coin_win_p => coin_win_p_sig,
1207 --new stuff
1208 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1209 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1210 dd_block_start_ftu => dd_block_start_ftu_sig,
1211 dd_send => dd_send_sig,
1212 dd_send_ack => dd_send_ack_sig,
1213 dd_send_ready => dd_send_ready_sig,
1214 --very new stuff
1215 ftu_error_calls => ftu_error_calls_sig,
1216 ftu_error_data => ftu_error_data_sig,
1217 ftu_error_send => ftu_error_send_sig,
1218 ftu_error_send_ack => ftu_error_send_ack_sig,
1219 ftu_error_send_ready => ftu_error_send_ready_sig,
1220 prescaling_FTU01 => prescaling_FTU01_sig,
1221 trigger_counter => trigger_counter_sig,
1222 trigger_counter_read => trigger_counter_read_sig,
1223 trigger_counter_valid => trigger_counter_valid_sig,
1224 --newest stuff
1225 board_id => dna_sig,
1226 get_ts_counter => get_ts_counter_sig,
1227 get_ts_counter_ready => get_ts_counter_ready_sig,
1228 get_ts_counter_started => get_ts_counter_started_sig,
1229 timestamp_counter => timestamp_counter_sig,
1230 get_ot_counter => get_ot_counter_sig,
1231 get_ot_counter_ready => get_ot_counter_ready_sig,
1232 get_ot_counter_started => get_ot_counter_started_sig,
1233 on_time_counter => on_time_counter_sig,
1234 temp_sensor_array => (35, 45, 55, 65),
1235 temp_sensor_ready => '1',
1236 crate_reset => crate_reset_sig,
1237 crate_reset_ack => crate_reset_ack_sig,
1238 crate_reset_param => crate_reset_param_sig,
1239 start_run => start_run_sig,
1240 start_run_ack => start_run_ack_sig,
1241 stop_run => stop_run_sig,
1242 stop_run_ack => stop_run_ack_sig,
1243 current_cc_state => current_cc_state_sig,
1244 start_run_param => start_run_param_sig,
1245 start_run_num_events => start_run_num_events_sig,
1246 new_config_ftu => new_config_ftu_sig,
1247 new_config_ftu_ack => new_config_ftu_ack_sig,
1248 new_config_ftu_param => new_config_ftu_param_sig
1249 );
1250
1251-- Inst_counter_dummy_ts : counter_dummy
1252-- port map(
1253-- clk => clk_50M_sig,
1254-- get_counter => get_ts_counter_sig,
1255-- get_counter_started => get_ts_counter_started_sig,
1256-- get_counter_ready => get_ts_counter_ready_sig,
1257-- counter => timestamp_counter_sig
1258-- );
1259
1260-- Inst_counter_dummy_ot : counter_dummy
1261-- port map(
1262-- clk => clk_50M_sig,
1263-- get_counter => get_ot_counter_sig,
1264-- get_counter_started => get_ot_counter_started_sig,
1265-- get_counter_ready => get_ot_counter_ready_sig,
1266-- counter => on_time_counter_sig
1267-- );
1268
1269 Inst_Timing_counter_ts : Timing_counter
1270 port map(
1271 clk => clk_50M_sig,
1272 enable => '1',
1273 reset => reset_timer_sig,
1274 read_counter => get_ts_counter_sig,
1275 reading_started => get_ts_counter_started_sig,
1276 reading_valid => get_ts_counter_ready_sig,
1277 counter_reading => timestamp_counter_sig
1278 );
1279
1280 Inst_Timing_counter_ot : Timing_counter
1281 port map(
1282 clk => clk_50M_sig,
1283 enable => trigger_active_sig,
1284 reset => reset_timer_sig,
1285 read_counter => get_ot_counter_sig,
1286 reading_started => get_ot_counter_started_sig,
1287 reading_valid => get_ot_counter_ready_sig,
1288 counter_reading => on_time_counter_sig
1289 );
1290
1291 Inst_Lightpulser_interface_Basic : Lightpulser_interface_Basic
1292 port map (
1293 clk_50 => clk_50M_sig,
1294 --clk_250 => clk_250M_sig,
1295 Cal_0_p => Cal_2_p, --swapped with Cal_2_p due to connector on FLD board
1296 Cal_0_n => Cal_2_n, --swapped with Cal_2_n due to connector on FLD board
1297 Cal_1_p => Cal_1_p,
1298 Cal_1_n => Cal_1_n,
1299 Cal_2_p => Cal_0_p, --swapped with Cal_0_p due to connector on FLD board
1300 Cal_2_n => Cal_0_n, --swapped with Cal_0_n due to connector on FLD board
1301 Cal_3_p => Cal_3_p,
1302 Cal_3_n => Cal_3_n,
1303 Cal_4_p => Cal_6_p, --swapped with Cal_6_p due to connector on FLD board
1304 Cal_4_n => Cal_6_n, --swapped with Cal_6_n due to connector on FLD board
1305 Cal_5_p => Cal_5_p,
1306 Cal_5_n => Cal_5_n,
1307 Cal_6_p => Cal_4_p, --swapped with Cal_4_p due to connector on FLD board
1308 Cal_6_n => Cal_4_n, --swapped with Cal_4_n due to connector on FLD board
1309 Cal_7_p => Cal_7_p,
1310 Cal_7_n => Cal_7_n,
1311 LP1_ampl => lp1_amplitude_sig,
1312 LP2_ampl => lp2_amplitude_sig,
1313 --LP1_delay => lp1_delay_sig,
1314 --LP2_delay => lp2_delay_sig,
1315 LP1_pulse => LP1_pulse_sig,
1316 LP2_pulse => LP2_pulse_sig,
1317 start_config => config_start_lp_sig,
1318 config_started => config_started_lp_sig,
1319 config_done => config_ready_lp_sig
1320 );
1321
1322 LED_red <= led_sig(3 downto 0);
1323 LED_ye <= led_sig(5 downto 4);
1324 LED_gn <= led_sig(7 downto 6);
1325
1326 TP(32 downto 8) <= (others => '0');
1327 --TP(8) <= clk_50M_sig;
1328 TP( 7 downto 0) <= cc_state_test_sig;
1329
1330 Crate_Res0 <= crate_res0_sig;
1331 Crate_Res1 <= crate_res1_sig;
1332 Crate_Res2 <= crate_res2_sig;
1333 Crate_Res3 <= crate_res3_sig;
1334
1335end Behavioral;
1336
1337
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