source: firmware/FTM/FTM_top.vhd@ 10231

Last change on this file since 10231 was 10227, checked in by weitzel, 15 years ago
first version of FTM firmware including ethernet and FTU interface; still some debugging needed
File size: 27.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 -- Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 -- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 -- LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 -- DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 -- SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 -- LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 -- Bus2_TxD_0 : out STD_LOGIC;
153
154 -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 -- Bus2_TxD_1 : out STD_LOGIC;
156
157 -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 -- Bus2_TxD_2 : out STD_LOGIC;
159
160 -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 -- Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 -- Crate_Res0 : out STD_LOGIC;
180 -- Crate_Res1 : out STD_LOGIC;
181 -- Crate_Res2 : out STD_LOGIC;
182 -- Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 -- Busy0 : in STD_LOGIC;
189 -- Busy1 : in STD_LOGIC;
190 -- Busy2 : in STD_LOGIC;
191 -- Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 -- RES_p : out STD_LOGIC; -- RES+ Reset
215 -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 -- TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 -- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 -- TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 -- Cal_0_p : out STD_LOGIC;
233 -- Cal_0_n : out STD_LOGIC;
234 -- Cal_1_p : out STD_LOGIC;
235 -- Cal_1_n : out STD_LOGIC;
236 -- Cal_2_p : out STD_LOGIC;
237 -- Cal_2_n : out STD_LOGIC;
238 -- Cal_3_p : out STD_LOGIC;
239 -- Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 -- Cal_4_p : out STD_LOGIC;
244 -- Cal_4_n : out STD_LOGIC;
245 -- Cal_5_p : out STD_LOGIC;
246 -- Cal_5_n : out STD_LOGIC;
247 -- Cal_6_p : out STD_LOGIC;
248 -- Cal_6_n : out STD_LOGIC;
249 -- Cal_7_p : out STD_LOGIC;
250 -- Cal_7_n : out STD_LOGIC
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal dd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
324 signal dd_busy_sig : std_logic;
325 signal dd_data_in_ftu_sig : std_logic_vector(15 DOWNTO 0);
326 signal dd_ready_sig : std_logic;
327 signal dd_started_ftu_sig : std_logic := '0';
328 signal dd_write_ftu_sig : std_logic;
329 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
330 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
331
332 signal clk_buf_sig : std_logic;
333 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
334 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
335 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
336 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
337 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
338
339 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
340
341 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
342
343 component FTM_clk_gen
344 port(
345 clk : IN STD_LOGIC;
346 rst : IN STD_LOGIC;
347 clk_1 : OUT STD_LOGIC;
348 clk_50 : OUT STD_LOGIC;
349 clk_250 : OUT STD_LOGIC;
350 clk_250_ps : OUT STD_LOGIC;
351 ready : OUT STD_LOGIC
352 );
353 end component;
354
355 component FTM_central_control
356 port(
357 clk : IN std_logic ;
358 new_config : IN std_logic ;
359 config_started : OUT std_logic := '0';
360 config_started_ack : IN std_logic ;
361 config_start_eth : OUT std_logic := '0';
362 config_started_eth : IN std_logic ;
363 config_ready_eth : IN std_logic ;
364 config_start_ftu : OUT std_logic := '0';
365 config_started_ftu : IN std_logic ;
366 config_ready_ftu : IN std_logic ;
367 ping_ftu_start : IN std_logic ;
368 ping_ftu_started : OUT std_logic := '0';
369 ping_ftu_ready : OUT std_logic := '0';
370 ping_ftu_start_ftu : OUT std_logic := '0';
371 ping_ftu_started_ftu : IN std_logic ;
372 ping_ftu_ready_ftu : IN std_logic
373 );
374 end component;
375
376 component FTM_ftu_control
377 port(
378 clk_50MHz : in std_logic;
379 rx_en : out STD_LOGIC;
380 tx_en : out STD_LOGIC;
381 rx_d_0 : in STD_LOGIC;
382 tx_d_0 : out STD_LOGIC;
383 rx_d_1 : in STD_LOGIC;
384 tx_d_1 : out STD_LOGIC;
385 rx_d_2 : in STD_LOGIC;
386 tx_d_2 : out STD_LOGIC;
387 rx_d_3 : in STD_LOGIC;
388 tx_d_3 : out STD_LOGIC;
389 new_config : in std_logic;
390 ping_all : in std_logic;
391 read_rates : in std_logic;
392 read_rates_started : out std_logic := '0';
393 read_rates_done : out std_logic := '0';
394 new_config_started : out std_logic := '0';
395 new_config_done : out std_logic := '0';
396 ping_all_started : out std_logic := '0';
397 ping_all_done : out std_logic := '0';
398 ftu_active_cr0 : in std_logic_vector (15 downto 0);
399 ftu_active_cr1 : in std_logic_vector (15 downto 0);
400 ftu_active_cr2 : in std_logic_vector (15 downto 0);
401 ftu_active_cr3 : in std_logic_vector (15 downto 0);
402 static_RAM_busy : in std_logic;
403 static_RAM_started : in std_logic;
404 static_RAM_ready : in std_logic;
405 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
406 read_static_RAM : out std_logic := '0';
407 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
408 dynamic_RAM_busy : in std_logic;
409 dynamic_RAM_started : in std_logic;
410 dynamic_RAM_ready : in std_logic;
411 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
412 write_dynamic_RAM : out std_logic := '0';
413 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
414 FTUlist_RAM_busy : in std_logic;
415 FTUlist_RAM_started : in std_logic;
416 FTUlist_RAM_ready : in std_logic;
417 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
418 write_FTUlist_RAM : out std_logic := '0';
419 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
420 );
421 end component;
422
423 component ethernet_modul
424 port(
425 wiz_reset : OUT std_logic := '1';
426 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
427 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
428 wiz_cs : OUT std_logic := '1';
429 wiz_wr : OUT std_logic := '1';
430 wiz_rd : OUT std_logic := '1';
431 wiz_int : IN std_logic ;
432 clk : IN std_logic ;
433 sd_ready : OUT std_logic ;
434 sd_busy : OUT std_logic ;
435 led : OUT std_logic_vector (7 DOWNTO 0);
436 sd_read_ftu : IN std_logic ;
437 sd_started_ftu : OUT std_logic := '0';
438 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
439 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
440 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
441 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
442 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
443 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
444 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
445 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
446 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
447 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
448 dead_time : OUT std_logic_vector (15 DOWNTO 0);
449 general_settings : OUT std_logic_vector (15 DOWNTO 0);
450 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
451 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
452 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
453 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
454 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
455 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
456 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
457 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
458 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
459 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
460 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
461 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
462 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
463 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
464 new_config : OUT std_logic := '0';
465 config_started : IN std_logic ;
466 config_start_eth : IN std_logic ;
467 config_started_eth : OUT std_logic := '0';
468 config_ready_eth : OUT std_logic := '0';
469 config_started_ack : OUT std_logic := '0';
470 fl_busy : OUT std_logic ;
471 fl_ready : OUT std_logic ;
472 fl_write_ftu : IN std_logic ;
473 fl_started_ftu : OUT std_logic := '0';
474 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
475 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
476 ping_ftu_start : OUT std_logic := '0';
477 ping_ftu_started : IN std_logic ;
478 ping_ftu_ready : IN std_logic ;
479 dd_write_ftu : IN std_logic ;
480 dd_started_ftu : OUT std_logic := '0';
481 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
482 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
483 dd_busy : OUT std_logic ;
484 dd_ready : OUT std_logic ;
485 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
486 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
487 );
488 end component;
489
490begin
491
492 -- IBUFG: Single-ended global clock input buffer
493 -- Spartan-3A
494 -- Xilinx HDL Language Template, version 11.4
495
496 IBUFG_inst : IBUFG
497 generic map (
498 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
499 -- "0"-"16"
500 IOSTANDARD => "DEFAULT")
501 port map (
502 O => clk_buf_sig, -- Clock buffer output
503 I => clk -- Clock buffer input (connect directly to top-level port)
504 );
505
506 Inst_FTM_clk_gen : FTM_clk_gen
507 port map(
508 clk => clk_buf_sig,
509 rst => reset_sig,
510 clk_1 => clk_1M_sig,
511 clk_50 => clk_50M_sig,
512 clk_250 => clk_250M_sig,
513 clk_250_ps => clk_250M_ps_sig,
514 ready => clk_ready_sig
515 );
516
517 Inst_FTM_central_control : FTM_central_control
518 port map(
519 clk => clk_50M_sig,
520 new_config => new_config_sig,
521 config_started => config_started_sig,
522 config_started_ack => config_started_ack_sig,
523 config_start_eth => config_start_eth_sig,
524 config_started_eth => config_started_eth_sig,
525 config_ready_eth => config_ready_eth_sig,
526 config_start_ftu => config_start_ftu_sig,
527 config_started_ftu => config_started_ftu_sig,
528 config_ready_ftu => config_ready_ftu_sig,
529 ping_ftu_start => ping_ftu_start_sig,
530 ping_ftu_started => ping_ftu_started_sig,
531 ping_ftu_ready => ping_ftu_ready_sig,
532 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
533 ping_ftu_started_ftu => ping_ftu_started1_sig,
534 ping_ftu_ready_ftu => ping_ftu_ready1_sig
535 );
536
537 Inst_FTM_ftu_control : FTM_ftu_control
538 port map(
539 clk_50MHz => clk_50M_sig,
540 rx_en => Bus1_Rx_En,
541 tx_en => Bus1_Tx_En,
542 rx_d_0 => Bus1_RxD_0,
543 tx_d_0 => Bus1_TxD_0,
544 rx_d_1 => Bus1_RxD_1,
545 tx_d_1 => Bus1_TxD_1,
546 rx_d_2 => Bus1_RxD_2,
547 tx_d_2 => Bus1_TxD_2,
548 rx_d_3 => Bus1_RxD_3,
549 tx_d_3 => Bus1_TxD_3,
550 new_config => config_start_ftu_sig,
551 ping_all => ping_ftu_start_ftu_sig,
552 read_rates => rates_ftu_start_sig,
553 read_rates_started => rates_ftu_started_sig,
554 read_rates_done => rates_ftu_ready_sig,
555 new_config_started => config_started_ftu_sig,
556 new_config_done => config_ready_ftu_sig,
557 ping_all_started => ping_ftu_started1_sig,
558 ping_all_done => ping_ftu_ready1_sig,
559 ftu_active_cr0 => ftu_active_cr0_sig,
560 ftu_active_cr1 => ftu_active_cr1_sig,
561 ftu_active_cr2 => ftu_active_cr2_sig,
562 ftu_active_cr3 => ftu_active_cr3_sig,
563 static_RAM_busy => sd_busy_sig,
564 static_RAM_started => sd_started_ftu_sig,
565 static_RAM_ready => sd_ready_sig,
566 data_static_RAM => sd_data_out_ftu_sig,
567 read_static_RAM => sd_read_ftu_sig,
568 addr_static_RAM => sd_addr_ftu_sig,
569 dynamic_RAM_busy => dd_busy_sig,
570 dynamic_RAM_started => dd_started_ftu_sig,
571 dynamic_RAM_ready => dd_ready_sig,
572 data_dynamic_RAM => dd_data_in_ftu_sig,
573 write_dynamic_RAM => dd_write_ftu_sig,
574 addr_dynamic_RAM => dd_addr_ftu_sig,
575 FTUlist_RAM_busy => fl_busy_sig,
576 FTUlist_RAM_started => fl_started_ftu_sig,
577 FTUlist_RAM_ready => fl_ready_sig,
578 data_FTUlist_RAM => fl_data_sig,
579 write_FTUlist_RAM => fl_write_sig,
580 addr_FTUlist_RAM => fl_addr_sig
581 );
582
583 Inst_ethernet_modul : ethernet_modul
584 port map(
585 wiz_reset => W_RES,
586 wiz_addr => W_A,
587 wiz_data => W_D,
588 wiz_cs => W_CS,
589 wiz_wr => W_WR,
590 wiz_rd => W_RD,
591 wiz_int => W_INT,
592 clk => clk_50M_sig,
593 sd_ready => sd_ready_sig,
594 sd_busy => sd_busy_sig,
595 led => led_sig,
596 sd_read_ftu => sd_read_ftu_sig,
597 sd_started_ftu => sd_started_ftu_sig,
598 cc_R0 => cc_R0_sig,
599 cc_R1 => cc_R1_sig,
600 cc_R11 => cc_R11_sig,
601 cc_R13 => cc_R13_sig,
602 cc_R14 => cc_R14_sig,
603 cc_R15 => cc_R15_sig,
604 cc_R8 => cc_R8_sig,
605 cc_R9 => cc_R9_sig,
606 coin_n_c => coin_n_c_sig,
607 coin_n_p => coin_n_p_sig,
608 dead_time => dead_time_sig,
609 general_settings => general_settings_sig,
610 lp1_amplitude => lp1_amplitude_sig,
611 lp1_delay => lp1_delay_sig,
612 lp2_amplitude => lp2_amplitude_sig,
613 lp2_delay => lp2_delay_sig,
614 lp_pt_freq => lp_pt_freq_sig,
615 lp_pt_ratio => lp_pt_ratio_sig,
616 timemarker_delay => timemarker_delay_sig,
617 trigger_delay => trigger_delay_sig,
618 sd_addr_ftu => sd_addr_ftu_sig,
619 sd_data_out_ftu => sd_data_out_ftu_sig,
620 ftu_active_cr0 => ftu_active_cr0_sig,
621 ftu_active_cr1 => ftu_active_cr1_sig,
622 ftu_active_cr2 => ftu_active_cr2_sig,
623 ftu_active_cr3 => ftu_active_cr3_sig,
624 new_config => new_config_sig,
625 config_started => config_started_sig,
626 config_start_eth => config_start_eth_sig,
627 config_started_eth => config_started_eth_sig,
628 config_ready_eth => config_ready_eth_sig,
629 config_started_ack => config_started_ack_sig,
630 fl_busy => fl_busy_sig,
631 fl_ready => fl_ready_sig,
632 fl_write_ftu => fl_write_sig,
633 fl_started_ftu => fl_started_ftu_sig,
634 fl_addr_ftu => fl_addr_sig,
635 fl_data_in_ftu => fl_data_sig,
636 ping_ftu_start => ping_ftu_start_sig,
637 ping_ftu_started => ping_ftu_started_sig,
638 ping_ftu_ready => ping_ftu_ready_sig,
639 dd_write_ftu => dd_write_ftu_sig,
640 dd_started_ftu => dd_started_ftu_sig,
641 dd_data_in_ftu => dd_data_in_ftu_sig,
642 dd_addr_ftu => dd_addr_ftu_sig,
643 dd_busy => dd_busy_sig,
644 dd_ready => dd_ready_sig,
645 coin_win_c => coin_win_c_sig,
646 coin_win_p => coin_win_p_sig
647 );
648
649 LED_red <= led_sig(3 downto 0);
650 LED_ye <= led_sig(5 downto 4);
651 LED_gn <= led_sig(7 downto 6);
652
653end Behavioral;
654
655
656
657
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