---------------------------------------------------------------------------------- -- Company: ETH Zurich, Institute for Particle Physics -- Engineer: P. Vogler, Q. Weitzel -- -- Create Date: 08 December 2010 -- Design Name: -- Module Name: FTM_top - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Top level entity for FTM firmware -- -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library ftm_definitions; USE ftm_definitions.ftm_array_types.all; USE ftm_definitions.ftm_constants.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity FTM_top is port( -- Clock clk : IN STD_LOGIC; -- external clock from oscillator U47 -- connection to the WIZnet W5300 ethernet controller -- on IO-Bank 1 ------------------------------------------------------------------------------- -- W5300 data bus W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 -- W5300 address bus W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because -- the W5300 is operated in the -- 16-bit mode -- -> W_A<0> assigned to unconnected pin -- W5300 control signals -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 -- W_CS is also routed to testpoint JP7 W_CS : out STD_LOGIC := '1'; -- W5300 chip select W_INT : IN STD_LOGIC; -- interrupt W_RD : out STD_LOGIC := '1'; -- read W_WR : out STD_LOGIC := '1'; -- write W_RES : out STD_LOGIC := '1'; -- reset W5300 chip -- W5300 buffer ready indicator -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); -- testpoints (T18) associated with the W5300 on IO-bank 1 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0); -- SPI Interface -- connection to the EEPROM U36 (AL25L016M) and -- temperature sensors U45, U46, U48 and U49 (all MAX6662) -- on IO-Bank 1 ------------------------------------------------------------------------------- -- S_CLK : out STD_LOGIC; -- SPI clock -- EEPROM -- MOSI : out STD_LOGIC; -- master out slave in -- MISO : in STD_LOGIC; -- master in slave out -- EE_CS : out STD_LOGIC; -- EEPROM chip select -- temperature sensors U45, U46, U48 and U49 -- SIO : inout STD_LOGIC; -- serial IO -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select -- Trigger primitives inputs -- on IO-Bank 2 ------------------------------------------------------------------------------- -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 -- NIM inputs ------------------------------------------------------------------------------ -- on IO-Bank 3 -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input -- Veto : in STD_LOGIC; -- trigger veto input -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs -- on IO-Bank 0 -- alternative external clock input for FPGA -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available -- LEDs on IO-Banks 0 and 3 ------------------------------------------------------------------------------- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green -- Clock conditioner LMK03000 -- on IO-Bank 3 ------------------------------------------------------------------------------- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for -- various RS-485 Interfaces -- on IO-Bank 3 ------------------------------------------------------------------------------- -- Bus 1: FTU slow control Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable Bus1_RxD_0 : in STD_LOGIC; -- crate 0 Bus1_TxD_0 : out STD_LOGIC; Bus1_RxD_1 : in STD_LOGIC; -- crate 1 Bus1_TxD_1 : out STD_LOGIC; Bus1_RxD_2 : in STD_LOGIC; -- crate 2 Bus1_TxD_2 : out STD_LOGIC; Bus1_RxD_3 : in STD_LOGIC; -- crate 3 Bus1_TxD_3 : out STD_LOGIC; -- Bus 2: Trigger-ID to FAD boards -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 -- Bus2_TxD_0 : out STD_LOGIC; -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 -- Bus2_TxD_1 : out STD_LOGIC; -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 -- Bus2_TxD_2 : out STD_LOGIC; -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 -- Bus2_TxD_3 : out STD_LOGIC; -- auxiliary access -- Aux_Rx_D : in STD_LOGIC; -- Aux_Tx_D : out STD_LOGIC; -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) -- TrID_Rx_D : in STD_LOGIC; -- TrID_Tx_D : out STD_LOGIC; -- Crate-Resets -- on IO-Bank 3 ------------------------------------------------------------------------------- -- Crate_Res0 : out STD_LOGIC; -- Crate_Res1 : out STD_LOGIC; -- Crate_Res2 : out STD_LOGIC; -- Crate_Res3 : out STD_LOGIC; -- Busy signals from the FAD boards -- on IO-Bank 3 ------------------------------------------------------------------------------- -- Busy0 : in STD_LOGIC; -- Busy1 : in STD_LOGIC; -- Busy2 : in STD_LOGIC; -- Busy3 : in STD_LOGIC; -- NIM outputs -- on IO-Bank 0 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage ------------------------------------------------------------------------------- -- calibration -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- -- auxiliarry / spare NIM outputs -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- -- fast control signal outputs -- LVDS output at the FPGA followed by LVDS to NIM conversion stage ------------------------------------------------------------------------------- -- RES_p : out STD_LOGIC; -- RES+ Reset -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 -- TRG_p : out STD_LOGIC; -- TRG+ Trigger -- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA -- LVDS calibration outputs -- on IO-Bank 0 ------------------------------------------------------------------------------- -- to connector J13 -- for light pulsar in the mirror dish -- Cal_0_p : out STD_LOGIC; -- Cal_0_n : out STD_LOGIC; -- Cal_1_p : out STD_LOGIC; -- Cal_1_n : out STD_LOGIC; -- Cal_2_p : out STD_LOGIC; -- Cal_2_n : out STD_LOGIC; -- Cal_3_p : out STD_LOGIC; -- Cal_3_n : out STD_LOGIC; -- to connector J12 -- for light pulsar inside shutter -- Cal_4_p : out STD_LOGIC; -- Cal_4_n : out STD_LOGIC; -- Cal_5_p : out STD_LOGIC; -- Cal_5_n : out STD_LOGIC; -- Cal_6_p : out STD_LOGIC; -- Cal_6_n : out STD_LOGIC; -- Cal_7_p : out STD_LOGIC; -- Cal_7_n : out STD_LOGIC -- Testpoints ------------------------------------------------------------------------------- -- TP : inout STD_LOGIC_VECTOR(32 downto 0); -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only -- Board ID - inputs -- local board-ID "solder programmable" -- all on 'input only' pins ------------------------------------------------------------------------------- -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only ); end FTM_top; architecture Behavioral of FTM_top is signal cc_R0_sig : std_logic_vector(31 DOWNTO 0); signal cc_R1_sig : std_logic_vector(31 DOWNTO 0); signal cc_R11_sig : std_logic_vector(31 DOWNTO 0); signal cc_R13_sig : std_logic_vector(31 DOWNTO 0); signal cc_R14_sig : std_logic_vector(31 DOWNTO 0); signal cc_R15_sig : std_logic_vector(31 DOWNTO 0); signal cc_R8_sig : std_logic_vector(31 DOWNTO 0); signal cc_R9_sig : std_logic_vector(31 DOWNTO 0); signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0); signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0); signal dead_time_sig : std_logic_vector(15 DOWNTO 0); signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0); signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0); signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0); signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0); signal general_settings_sig : std_logic_vector(15 DOWNTO 0); signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0); signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0); signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0); signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0); signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0); signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0); signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0); signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0); signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0); signal sd_busy_sig : std_logic; signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); signal sd_read_ftu_sig : std_logic; signal sd_ready_sig : std_logic; signal sd_started_ftu_sig : std_logic := '0'; signal new_config_sig : std_logic := '0'; signal config_started_sig : std_logic := '0'; signal config_start_eth_sig : std_logic := '0'; signal config_started_eth_sig : std_logic := '0'; signal config_ready_eth_sig : std_logic := '0'; signal config_started_ack_sig : std_logic := '0'; signal ping_ftu_start_sig : std_logic := '0'; signal ping_ftu_started_sig : std_logic := '0'; signal ping_ftu_ready_sig : std_logic := '0'; signal config_start_ftu_sig : std_logic := '0'; signal config_started_ftu_sig : std_logic := '0'; signal config_ready_ftu_sig : std_logic := '0'; signal rates_ftu_start_sig : std_logic := '0'; signal rates_ftu_started_sig : std_logic := '0'; signal rates_ftu_ready_sig : std_logic := '0'; signal fl_busy_sig : std_logic; signal fl_ready_sig : std_logic; signal fl_write_sig : std_logic := '0'; signal fl_started_ftu_sig : std_logic := '0'; signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); signal ping_ftu_start_ftu_sig : std_logic := '0'; signal ping_ftu_started1_sig : std_logic := '0'; signal ping_ftu_ready1_sig : std_logic := '0'; signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); --new or changed stuff signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); signal dd_block_start_sig : std_logic := '0'; signal dd_block_start_ack_ftu_sig : std_logic := '0'; signal dd_block_ready_sig : std_logic := '0'; signal dd_busy_sig : std_logic; signal dd_write_sig : std_logic := '0'; signal dd_started_ftu_sig : std_logic := '0'; signal dd_ready_sig : std_logic; signal dd_send_sig : std_logic := '1'; signal dd_send_ack_sig : std_logic := '1'; signal dd_send_ready_sig : std_logic := '1'; signal config_start_cc_sig : std_logic := '0'; signal config_started_cc_sig : std_logic := '0'; signal config_ready_cc_sig : std_logic := '0'; signal clk_buf_sig : std_logic; signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); component FTM_clk_gen port( clk : IN STD_LOGIC; rst : IN STD_LOGIC; clk_1 : OUT STD_LOGIC; clk_50 : OUT STD_LOGIC; clk_250 : OUT STD_LOGIC; clk_250_ps : OUT STD_LOGIC; ready : OUT STD_LOGIC ); end component; component Clock_cond_interface is port( clk : IN STD_LOGIC; CLK_Clk_Cond : out STD_LOGIC; LE_Clk_Cond : out STD_LOGIC; DATA_Clk_Cond : out STD_LOGIC; SYNC_Clk_Cond : out STD_LOGIC; LD_Clk_Cond : in STD_LOGIC; TIM_Sel : out STD_LOGIC; cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); start_config : in STD_LOGIC; config_started : out STD_LOGIC; config_done : out STD_LOGIC; timemarker_select: in STD_LOGIC ); end component; component FTM_central_control port( clk : IN std_logic; clk_scaler : IN std_logic; new_config : IN std_logic; config_started : OUT std_logic := '0'; config_started_ack : IN std_logic; config_start_eth : OUT std_logic := '0'; config_started_eth : IN std_logic; config_ready_eth : IN std_logic; config_start_ftu : OUT std_logic := '0'; config_started_ftu : IN std_logic; config_ready_ftu : IN std_logic; ping_ftu_start : IN std_logic; ping_ftu_started : OUT std_logic := '0'; ping_ftu_ready : OUT std_logic := '0'; ping_ftu_start_ftu : OUT std_logic := '0'; ping_ftu_started_ftu : IN std_logic; ping_ftu_ready_ftu : IN std_logic; rates_ftu : OUT std_logic := '0'; rates_started_ftu : IN std_logic; rates_ready_ftu : IN std_logic; prescaling_FTU01 : IN std_logic_vector(7 downto 0); dd_send : OUT std_logic := '0'; dd_send_ack : IN std_logic; dd_send_ready : IN std_logic; config_start_cc : out std_logic := '0'; config_started_cc : in std_logic; config_ready_cc : in std_logic ); end component; component FTM_ftu_control port( clk_50MHz : in std_logic; rx_en : out STD_LOGIC; tx_en : out STD_LOGIC; rx_d_0 : in STD_LOGIC; tx_d_0 : out STD_LOGIC; rx_d_1 : in STD_LOGIC; tx_d_1 : out STD_LOGIC; rx_d_2 : in STD_LOGIC; tx_d_2 : out STD_LOGIC; rx_d_3 : in STD_LOGIC; tx_d_3 : out STD_LOGIC; new_config : in std_logic; ping_all : in std_logic; read_rates : in std_logic; read_rates_started : out std_logic := '0'; read_rates_done : out std_logic := '0'; new_config_started : out std_logic := '0'; new_config_done : out std_logic := '0'; ping_all_started : out std_logic := '0'; ping_all_done : out std_logic := '0'; ftu_active_cr0 : in std_logic_vector (15 downto 0); ftu_active_cr1 : in std_logic_vector (15 downto 0); ftu_active_cr2 : in std_logic_vector (15 downto 0); ftu_active_cr3 : in std_logic_vector (15 downto 0); static_RAM_busy : in std_logic; static_RAM_started : in std_logic; static_RAM_ready : in std_logic; data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0'); read_static_RAM : out std_logic := '0'; addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0'); dynamic_RAM_busy : in std_logic; dynamic_RAM_started : in std_logic; dynamic_RAM_ready : in std_logic; data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0'); write_dynamic_RAM : out std_logic := '0'; addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0'); FTUlist_RAM_busy : in std_logic; FTUlist_RAM_started : in std_logic; FTUlist_RAM_ready : in std_logic; data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0'); write_FTUlist_RAM : out std_logic := '0'; addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0') ); end component; component ethernet_modul port( wiz_reset : OUT std_logic := '1'; wiz_addr : OUT std_logic_vector (9 DOWNTO 0); wiz_data : INOUT std_logic_vector (15 DOWNTO 0); wiz_cs : OUT std_logic := '1'; wiz_wr : OUT std_logic := '1'; wiz_rd : OUT std_logic := '1'; wiz_int : IN std_logic ; clk : IN std_logic ; sd_ready : OUT std_logic ; sd_busy : OUT std_logic ; led : OUT std_logic_vector (7 DOWNTO 0); sd_read_ftu : IN std_logic ; sd_started_ftu : OUT std_logic := '0'; cc_R0 : OUT std_logic_vector (31 DOWNTO 0); cc_R1 : OUT std_logic_vector (31 DOWNTO 0); cc_R11 : OUT std_logic_vector (31 DOWNTO 0); cc_R13 : OUT std_logic_vector (31 DOWNTO 0); cc_R14 : OUT std_logic_vector (31 DOWNTO 0); cc_R15 : OUT std_logic_vector (31 DOWNTO 0); cc_R8 : OUT std_logic_vector (31 DOWNTO 0); cc_R9 : OUT std_logic_vector (31 DOWNTO 0); coin_n_c : OUT std_logic_vector (15 DOWNTO 0); coin_n_p : OUT std_logic_vector (15 DOWNTO 0); dead_time : OUT std_logic_vector (15 DOWNTO 0); general_settings : OUT std_logic_vector (15 DOWNTO 0); lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); lp1_delay : OUT std_logic_vector (15 DOWNTO 0); lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); lp2_delay : OUT std_logic_vector (15 DOWNTO 0); lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); trigger_delay : OUT std_logic_vector (15 DOWNTO 0); sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); new_config : OUT std_logic := '0'; config_started : IN std_logic ; config_start_eth : IN std_logic ; config_started_eth : OUT std_logic := '0'; config_ready_eth : OUT std_logic := '0'; config_started_ack : OUT std_logic := '0'; fl_busy : OUT std_logic ; fl_ready : OUT std_logic ; fl_write_ftu : IN std_logic ; fl_started_ftu : OUT std_logic := '0'; fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); ping_ftu_start : OUT std_logic := '0'; ping_ftu_started : IN std_logic ; ping_ftu_ready : IN std_logic ; dd_write_ftu : IN std_logic ; dd_started_ftu : OUT std_logic := '0'; dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); dd_busy : OUT std_logic ; dd_ready : OUT std_logic ; coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); --new stuff dd_block_ready_ftu : IN std_logic; dd_block_start_ack_ftu : OUT std_logic := '0'; dd_block_start_ftu : IN std_logic; dd_send : IN std_logic; dd_send_ack : OUT std_logic := '1'; dd_send_ready : OUT std_logic := '1' ); end component; begin -- IBUFG: Single-ended global clock input buffer -- Spartan-3A -- Xilinx HDL Language Template, version 11.4 IBUFG_inst : IBUFG generic map ( IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, -- "0"-"16" IOSTANDARD => "DEFAULT") port map ( O => clk_buf_sig, -- Clock buffer output I => clk -- Clock buffer input (connect directly to top-level port) ); Inst_FTM_clk_gen : FTM_clk_gen port map( clk => clk_buf_sig, rst => reset_sig, clk_1 => clk_1M_sig, clk_50 => clk_50M_sig, clk_250 => clk_250M_sig, clk_250_ps => clk_250M_ps_sig, ready => clk_ready_sig ); Inst_Clock_cond_interface : Clock_cond_interface port map( clk => clk_50M_sig, CLK_Clk_Cond => CLK_Clk_Cond, LE_Clk_Cond => LE_Clk_Cond, DATA_Clk_Cond => DATA_Clk_Cond, SYNC_Clk_Cond => SYNC_Clk_Cond, LD_Clk_Cond => LD_Clk_Cond, TIM_Sel => TIM_Sel, cc_R0 => cc_R0_sig, cc_R1 => cc_R1_sig, cc_R8 => cc_R8_sig, cc_R9 => cc_R9_sig, cc_R11 => cc_R11_sig, cc_R13 => cc_R13_sig, cc_R14 => cc_R14_sig, cc_R15 => cc_R15_sig, start_config => config_start_cc_sig, config_started => config_started_cc_sig, config_done => config_ready_cc_sig, timemarker_select => general_settings_sig(0) ); Inst_FTM_central_control : FTM_central_control port map( clk => clk_50M_sig, clk_scaler => clk_1M_sig, new_config => new_config_sig, config_started => config_started_sig, config_started_ack => config_started_ack_sig, config_start_eth => config_start_eth_sig, config_started_eth => config_started_eth_sig, config_ready_eth => config_ready_eth_sig, config_start_ftu => config_start_ftu_sig, config_started_ftu => config_started_ftu_sig, config_ready_ftu => config_ready_ftu_sig, ping_ftu_start => ping_ftu_start_sig, ping_ftu_started => ping_ftu_started_sig, ping_ftu_ready => ping_ftu_ready_sig, ping_ftu_start_ftu => ping_ftu_start_ftu_sig, ping_ftu_started_ftu => ping_ftu_started1_sig, ping_ftu_ready_ftu => ping_ftu_ready1_sig, rates_ftu => rates_ftu_start_sig, rates_started_ftu => rates_ftu_started_sig, rates_ready_ftu => rates_ftu_ready_sig, prescaling_FTU01 => "00010011", dd_send => dd_send_sig, dd_send_ack => dd_send_ack_sig, dd_send_ready => dd_send_ready_sig, config_start_cc => config_start_cc_sig, config_started_cc => config_started_cc_sig, config_ready_cc => config_ready_cc_sig ); Inst_FTM_ftu_control : FTM_ftu_control port map( clk_50MHz => clk_50M_sig, rx_en => Bus1_Rx_En, tx_en => Bus1_Tx_En, rx_d_0 => Bus1_RxD_0, tx_d_0 => Bus1_TxD_0, rx_d_1 => Bus1_RxD_1, tx_d_1 => Bus1_TxD_1, rx_d_2 => Bus1_RxD_2, tx_d_2 => Bus1_TxD_2, rx_d_3 => Bus1_RxD_3, tx_d_3 => Bus1_TxD_3, new_config => config_start_ftu_sig, ping_all => ping_ftu_start_ftu_sig, read_rates => rates_ftu_start_sig, read_rates_started => rates_ftu_started_sig, read_rates_done => rates_ftu_ready_sig, new_config_started => config_started_ftu_sig, new_config_done => config_ready_ftu_sig, ping_all_started => ping_ftu_started1_sig, ping_all_done => ping_ftu_ready1_sig, ftu_active_cr0 => ftu_active_cr0_sig, ftu_active_cr1 => ftu_active_cr1_sig, ftu_active_cr2 => ftu_active_cr2_sig, ftu_active_cr3 => ftu_active_cr3_sig, static_RAM_busy => sd_busy_sig, static_RAM_started => sd_started_ftu_sig, static_RAM_ready => sd_ready_sig, data_static_RAM => sd_data_out_ftu_sig, read_static_RAM => sd_read_ftu_sig, addr_static_RAM => sd_addr_ftu_sig, dynamic_RAM_busy => dd_busy_sig, dynamic_RAM_started => dd_started_ftu_sig, dynamic_RAM_ready => dd_ready_sig, data_dynamic_RAM => dd_data_sig, write_dynamic_RAM => dd_write_sig, addr_dynamic_RAM => dd_addr_sig, FTUlist_RAM_busy => fl_busy_sig, FTUlist_RAM_started => fl_started_ftu_sig, FTUlist_RAM_ready => fl_ready_sig, data_FTUlist_RAM => fl_data_sig, write_FTUlist_RAM => fl_write_sig, addr_FTUlist_RAM => fl_addr_sig ); Inst_ethernet_modul : ethernet_modul port map( wiz_reset => W_RES, wiz_addr => W_A, wiz_data => W_D, wiz_cs => W_CS, wiz_wr => W_WR, wiz_rd => W_RD, wiz_int => W_INT, clk => clk_50M_sig, sd_ready => sd_ready_sig, sd_busy => sd_busy_sig, led => led_sig, sd_read_ftu => sd_read_ftu_sig, sd_started_ftu => sd_started_ftu_sig, cc_R0 => cc_R0_sig, cc_R1 => cc_R1_sig, cc_R11 => cc_R11_sig, cc_R13 => cc_R13_sig, cc_R14 => cc_R14_sig, cc_R15 => cc_R15_sig, cc_R8 => cc_R8_sig, cc_R9 => cc_R9_sig, coin_n_c => coin_n_c_sig, coin_n_p => coin_n_p_sig, dead_time => dead_time_sig, general_settings => general_settings_sig, lp1_amplitude => lp1_amplitude_sig, lp1_delay => lp1_delay_sig, lp2_amplitude => lp2_amplitude_sig, lp2_delay => lp2_delay_sig, lp_pt_freq => lp_pt_freq_sig, lp_pt_ratio => lp_pt_ratio_sig, timemarker_delay => timemarker_delay_sig, trigger_delay => trigger_delay_sig, sd_addr_ftu => sd_addr_ftu_sig, sd_data_out_ftu => sd_data_out_ftu_sig, ftu_active_cr0 => ftu_active_cr0_sig, ftu_active_cr1 => ftu_active_cr1_sig, ftu_active_cr2 => ftu_active_cr2_sig, ftu_active_cr3 => ftu_active_cr3_sig, new_config => new_config_sig, config_started => config_started_sig, config_start_eth => config_start_eth_sig, config_started_eth => config_started_eth_sig, config_ready_eth => config_ready_eth_sig, config_started_ack => config_started_ack_sig, fl_busy => fl_busy_sig, fl_ready => fl_ready_sig, fl_write_ftu => fl_write_sig, fl_started_ftu => fl_started_ftu_sig, fl_addr_ftu => fl_addr_sig, fl_data_in_ftu => fl_data_sig, ping_ftu_start => ping_ftu_start_sig, ping_ftu_started => ping_ftu_started_sig, ping_ftu_ready => ping_ftu_ready_sig, dd_write_ftu => dd_write_sig, dd_started_ftu => dd_started_ftu_sig, dd_data_in_ftu => dd_data_sig, dd_addr_ftu => dd_addr_sig, dd_busy => dd_busy_sig, dd_ready => dd_ready_sig, coin_win_c => coin_win_c_sig, coin_win_p => coin_win_p_sig, --new stuff dd_block_ready_ftu => dd_block_ready_sig, dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig, dd_block_start_ftu => dd_block_start_sig, dd_send => dd_send_sig, dd_send_ack => dd_send_ack_sig, dd_send_ready => dd_send_ready_sig ); LED_red <= led_sig(3 downto 0); LED_ye <= led_sig(5 downto 4); LED_gn <= led_sig(7 downto 6); end Behavioral;