source: firmware/FTM/FTM_top.vhd@ 10187

Last change on this file since 10187 was 10067, checked in by weitzel, 15 years ago
Skeleton of FTM_top and FTM_top_tb added
File size: 9.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32
33entity FTM_top is
34 port(
35
36 -- Clock
37 clk : IN STD_LOGIC; -- external clock from oscillator U47
38
39 -- connection to the WIZnet W5300 ethernet controller
40 -- on IO-Bank 1
41 -------------------------------------------------------------------------------
42 -- W5300 data bus
43 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
44
45 -- W5300 address bus
46 W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
47 -- the W5300 is operated in the
48 -- 16-bit mode
49
50 -- W5300 control signals
51 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
52 -- W_CS is also routed to testpoint JP7
53 W_CS : out STD_LOGIC; -- W5300 chip select
54 W_INT : IN STD_LOGIC; -- interrupt
55 W_RD : out STD_LOGIC; -- read
56 W_WR : out STD_LOGIC; -- write
57 W_RES : out STD_LOGIC; -- reset W5300 chip
58
59 -- W5300 buffer ready indicator
60 W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
61
62 -- testpoints (T18) associated with the W5300 on IO-bank 1
63 W_T : inout STD_LOGIC_VECTOR(3 downto 0);
64
65
66 -- SPI Interface
67 -- connection to the EEPROM U36 (AL25L016M) and
68 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
69 -- on IO-Bank 1
70 -------------------------------------------------------------------------------
71 S_CLK : out STD_LOGIC; -- SPI clock
72
73 -- EEPROM
74 -- MOSI : out STD_LOGIC; -- master out slave in
75 -- MISO : in STD_LOGIC; -- master in slave out
76 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
77
78 -- temperature sensors U45, U46, U48 and U49
79 SIO : inout STD_LOGIC; -- serial IO
80 TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
81
82
83 -- Trigger primitives inputs
84 -- on IO-Bank 2
85 -------------------------------------------------------------------------------
86 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
87 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
88 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
89 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
90
91
92 -- NIM inputs
93 ------------------------------------------------------------------------------
94 -- on IO-Bank 3
95 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
96 Veto : in STD_LOGIC; -- trigger veto input
97 NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
98
99 -- on IO-Bank 0
100 -- alternative external clock input for FPGA
101 NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
102
103
104 -- LEDs on IO-Banks 0 and 3
105 -------------------------------------------------------------------------------
106 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
107 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
108 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
109
110
111 -- Clock conditioner LMK03000
112 -- on IO-Bank 3
113 -------------------------------------------------------------------------------
114 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
115 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
116 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
117
118 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
119 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
120
121
122 -- various RS-485 Interfaces
123 -- on IO-Bank 3
124 -------------------------------------------------------------------------------
125 -- Bus 1: FTU slow control
126 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
127 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
128
129 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
130 Bus1_TxD_0 : out STD_LOGIC;
131
132 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
133 Bus1_TxD_1 : out STD_LOGIC;
134
135 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
136 Bus1_TxD_2 : out STD_LOGIC;
137
138 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
139 Bus1_TxD_3 : out STD_LOGIC;
140
141
142 -- Bus 2: Trigger-ID to FAD boards
143 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
144 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
145
146 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
147 Bus2_TxD_0 : out STD_LOGIC;
148
149 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
150 Bus2_TxD_1 : out STD_LOGIC;
151
152 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
153 Bus2_TxD_2 : out STD_LOGIC;
154
155 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
156 Bus2_TxD_3 : out STD_LOGIC;
157
158
159 -- auxiliary access
160 -- Aux_Rx_D : in STD_LOGIC;
161 -- Aux_Tx_D : out STD_LOGIC;
162 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
163 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
164
165
166 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
167 -- TrID_Rx_D : in STD_LOGIC;
168 -- TrID_Tx_D : out STD_LOGIC;
169
170
171 -- Crate-Resets
172 -- on IO-Bank 3
173 -------------------------------------------------------------------------------
174 Crate_Res0 : out STD_LOGIC;
175 Crate_Res1 : out STD_LOGIC;
176 Crate_Res2 : out STD_LOGIC;
177 Crate_Res3 : out STD_LOGIC;
178
179
180 -- Busy signals from the FAD boards
181 -- on IO-Bank 3
182 -------------------------------------------------------------------------------
183 Busy0 : in STD_LOGIC;
184 Busy1 : in STD_LOGIC;
185 Busy2 : in STD_LOGIC;
186 Busy3 : in STD_LOGIC;
187
188
189 -- NIM outputs
190 -- on IO-Bank 0
191 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
192 -------------------------------------------------------------------------------
193 -- calibration
194 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
195 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
196 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
197 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
198
199 -- auxiliarry / spare NIM outputs
200 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
201 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
202 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
203 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
204
205
206 -- fast control signal outputs
207 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
208 -------------------------------------------------------------------------------
209 RES_p : out STD_LOGIC; -- RES+ Reset
210 RES_n : out STD_LOGIC; -- RES- IO-Bank 0
211
212 TRG_p : out STD_LOGIC; -- TRG+ Trigger
213 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
214
215 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
216 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
217 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
218
219 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
220
221
222 -- LVDS calibration outputs
223 -- on IO-Bank 0
224 -------------------------------------------------------------------------------
225 -- to connector J13
226 -- for light pulsar in the mirror dish
227 Cal_0_p : out STD_LOGIC;
228 Cal_0_n : out STD_LOGIC;
229 Cal_1_p : out STD_LOGIC;
230 Cal_1_n : out STD_LOGIC;
231 Cal_2_p : out STD_LOGIC;
232 Cal_2_n : out STD_LOGIC;
233 Cal_3_p : out STD_LOGIC;
234 Cal_3_n : out STD_LOGIC;
235
236 -- to connector J12
237 -- for light pulsar inside shutter
238 Cal_4_p : out STD_LOGIC;
239 Cal_4_n : out STD_LOGIC;
240 Cal_5_p : out STD_LOGIC;
241 Cal_5_n : out STD_LOGIC;
242 Cal_6_p : out STD_LOGIC;
243 Cal_6_n : out STD_LOGIC;
244 Cal_7_p : out STD_LOGIC;
245 Cal_7_n : out STD_LOGIC
246
247
248 -- Testpoints
249 -------------------------------------------------------------------------------
250 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
251 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
252
253 -- Board ID - inputs
254 -- local board-ID "solder programmable"
255 -- all on 'input only' pins
256 -------------------------------------------------------------------------------
257 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
258
259 );
260end FTM_top;
261
262architecture Behavioral of FTM_top is
263
264begin
265
266end Behavioral;
267
268
269
270
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