source: firmware/FTM/FTM_top.vhd@ 10761

Last change on this file since 10761 was 10760, checked in by weitzel, 14 years ago
FTM: reset of timing counters implemented
File size: 51.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 Bus2_TxD_0 : out STD_LOGIC;
153
154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 Bus2_TxD_1 : out STD_LOGIC;
156
157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 Bus2_TxD_2 : out STD_LOGIC;
159
160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 Crate_Res0 : out STD_LOGIC;
180 Crate_Res1 : out STD_LOGIC;
181 Crate_Res2 : out STD_LOGIC;
182 Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 -- RES_p : out STD_LOGIC; -- RES+ Reset
215 -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 -- Cal_0_p : out STD_LOGIC;
233 -- Cal_0_n : out STD_LOGIC;
234 -- Cal_1_p : out STD_LOGIC;
235 -- Cal_1_n : out STD_LOGIC;
236 -- Cal_2_p : out STD_LOGIC;
237 -- Cal_2_n : out STD_LOGIC;
238 -- Cal_3_p : out STD_LOGIC;
239 -- Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 -- Cal_4_p : out STD_LOGIC;
244 -- Cal_4_n : out STD_LOGIC;
245 -- Cal_5_p : out STD_LOGIC;
246 -- Cal_5_n : out STD_LOGIC;
247 -- Cal_6_p : out STD_LOGIC;
248 -- Cal_6_n : out STD_LOGIC;
249 -- Cal_7_p : out STD_LOGIC;
250 -- Cal_7_n : out STD_LOGIC
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 TP : inout STD_LOGIC_VECTOR(32 downto 0)
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_ftu_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_ftu_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic := '0';
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352
353 signal config_trigger_sig : std_logic;
354 signal config_trigger_done_sig : std_logic;
355
356 signal clk_buf_sig : std_logic;
357 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
358 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
359 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
360 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
361 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
362
363 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager
364 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager
365 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast
366
367 signal trigger_active_sig : std_logic; -- initialized in trigger manager
368
369 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
370
371 signal trigger_signal_sig : std_logic := '0';
372 signal TIM_signal_sig : std_logic := '0';
373
374 --signals for FPGA DNA identifier
375 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen
376 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control
377 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen
378
379 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
380
381 signal get_ot_counter_sig : std_logic;
382 signal get_ot_counter_started_sig : std_logic;
383 signal get_ot_counter_ready_sig : std_logic;
384 signal on_time_counter_sig : std_logic_vector(47 downto 0);
385
386 signal get_ts_counter_sig : std_logic;
387 signal get_ts_counter_started_sig : std_logic;
388 signal get_ts_counter_ready_sig : std_logic;
389 signal timestamp_counter_sig : std_logic_vector(47 downto 0);
390
391 signal crate_reset_sig : std_logic;
392 signal crate_reset_ack_sig : std_logic;
393 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0);
394 signal start_run_sig : std_logic;
395 signal start_run_ack_sig : std_logic;
396 signal stop_run_sig : std_logic;
397 signal stop_run_ack_sig : std_logic;
398 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0);
399 signal cc_state_test_sig : std_logic_vector ( 7 downto 0);
400 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0);
401 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0);
402
403 signal trigger_start_sig : std_logic;
404 signal trigger_stop_sig : std_logic;
405
406 signal enable_ID_sending_sig : std_logic;
407 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control
408
409-- component FTM_clk_gen
410-- port(
411-- clk : IN STD_LOGIC;
412-- rst : IN STD_LOGIC;
413-- clk_1 : OUT STD_LOGIC;
414-- clk_50 : OUT STD_LOGIC;
415-- clk_250 : OUT STD_LOGIC;
416-- clk_250_ps : OUT STD_LOGIC;
417-- ready : OUT STD_LOGIC
418-- );
419-- end component;
420
421 component FTM_clk_gen_2
422 port(
423 clk : IN STD_LOGIC;
424 rst : IN STD_LOGIC;
425 clk_1 : OUT STD_LOGIC;
426 clk_50 : OUT STD_LOGIC;
427 clk_250 : OUT STD_LOGIC;
428 clk_250_ps : OUT STD_LOGIC;
429 ready : OUT STD_LOGIC
430 );
431 end component;
432
433 component FTM_dna_gen
434 port(
435 clk : IN STD_LOGIC;
436 start : IN STD_LOGIC;
437 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
438 ready : OUT STD_LOGIC
439 );
440 end component;
441
442 component trigger_manager
443 port(
444 --clocks
445 clk_50MHz : in std_logic;
446 clk_250MHz : in std_logic;
447 clk_250MHz_180 : in std_logic;
448 --trigger primitives from FTUs
449 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
450 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
451 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
452 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
453 --external signals
454 ext_trig_1 : in std_logic;
455 ext_trig_2 : in std_logic;
456 ext_veto : in std_logic;
457 FAD_busy_0 : in std_logic; --crate 0
458 FAD_busy_1 : in std_logic; --crate 1
459 FAD_busy_2 : in std_logic; --crate 2
460 FAD_busy_3 : in std_logic; --crate 3
461 --control signals from e.g. main control
462 start_run : in std_logic; --enable trigger output
463 stop_run : in std_logic; --disable trigger output
464 new_config : in std_logic;
465 --settings register (see FTM Firmware Specifications)
466 general_settings : in std_logic_vector(15 downto 0);
467 LP_and_PED_freq : in std_logic_vector(15 downto 0);
468 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
469 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
470 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
471 trigger_delay : in std_logic_vector(15 downto 0);
472 TIM_delay : in std_logic_vector(15 downto 0);
473 dead_time : in std_logic_vector(15 downto 0);
474 coinc_window_phys : in std_logic_vector(15 downto 0);
475 coinc_window_calib : in std_logic_vector(15 downto 0);
476 active_FTU_list_0 : in std_logic_vector(15 downto 0);
477 active_FTU_list_1 : in std_logic_vector(15 downto 0);
478 active_FTU_list_2 : in std_logic_vector(15 downto 0);
479 active_FTU_list_3 : in std_logic_vector(15 downto 0);
480 --control signals or information for other entities
481 trigger_ID_read : in std_logic;
482 trig_cnt_copy_read : in std_logic;
483 trigger_ID_ready : out std_logic;
484 trigger_ID : out std_logic_vector(55 downto 0);
485 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
486 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
487 trigger_active : out std_logic; --phys triggers are enabled/active
488 config_done : out std_logic;
489 LP1_pulse : out std_logic; --send start signal to light pulser 1
490 LP2_pulse : out std_logic; --send start signal to light pulser 2
491 --trigger and time marker output signals to FADs
492 trigger_signal : out std_logic;
493 TIM_signal : out std_logic
494 );
495 end component;
496
497 component Clock_cond_interface is
498 port(
499 clk : IN STD_LOGIC;
500 CLK_Clk_Cond : out STD_LOGIC;
501 LE_Clk_Cond : out STD_LOGIC;
502 DATA_Clk_Cond : out STD_LOGIC;
503 SYNC_Clk_Cond : out STD_LOGIC;
504 LD_Clk_Cond : in STD_LOGIC;
505 TIM_Sel : out STD_LOGIC;
506 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
507 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
508 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
509 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
510 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
511 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
512 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
513 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
514 start_config : in STD_LOGIC;
515 config_started : out STD_LOGIC;
516 config_done : out STD_LOGIC;
517 timemarker_select: in STD_LOGIC
518 );
519 end component;
520
521 component FTM_central_control
522 port(
523 clk : IN std_logic;
524 clk_ready : in std_logic;
525 clk_scaler : IN std_logic;
526 new_config : IN std_logic;
527 config_started : OUT std_logic := '0';
528 config_started_ack : IN std_logic;
529 config_start_eth : OUT std_logic := '0';
530 config_started_eth : IN std_logic;
531 config_ready_eth : IN std_logic;
532 config_start_ftu : OUT std_logic := '0';
533 config_started_ftu : IN std_logic;
534 config_ready_ftu : IN std_logic;
535 ping_ftu_start : IN std_logic;
536 ping_ftu_started : OUT std_logic := '0';
537 ping_ftu_ready : OUT std_logic := '0';
538 ping_ftu_start_ftu : OUT std_logic := '0';
539 ping_ftu_started_ftu : IN std_logic;
540 ping_ftu_ready_ftu : IN std_logic;
541 rates_ftu : OUT std_logic := '0';
542 rates_started_ftu : IN std_logic;
543 rates_ready_ftu : IN std_logic;
544 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
545 dd_send : OUT std_logic := '0';
546 dd_send_ack : IN std_logic;
547 dd_send_ready : IN std_logic;
548 dd_block_ready_ftu : out std_logic := '0';
549 dd_block_start_ack_ftu : in std_logic;
550 dd_block_start_ftu : out std_logic := '0';
551 config_start_cc : out std_logic := '0';
552 config_started_cc : in std_logic;
553 config_ready_cc : in std_logic;
554 config_trigger : out std_logic;
555 config_trigger_done : in std_logic;
556 dna_start : out std_logic;
557 dna_ready : in std_logic;
558 crate_reset : IN std_logic;
559 crate_reset_ack : OUT std_logic;
560 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
561 start_run : IN std_logic;
562 start_run_ack : OUT std_logic;
563 stop_run : IN std_logic;
564 stop_run_ack : OUT std_logic;
565 current_cc_state : OUT std_logic_vector (15 DOWNTO 0);
566 cc_state_test : OUT std_logic_vector ( 7 downto 0);
567 start_run_param : IN std_logic_vector (15 DOWNTO 0);
568 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
569 trigger_start : out std_logic;
570 trigger_stop : out std_logic;
571 enable_ID_sending : out std_logic;
572 reset_timer : out std_logic
573 );
574 end component;
575
576 component FTM_ftu_control
577 port(
578 clk_50MHz : in std_logic;
579 rx_en : out STD_LOGIC;
580 tx_en : out STD_LOGIC;
581 rx_d_0 : in STD_LOGIC;
582 tx_d_0 : out STD_LOGIC;
583 rx_d_1 : in STD_LOGIC;
584 tx_d_1 : out STD_LOGIC;
585 rx_d_2 : in STD_LOGIC;
586 tx_d_2 : out STD_LOGIC;
587 rx_d_3 : in STD_LOGIC;
588 tx_d_3 : out STD_LOGIC;
589 new_config : in std_logic;
590 ping_all : in std_logic;
591 read_rates : in std_logic;
592 read_rates_started : out std_logic := '0';
593 read_rates_done : out std_logic := '0';
594 new_config_started : out std_logic := '0';
595 new_config_done : out std_logic := '0';
596 ping_all_started : out std_logic := '0';
597 ping_all_done : out std_logic := '0';
598 ftu_active_cr0 : in std_logic_vector (15 downto 0);
599 ftu_active_cr1 : in std_logic_vector (15 downto 0);
600 ftu_active_cr2 : in std_logic_vector (15 downto 0);
601 ftu_active_cr3 : in std_logic_vector (15 downto 0);
602 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
603 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
604 ftu_error_send : out std_logic := '0';
605 ftu_error_send_ack : in std_logic;
606 ftu_error_send_ready : in std_logic;
607 static_RAM_busy : in std_logic;
608 static_RAM_started : in std_logic;
609 static_RAM_ready : in std_logic;
610 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
611 read_static_RAM : out std_logic := '0';
612 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
613 dynamic_RAM_busy : in std_logic;
614 dynamic_RAM_started : in std_logic;
615 dynamic_RAM_ready : in std_logic;
616 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
617 write_dynamic_RAM : out std_logic := '0';
618 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
619 FTUlist_RAM_busy : in std_logic;
620 FTUlist_RAM_started : in std_logic;
621 FTUlist_RAM_ready : in std_logic;
622 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
623 write_FTUlist_RAM : out std_logic := '0';
624 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
625 );
626 end component;
627
628 component FTM_fad_broadcast
629 port(
630 clk_50MHz : in std_logic;
631 rx_en : out STD_LOGIC;
632 tx_en : out STD_LOGIC;
633 rx_d_0 : in STD_LOGIC;
634 tx_d_0 : out STD_LOGIC;
635 rx_d_1 : in STD_LOGIC;
636 tx_d_1 : out STD_LOGIC;
637 rx_d_2 : in STD_LOGIC;
638 tx_d_2 : out STD_LOGIC;
639 rx_d_3 : in STD_LOGIC;
640 tx_d_3 : out STD_LOGIC;
641 enable_ID_sending : in std_logic;
642 TIM_source : in std_logic;
643 LP_settings : in std_logic_vector(3 downto 0);
644 trigger_ID_ready : in std_logic;
645 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
646 trigger_ID_read : out std_logic
647 );
648 end component;
649
650 component ethernet_modul
651 port(
652 wiz_reset : OUT std_logic := '1';
653 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
654 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
655 wiz_cs : OUT std_logic := '1';
656 wiz_wr : OUT std_logic := '1';
657 wiz_rd : OUT std_logic := '1';
658 wiz_int : IN std_logic ;
659 clk : IN std_logic ;
660 sd_ready : OUT std_logic ;
661 sd_busy : OUT std_logic ;
662 led : OUT std_logic_vector (7 DOWNTO 0);
663 sd_read_ftu : IN std_logic ;
664 sd_started_ftu : OUT std_logic := '0';
665 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
666 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
667 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
668 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
669 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
670 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
671 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
672 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
673 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
674 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
675 dead_time : OUT std_logic_vector (15 DOWNTO 0);
676 general_settings : OUT std_logic_vector (15 DOWNTO 0);
677 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
678 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
679 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
680 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
681 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
682 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
683 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
684 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
685 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
686 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
687 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
688 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
689 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
690 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
691 new_config : OUT std_logic := '0';
692 config_started : IN std_logic ;
693 config_start_eth : IN std_logic ;
694 config_started_eth : OUT std_logic := '0';
695 config_ready_eth : OUT std_logic := '0';
696 config_started_ack : OUT std_logic := '0';
697 fl_busy : OUT std_logic ;
698 fl_ready : OUT std_logic ;
699 fl_write_ftu : IN std_logic ;
700 fl_started_ftu : OUT std_logic := '0';
701 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
702 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
703 ping_ftu_start : OUT std_logic := '0';
704 ping_ftu_started : IN std_logic ;
705 ping_ftu_ready : IN std_logic ;
706 dd_write_ftu : IN std_logic ;
707 dd_started_ftu : OUT std_logic := '0';
708 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
709 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
710 dd_busy : OUT std_logic ;
711 dd_ready : OUT std_logic ;
712 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
713 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
714 --new stuff
715 dd_block_ready_ftu : IN std_logic;
716 dd_block_start_ack_ftu : OUT std_logic := '0';
717 dd_block_start_ftu : IN std_logic;
718 dd_send : IN std_logic;
719 dd_send_ack : OUT std_logic := '1';
720 dd_send_ready : OUT std_logic := '1';
721 --very new stuff
722 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
723 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
724 ftu_error_send : IN std_logic;
725 ftu_error_send_ack : OUT std_logic := '1';
726 ftu_error_send_ready : OUT std_logic := '1';
727 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
728 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
729 trigger_counter_read : OUT std_logic := '0';
730 trigger_counter_valid : IN std_logic;
731 --newest stuff
732 board_id : IN std_logic_vector (63 DOWNTO 0);
733 get_ts_counter : OUT std_logic := '0';
734 get_ts_counter_ready : IN std_logic;
735 get_ts_counter_started : IN std_logic;
736 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
737 get_ot_counter : OUT std_logic := '0';
738 get_ot_counter_ready : IN std_logic;
739 get_ot_counter_started : IN std_logic;
740 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
741 temp_sensor_array : IN sensor_array_type;
742 temp_sensor_ready : IN std_logic;
743 crate_reset : OUT std_logic := '0';
744 crate_reset_ack : IN std_logic;
745 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
746 start_run : OUT std_logic := '0';
747 start_run_ack : IN std_logic;
748 stop_run : OUT std_logic := '0';
749 stop_run_ack : IN std_logic;
750 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
751 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
752 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0')
753 );
754 end component;
755
756-- component counter_dummy IS
757-- PORT(
758-- clk : IN std_logic;
759-- get_counter : IN std_logic;
760-- get_counter_started : OUT std_logic := '0';
761-- get_counter_ready : OUT std_logic := '0';
762-- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
763-- );
764-- end component;
765
766 component Timing_counter is
767 port(
768 clk : in STD_LOGIC; -- 50 MHz system clock
769 enable : in STD_LOGIC; -- enable counter
770 reset : in Std_LOGIC; -- reset counter
771 read_counter : in STD_LOGIC; -- read counter
772 reading_started : out STD_LOGIC;
773 reading_valid : out STD_LOGIC; -- counter reading at output ready
774 counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0)
775 );
776 end component;
777
778
779begin
780
781-- -- IBUFG: Single-ended global clock input buffer
782-- -- Spartan-3A
783-- -- Xilinx HDL Language Template, version 11.4
784
785-- IBUFG_inst : IBUFG
786-- generic map (
787-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
788-- -- "0"-"16"
789-- IOSTANDARD => "DEFAULT")
790-- port map (
791-- O => clk_buf_sig, -- Clock buffer output
792-- I => clk -- Clock buffer input (connect directly to top-level port)
793-- );
794
795-- Inst_FTM_clk_gen : FTM_clk_gen
796-- port map(
797-- clk => clk_buf_sig,
798-- rst => reset_sig,
799-- clk_1 => clk_1M_sig,
800-- clk_50 => clk_50M_sig,
801-- clk_250 => clk_250M_sig,
802-- clk_250_ps => clk_250M_ps_sig,
803-- ready => clk_ready_sig
804-- );
805
806 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
807 port map(
808 clk => clk,
809 rst => reset_sig,
810 clk_1 => clk_1M_sig,
811 clk_50 => clk_50M_sig,
812 clk_250 => clk_250M_sig,
813 clk_250_ps => clk_250M_ps_sig,
814 ready => clk_ready_sig
815 );
816
817 Inst_FTM_dna_gen : FTM_dna_gen
818 port map(
819 clk => clk_50M_sig,
820 start => dna_start_sig,
821 dna => dna_sig,
822 ready => dna_ready_sig
823 );
824
825 --differential output buffer for trigger signal
826 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
827 port map(
828 O => TRG_p,
829 OB => TRG_n,
830 I => trigger_signal_sig
831 );
832
833 --differential output buffer for trigger signal
834 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
835 port map(
836 O => TIM_Run_p,
837 OB => TIM_Run_n,
838 I => TIM_signal_sig
839 );
840
841 Inst_trigger_manager : trigger_manager
842 port map(
843 --clocks
844 clk_50MHz => clk_50M_sig,
845 clk_250MHz => clk_250M_sig,
846 clk_250MHz_180 => clk_250M_ps_sig,
847 --trigger primitives from FTUs
848 trig_prim_0 => Trig_Prim_A, --crate 0
849 trig_prim_1 => Trig_Prim_B, --crate 1
850 trig_prim_2 => Trig_Prim_C, --crate 2
851 trig_prim_3 => Trig_Prim_D, --crate 3
852 --external signals
853 ext_trig_1 => ext_Trig(1),
854 ext_trig_2 => ext_Trig(2),
855 ext_veto => Veto,
856 FAD_busy_0 => Busy0, --crate 0
857 FAD_busy_1 => Busy1, --crate 1
858 FAD_busy_2 => Busy2, --crate 2
859 FAD_busy_3 => Busy3, --crate 3
860 --control signals from e.g. main control
861 start_run => trigger_start_sig, --enable trigger output
862 stop_run => trigger_stop_sig, --disable trigger output
863 new_config => config_trigger_sig,
864 --settings register (see FTM Firmware Specifications)
865 general_settings => general_settings_sig,
866 LP_and_PED_freq => lp_pt_freq_sig,
867 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
868 maj_coinc_n_phys => coin_n_p_sig,
869 maj_coinc_n_calib => coin_n_c_sig,
870 trigger_delay => trigger_delay_sig,
871 TIM_delay => timemarker_delay_sig,
872 dead_time => dead_time_sig,
873 coinc_window_phys => coin_win_p_sig,
874 coinc_window_calib => coin_win_c_sig,
875 active_FTU_list_0 => ftu_active_cr0_sig,
876 active_FTU_list_1 => ftu_active_cr1_sig,
877 active_FTU_list_2 => ftu_active_cr2_sig,
878 active_FTU_list_3 => ftu_active_cr3_sig,
879 --control signals or information for other entities
880 trigger_ID_read => trigger_ID_read_sig,
881 trig_cnt_copy_read => trigger_counter_read_sig,
882 trigger_ID_ready => trigger_ID_ready_sig,
883 trigger_ID => trigger_ID_sig,
884 trig_cnt_copy => trigger_counter_sig, --counter reading
885 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
886 trigger_active => trigger_active_sig, --phys triggers are enabled/active
887 config_done => config_trigger_done_sig,
888 LP1_pulse => open, --send start signal to light pulser 1
889 LP2_pulse => open, --send start signal to light pulser 2
890 --trigger and time marker output signals to FADs
891 trigger_signal => trigger_signal_sig,
892 TIM_signal => TIM_signal_sig
893 );
894
895 Inst_Clock_cond_interface : Clock_cond_interface
896 port map(
897 clk => clk_50M_sig,
898 CLK_Clk_Cond => CLK_Clk_Cond,
899 LE_Clk_Cond => LE_Clk_Cond,
900 DATA_Clk_Cond => DATA_Clk_Cond,
901 SYNC_Clk_Cond => SYNC_Clk_Cond,
902 LD_Clk_Cond => LD_Clk_Cond,
903 TIM_Sel => TIM_Sel,
904 cc_R0 => cc_R0_sig,
905 cc_R1 => cc_R1_sig,
906 cc_R8 => cc_R8_sig,
907 cc_R9 => cc_R9_sig,
908 cc_R11 => cc_R11_sig,
909 cc_R13 => cc_R13_sig,
910 cc_R14 => cc_R14_sig,
911 cc_R15 => cc_R15_sig,
912 start_config => config_start_cc_sig,
913 config_started => config_started_cc_sig,
914 config_done => config_ready_cc_sig,
915 timemarker_select => general_settings_sig(0)
916 );
917
918 Inst_FTM_central_control : FTM_central_control
919 port map(
920 clk => clk_50M_sig,
921 clk_ready => clk_ready_sig,
922 clk_scaler => clk_1M_sig,
923 new_config => new_config_sig,
924 config_started => config_started_sig,
925 config_started_ack => config_started_ack_sig,
926 config_start_eth => config_start_eth_sig,
927 config_started_eth => config_started_eth_sig,
928 config_ready_eth => config_ready_eth_sig,
929 config_start_ftu => config_start_ftu_sig,
930 config_started_ftu => config_started_ftu_sig,
931 config_ready_ftu => config_ready_ftu_sig,
932 ping_ftu_start => ping_ftu_start_sig,
933 ping_ftu_started => ping_ftu_started_sig,
934 ping_ftu_ready => ping_ftu_ready_sig,
935 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
936 ping_ftu_started_ftu => ping_ftu_started1_sig,
937 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
938 rates_ftu => rates_ftu_start_sig,
939 rates_started_ftu => rates_ftu_started_sig,
940 rates_ready_ftu => rates_ftu_ready_sig,
941 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
942 dd_send => dd_send_sig,
943 dd_send_ack => dd_send_ack_sig,
944 dd_send_ready => dd_send_ready_sig,
945 dd_block_ready_ftu => dd_block_ready_ftu_sig,
946 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
947 dd_block_start_ftu => dd_block_start_ftu_sig,
948 config_start_cc => config_start_cc_sig,
949 config_started_cc => config_started_cc_sig,
950 config_ready_cc => config_ready_cc_sig,
951 config_trigger => config_trigger_sig,
952 config_trigger_done => config_trigger_done_sig,
953 dna_start => dna_start_sig,
954 dna_ready => dna_ready_sig,
955 crate_reset => crate_reset_sig,
956 crate_reset_ack => crate_reset_ack_sig,
957 crate_reset_param => crate_reset_param_sig,
958 start_run => start_run_sig,
959 start_run_ack => start_run_ack_sig,
960 stop_run => stop_run_sig,
961 stop_run_ack => stop_run_ack_sig,
962 current_cc_state => current_cc_state_sig,
963 cc_state_test => cc_state_test_sig,
964 start_run_param => start_run_param_sig,
965 start_run_num_events => start_run_num_events_sig,
966 trigger_start => trigger_start_sig,
967 trigger_stop => trigger_stop_sig,
968 enable_ID_sending => enable_ID_sending_sig,
969 reset_timer => reset_timer_sig
970 );
971
972 Inst_FTM_ftu_control : FTM_ftu_control
973 port map(
974 clk_50MHz => clk_50M_sig,
975 rx_en => Bus1_Rx_En,
976 tx_en => Bus1_Tx_En,
977 rx_d_0 => Bus1_RxD_0,
978 tx_d_0 => Bus1_TxD_0,
979 rx_d_1 => Bus1_RxD_1,
980 tx_d_1 => Bus1_TxD_1,
981 rx_d_2 => Bus1_RxD_2,
982 tx_d_2 => Bus1_TxD_2,
983 rx_d_3 => Bus1_RxD_3,
984 tx_d_3 => Bus1_TxD_3,
985 new_config => config_start_ftu_sig,
986 ping_all => ping_ftu_start_ftu_sig,
987 read_rates => rates_ftu_start_sig,
988 read_rates_started => rates_ftu_started_sig,
989 read_rates_done => rates_ftu_ready_sig,
990 new_config_started => config_started_ftu_sig,
991 new_config_done => config_ready_ftu_sig,
992 ping_all_started => ping_ftu_started1_sig,
993 ping_all_done => ping_ftu_ready1_sig,
994 ftu_active_cr0 => ftu_active_cr0_sig,
995 ftu_active_cr1 => ftu_active_cr1_sig,
996 ftu_active_cr2 => ftu_active_cr2_sig,
997 ftu_active_cr3 => ftu_active_cr3_sig,
998 ftu_error_calls => ftu_error_calls_sig,
999 ftu_error_data => ftu_error_data_sig,
1000 ftu_error_send => ftu_error_send_sig,
1001 ftu_error_send_ack => ftu_error_send_ack_sig,
1002 ftu_error_send_ready=> ftu_error_send_ready_sig,
1003 static_RAM_busy => sd_busy_sig,
1004 static_RAM_started => sd_started_ftu_sig,
1005 static_RAM_ready => sd_ready_sig,
1006 data_static_RAM => sd_data_out_ftu_sig,
1007 read_static_RAM => sd_read_ftu_sig,
1008 addr_static_RAM => sd_addr_ftu_sig,
1009 dynamic_RAM_busy => dd_busy_sig,
1010 dynamic_RAM_started => dd_started_ftu_sig,
1011 dynamic_RAM_ready => dd_ready_sig,
1012 data_dynamic_RAM => dd_data_sig,
1013 write_dynamic_RAM => dd_write_sig,
1014 addr_dynamic_RAM => dd_addr_sig,
1015 FTUlist_RAM_busy => fl_busy_sig,
1016 FTUlist_RAM_started => fl_started_ftu_sig,
1017 FTUlist_RAM_ready => fl_ready_sig,
1018 data_FTUlist_RAM => fl_data_sig,
1019 write_FTUlist_RAM => fl_write_sig,
1020 addr_FTUlist_RAM => fl_addr_sig
1021 );
1022
1023 Inst_FTM_fad_broadcast : FTM_fad_broadcast
1024 port map(
1025 clk_50MHz => clk_50M_sig,
1026 rx_en => Bus2_Rx_En,
1027 tx_en => Bus2_Tx_En,
1028 rx_d_0 => Bus2_RxD_0,
1029 tx_d_0 => Bus2_TxD_0,
1030 rx_d_1 => Bus2_RxD_1,
1031 tx_d_1 => Bus2_TxD_1,
1032 rx_d_2 => Bus2_RxD_2,
1033 tx_d_2 => Bus2_TxD_2,
1034 rx_d_3 => Bus2_RxD_3,
1035 tx_d_3 => Bus2_TxD_3,
1036 --enable_ID_sending => trigger_start_sig,
1037 enable_ID_sending => enable_ID_sending_sig,
1038 --enable_ID_sending => '1',
1039 TIM_source => general_settings_sig(0),
1040 LP_settings => "0000",
1041 trigger_ID_ready => trigger_ID_ready_sig,
1042 trigger_ID => trigger_ID_sig,
1043 trigger_ID_read => trigger_ID_read_sig
1044 );
1045
1046 Inst_ethernet_modul : ethernet_modul
1047 port map(
1048 wiz_reset => W_RES,
1049 wiz_addr => W_A,
1050 wiz_data => W_D,
1051 wiz_cs => W_CS,
1052 wiz_wr => W_WR,
1053 wiz_rd => W_RD,
1054 wiz_int => W_INT,
1055 clk => clk_50M_sig,
1056 sd_ready => sd_ready_sig,
1057 sd_busy => sd_busy_sig,
1058 led => led_sig,
1059 sd_read_ftu => sd_read_ftu_sig,
1060 sd_started_ftu => sd_started_ftu_sig,
1061 cc_R0 => cc_R0_sig,
1062 cc_R1 => cc_R1_sig,
1063 cc_R11 => cc_R11_sig,
1064 cc_R13 => cc_R13_sig,
1065 cc_R14 => cc_R14_sig,
1066 cc_R15 => cc_R15_sig,
1067 cc_R8 => cc_R8_sig,
1068 cc_R9 => cc_R9_sig,
1069 coin_n_c => coin_n_c_sig,
1070 coin_n_p => coin_n_p_sig,
1071 dead_time => dead_time_sig,
1072 general_settings => general_settings_sig,
1073 lp1_amplitude => lp1_amplitude_sig,
1074 lp1_delay => lp1_delay_sig,
1075 lp2_amplitude => lp2_amplitude_sig,
1076 lp2_delay => lp2_delay_sig,
1077 lp_pt_freq => lp_pt_freq_sig,
1078 lp_pt_ratio => lp_pt_ratio_sig,
1079 timemarker_delay => timemarker_delay_sig,
1080 trigger_delay => trigger_delay_sig,
1081 sd_addr_ftu => sd_addr_ftu_sig,
1082 sd_data_out_ftu => sd_data_out_ftu_sig,
1083 ftu_active_cr0 => ftu_active_cr0_sig,
1084 ftu_active_cr1 => ftu_active_cr1_sig,
1085 ftu_active_cr2 => ftu_active_cr2_sig,
1086 ftu_active_cr3 => ftu_active_cr3_sig,
1087 new_config => new_config_sig,
1088 config_started => config_started_sig,
1089 config_start_eth => config_start_eth_sig,
1090 config_started_eth => config_started_eth_sig,
1091 config_ready_eth => config_ready_eth_sig,
1092 config_started_ack => config_started_ack_sig,
1093 fl_busy => fl_busy_sig,
1094 fl_ready => fl_ready_sig,
1095 fl_write_ftu => fl_write_sig,
1096 fl_started_ftu => fl_started_ftu_sig,
1097 fl_addr_ftu => fl_addr_sig,
1098 fl_data_in_ftu => fl_data_sig,
1099 ping_ftu_start => ping_ftu_start_sig,
1100 ping_ftu_started => ping_ftu_started_sig,
1101 ping_ftu_ready => ping_ftu_ready_sig,
1102 dd_write_ftu => dd_write_sig,
1103 dd_started_ftu => dd_started_ftu_sig,
1104 dd_data_in_ftu => dd_data_sig,
1105 dd_addr_ftu => dd_addr_sig,
1106 dd_busy => dd_busy_sig,
1107 dd_ready => dd_ready_sig,
1108 coin_win_c => coin_win_c_sig,
1109 coin_win_p => coin_win_p_sig,
1110 --new stuff
1111 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1112 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1113 dd_block_start_ftu => dd_block_start_ftu_sig,
1114 dd_send => dd_send_sig,
1115 dd_send_ack => dd_send_ack_sig,
1116 dd_send_ready => dd_send_ready_sig,
1117 --very new stuff
1118 ftu_error_calls => ftu_error_calls_sig,
1119 ftu_error_data => ftu_error_data_sig,
1120 ftu_error_send => ftu_error_send_sig,
1121 ftu_error_send_ack => ftu_error_send_ack_sig,
1122 ftu_error_send_ready => ftu_error_send_ready_sig,
1123 prescaling_FTU01 => prescaling_FTU01_sig,
1124 trigger_counter => trigger_counter_sig,
1125 trigger_counter_read => trigger_counter_read_sig,
1126 trigger_counter_valid => trigger_counter_valid_sig,
1127 --newest stuff
1128 board_id => dna_sig,
1129 get_ts_counter => get_ts_counter_sig,
1130 get_ts_counter_ready => get_ts_counter_ready_sig,
1131 get_ts_counter_started => get_ts_counter_started_sig,
1132 timestamp_counter => timestamp_counter_sig,
1133 get_ot_counter => get_ot_counter_sig,
1134 get_ot_counter_ready => get_ot_counter_ready_sig,
1135 get_ot_counter_started => get_ot_counter_started_sig,
1136 on_time_counter => on_time_counter_sig,
1137 temp_sensor_array => (35, 45, 55, 65),
1138 temp_sensor_ready => '1',
1139 crate_reset => crate_reset_sig,
1140 crate_reset_ack => crate_reset_ack_sig,
1141 crate_reset_param => crate_reset_param_sig,
1142 start_run => start_run_sig,
1143 start_run_ack => start_run_ack_sig,
1144 stop_run => stop_run_sig,
1145 stop_run_ack => stop_run_ack_sig,
1146 current_cc_state => current_cc_state_sig,
1147 start_run_param => start_run_param_sig,
1148 start_run_num_events => start_run_num_events_sig
1149 );
1150
1151-- Inst_counter_dummy_ts : counter_dummy
1152-- port map(
1153-- clk => clk_50M_sig,
1154-- get_counter => get_ts_counter_sig,
1155-- get_counter_started => get_ts_counter_started_sig,
1156-- get_counter_ready => get_ts_counter_ready_sig,
1157-- counter => timestamp_counter_sig
1158-- );
1159
1160-- Inst_counter_dummy_ot : counter_dummy
1161-- port map(
1162-- clk => clk_50M_sig,
1163-- get_counter => get_ot_counter_sig,
1164-- get_counter_started => get_ot_counter_started_sig,
1165-- get_counter_ready => get_ot_counter_ready_sig,
1166-- counter => on_time_counter_sig
1167-- );
1168
1169 Inst_Timing_counter_ts : Timing_counter
1170 port map(
1171 clk => clk_50M_sig,
1172 enable => '1',
1173 reset => reset_timer_sig,
1174 read_counter => get_ts_counter_sig,
1175 reading_started => get_ts_counter_started_sig,
1176 reading_valid => get_ts_counter_ready_sig,
1177 counter_reading => timestamp_counter_sig
1178 );
1179
1180 Inst_Timing_counter_ot : Timing_counter
1181 port map(
1182 clk => clk_50M_sig,
1183 enable => trigger_active_sig,
1184 reset => reset_timer_sig,
1185 read_counter => get_ot_counter_sig,
1186 reading_started => get_ot_counter_started_sig,
1187 reading_valid => get_ot_counter_ready_sig,
1188 counter_reading => on_time_counter_sig
1189 );
1190
1191 LED_red <= led_sig(3 downto 0);
1192 LED_ye <= led_sig(5 downto 4);
1193 LED_gn <= led_sig(7 downto 6);
1194
1195 TP(32 downto 8) <= (others => '0');
1196 --TP(8) <= clk_50M_sig;
1197 TP( 7 downto 0) <= cc_state_test_sig;
1198
1199 Crate_Res0 <= '1';
1200 Crate_Res1 <= '1';
1201 Crate_Res2 <= '1';
1202 Crate_Res3 <= '1';
1203
1204end Behavioral;
1205
1206
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