source: firmware/FTM/FTM_top.vhd@ 10789

Last change on this file since 10789 was 10779, checked in by weitzel, 13 years ago
some changes in FTM Timing_counter
File size: 51.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 Bus2_TxD_0 : out STD_LOGIC;
153
154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 Bus2_TxD_1 : out STD_LOGIC;
156
157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 Bus2_TxD_2 : out STD_LOGIC;
159
160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 Crate_Res0 : out STD_LOGIC;
180 Crate_Res1 : out STD_LOGIC;
181 Crate_Res2 : out STD_LOGIC;
182 Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 -- RES_p : out STD_LOGIC; -- RES+ Reset
215 -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 -- Cal_0_p : out STD_LOGIC;
233 -- Cal_0_n : out STD_LOGIC;
234 -- Cal_1_p : out STD_LOGIC;
235 -- Cal_1_n : out STD_LOGIC;
236 -- Cal_2_p : out STD_LOGIC;
237 -- Cal_2_n : out STD_LOGIC;
238 -- Cal_3_p : out STD_LOGIC;
239 -- Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 -- Cal_4_p : out STD_LOGIC;
244 -- Cal_4_n : out STD_LOGIC;
245 -- Cal_5_p : out STD_LOGIC;
246 -- Cal_5_n : out STD_LOGIC;
247 -- Cal_6_p : out STD_LOGIC;
248 -- Cal_6_n : out STD_LOGIC;
249 -- Cal_7_p : out STD_LOGIC;
250 -- Cal_7_n : out STD_LOGIC
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 TP : inout STD_LOGIC_VECTOR(32 downto 0)
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_ftu_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_ftu_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic := '0';
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352
353 signal config_trigger_sig : std_logic;
354 signal config_trigger_done_sig : std_logic;
355
356 signal clk_buf_sig : std_logic;
357 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
358 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
359 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
360 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
361 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
362
363 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager
364 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager
365 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast
366
367 signal trigger_active_sig : std_logic; -- initialized in trigger manager
368
369 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
370
371 signal trigger_signal_sig : std_logic := '0';
372 signal TIM_signal_sig : std_logic := '0';
373
374 --signals for FPGA DNA identifier
375 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen
376 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control
377 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen
378
379 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
380
381 signal get_ot_counter_sig : std_logic;
382 signal get_ot_counter_started_sig : std_logic;
383 signal get_ot_counter_ready_sig : std_logic;
384 signal on_time_counter_sig : std_logic_vector(47 downto 0);
385
386 signal get_ts_counter_sig : std_logic;
387 signal get_ts_counter_started_sig : std_logic;
388 signal get_ts_counter_ready_sig : std_logic;
389 signal timestamp_counter_sig : std_logic_vector(47 downto 0);
390
391 signal crate_reset_sig : std_logic;
392 signal crate_reset_ack_sig : std_logic;
393 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0);
394 signal start_run_sig : std_logic;
395 signal start_run_ack_sig : std_logic;
396 signal stop_run_sig : std_logic;
397 signal stop_run_ack_sig : std_logic;
398 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0);
399 signal cc_state_test_sig : std_logic_vector ( 7 downto 0);
400 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0);
401 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0);
402
403 signal trigger_start_sig : std_logic;
404 signal trigger_stop_sig : std_logic;
405
406 signal enable_ID_sending_sig : std_logic;
407 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control
408
409 signal crate_res0_sig : std_logic; -- initialized in FTM_central_control
410 signal crate_res1_sig : std_logic; -- initialized in FTM_central_control
411 signal crate_res2_sig : std_logic; -- initialized in FTM_central_control
412 signal crate_res3_sig : std_logic; -- initialized in FTM_central_control
413
414-- component FTM_clk_gen
415-- port(
416-- clk : IN STD_LOGIC;
417-- rst : IN STD_LOGIC;
418-- clk_1 : OUT STD_LOGIC;
419-- clk_50 : OUT STD_LOGIC;
420-- clk_250 : OUT STD_LOGIC;
421-- clk_250_ps : OUT STD_LOGIC;
422-- ready : OUT STD_LOGIC
423-- );
424-- end component;
425
426 component FTM_clk_gen_2
427 port(
428 clk : IN STD_LOGIC;
429 rst : IN STD_LOGIC;
430 clk_1 : OUT STD_LOGIC;
431 clk_50 : OUT STD_LOGIC;
432 clk_250 : OUT STD_LOGIC;
433 clk_250_ps : OUT STD_LOGIC;
434 ready : OUT STD_LOGIC
435 );
436 end component;
437
438 component FTM_dna_gen
439 port(
440 clk : IN STD_LOGIC;
441 start : IN STD_LOGIC;
442 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
443 ready : OUT STD_LOGIC
444 );
445 end component;
446
447 component trigger_manager
448 port(
449 --clocks
450 clk_50MHz : in std_logic;
451 clk_250MHz : in std_logic;
452 clk_250MHz_180 : in std_logic;
453 --trigger primitives from FTUs
454 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
455 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
456 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
457 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
458 --external signals
459 ext_trig_1 : in std_logic;
460 ext_trig_2 : in std_logic;
461 ext_veto : in std_logic;
462 FAD_busy_0 : in std_logic; --crate 0
463 FAD_busy_1 : in std_logic; --crate 1
464 FAD_busy_2 : in std_logic; --crate 2
465 FAD_busy_3 : in std_logic; --crate 3
466 --control signals from e.g. main control
467 start_run : in std_logic; --enable trigger output
468 stop_run : in std_logic; --disable trigger output
469 new_config : in std_logic;
470 --settings register (see FTM Firmware Specifications)
471 general_settings : in std_logic_vector(15 downto 0);
472 LP_and_PED_freq : in std_logic_vector(15 downto 0);
473 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
474 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
475 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
476 trigger_delay : in std_logic_vector(15 downto 0);
477 TIM_delay : in std_logic_vector(15 downto 0);
478 dead_time : in std_logic_vector(15 downto 0);
479 coinc_window_phys : in std_logic_vector(15 downto 0);
480 coinc_window_calib : in std_logic_vector(15 downto 0);
481 active_FTU_list_0 : in std_logic_vector(15 downto 0);
482 active_FTU_list_1 : in std_logic_vector(15 downto 0);
483 active_FTU_list_2 : in std_logic_vector(15 downto 0);
484 active_FTU_list_3 : in std_logic_vector(15 downto 0);
485 --control signals or information for other entities
486 trigger_ID_read : in std_logic;
487 trig_cnt_copy_read : in std_logic;
488 trigger_ID_ready : out std_logic;
489 trigger_ID : out std_logic_vector(55 downto 0);
490 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
491 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
492 trigger_active : out std_logic; --phys triggers are enabled/active
493 config_done : out std_logic;
494 LP1_pulse : out std_logic; --send start signal to light pulser 1
495 LP2_pulse : out std_logic; --send start signal to light pulser 2
496 --trigger and time marker output signals to FADs
497 trigger_signal : out std_logic;
498 TIM_signal : out std_logic
499 );
500 end component;
501
502 component Clock_cond_interface is
503 port(
504 clk : IN STD_LOGIC;
505 CLK_Clk_Cond : out STD_LOGIC;
506 LE_Clk_Cond : out STD_LOGIC;
507 DATA_Clk_Cond : out STD_LOGIC;
508 SYNC_Clk_Cond : out STD_LOGIC;
509 LD_Clk_Cond : in STD_LOGIC;
510 TIM_Sel : out STD_LOGIC;
511 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
512 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
513 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
514 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
515 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
516 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
517 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
518 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
519 start_config : in STD_LOGIC;
520 config_started : out STD_LOGIC;
521 config_done : out STD_LOGIC;
522 timemarker_select: in STD_LOGIC
523 );
524 end component;
525
526 component FTM_central_control
527 port(
528 clk : IN std_logic;
529 clk_ready : in std_logic;
530 clk_scaler : IN std_logic;
531 new_config : IN std_logic;
532 config_started : OUT std_logic := '0';
533 config_started_ack : IN std_logic;
534 config_start_eth : OUT std_logic := '0';
535 config_started_eth : IN std_logic;
536 config_ready_eth : IN std_logic;
537 config_start_ftu : OUT std_logic := '0';
538 config_started_ftu : IN std_logic;
539 config_ready_ftu : IN std_logic;
540 ping_ftu_start : IN std_logic;
541 ping_ftu_started : OUT std_logic := '0';
542 ping_ftu_ready : OUT std_logic := '0';
543 ping_ftu_start_ftu : OUT std_logic := '0';
544 ping_ftu_started_ftu : IN std_logic;
545 ping_ftu_ready_ftu : IN std_logic;
546 rates_ftu : OUT std_logic := '0';
547 rates_started_ftu : IN std_logic;
548 rates_ready_ftu : IN std_logic;
549 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
550 dd_send : OUT std_logic := '0';
551 dd_send_ack : IN std_logic;
552 dd_send_ready : IN std_logic;
553 dd_block_ready_ftu : out std_logic := '0';
554 dd_block_start_ack_ftu : in std_logic;
555 dd_block_start_ftu : out std_logic := '0';
556 config_start_cc : out std_logic := '0';
557 config_started_cc : in std_logic;
558 config_ready_cc : in std_logic;
559 config_trigger : out std_logic;
560 config_trigger_done : in std_logic;
561 dna_start : out std_logic;
562 dna_ready : in std_logic;
563 crate_reset : IN std_logic;
564 crate_reset_ack : OUT std_logic;
565 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
566 start_run : IN std_logic;
567 start_run_ack : OUT std_logic;
568 stop_run : IN std_logic;
569 stop_run_ack : OUT std_logic;
570 current_cc_state : OUT std_logic_vector (15 DOWNTO 0);
571 cc_state_test : OUT std_logic_vector ( 7 downto 0);
572 start_run_param : IN std_logic_vector (15 DOWNTO 0);
573 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
574 trigger_start : out std_logic;
575 trigger_stop : out std_logic;
576 enable_ID_sending : out std_logic;
577 reset_timer : out std_logic;
578 crate_res_0 : out std_logic;
579 crate_res_1 : out std_logic;
580 crate_res_2 : out std_logic;
581 crate_res_3 : out std_logic
582 );
583 end component;
584
585 component FTM_ftu_control
586 port(
587 clk_50MHz : in std_logic;
588 rx_en : out STD_LOGIC;
589 tx_en : out STD_LOGIC;
590 rx_d_0 : in STD_LOGIC;
591 tx_d_0 : out STD_LOGIC;
592 rx_d_1 : in STD_LOGIC;
593 tx_d_1 : out STD_LOGIC;
594 rx_d_2 : in STD_LOGIC;
595 tx_d_2 : out STD_LOGIC;
596 rx_d_3 : in STD_LOGIC;
597 tx_d_3 : out STD_LOGIC;
598 new_config : in std_logic;
599 ping_all : in std_logic;
600 read_rates : in std_logic;
601 read_rates_started : out std_logic := '0';
602 read_rates_done : out std_logic := '0';
603 new_config_started : out std_logic := '0';
604 new_config_done : out std_logic := '0';
605 ping_all_started : out std_logic := '0';
606 ping_all_done : out std_logic := '0';
607 ftu_active_cr0 : in std_logic_vector (15 downto 0);
608 ftu_active_cr1 : in std_logic_vector (15 downto 0);
609 ftu_active_cr2 : in std_logic_vector (15 downto 0);
610 ftu_active_cr3 : in std_logic_vector (15 downto 0);
611 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
612 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
613 ftu_error_send : out std_logic := '0';
614 ftu_error_send_ack : in std_logic;
615 ftu_error_send_ready : in std_logic;
616 static_RAM_busy : in std_logic;
617 static_RAM_started : in std_logic;
618 static_RAM_ready : in std_logic;
619 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
620 read_static_RAM : out std_logic := '0';
621 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
622 dynamic_RAM_busy : in std_logic;
623 dynamic_RAM_started : in std_logic;
624 dynamic_RAM_ready : in std_logic;
625 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
626 write_dynamic_RAM : out std_logic := '0';
627 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
628 FTUlist_RAM_busy : in std_logic;
629 FTUlist_RAM_started : in std_logic;
630 FTUlist_RAM_ready : in std_logic;
631 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
632 write_FTUlist_RAM : out std_logic := '0';
633 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
634 );
635 end component;
636
637 component FTM_fad_broadcast
638 port(
639 clk_50MHz : in std_logic;
640 rx_en : out STD_LOGIC;
641 tx_en : out STD_LOGIC;
642 rx_d_0 : in STD_LOGIC;
643 tx_d_0 : out STD_LOGIC;
644 rx_d_1 : in STD_LOGIC;
645 tx_d_1 : out STD_LOGIC;
646 rx_d_2 : in STD_LOGIC;
647 tx_d_2 : out STD_LOGIC;
648 rx_d_3 : in STD_LOGIC;
649 tx_d_3 : out STD_LOGIC;
650 enable_ID_sending : in std_logic;
651 TIM_source : in std_logic;
652 LP_settings : in std_logic_vector(3 downto 0);
653 trigger_ID_ready : in std_logic;
654 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
655 trigger_ID_read : out std_logic
656 );
657 end component;
658
659 component ethernet_modul
660 port(
661 wiz_reset : OUT std_logic := '1';
662 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
663 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
664 wiz_cs : OUT std_logic := '1';
665 wiz_wr : OUT std_logic := '1';
666 wiz_rd : OUT std_logic := '1';
667 wiz_int : IN std_logic ;
668 clk : IN std_logic ;
669 sd_ready : OUT std_logic ;
670 sd_busy : OUT std_logic ;
671 led : OUT std_logic_vector (7 DOWNTO 0);
672 sd_read_ftu : IN std_logic ;
673 sd_started_ftu : OUT std_logic := '0';
674 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
675 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
676 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
677 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
678 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
679 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
680 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
681 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
682 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
683 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
684 dead_time : OUT std_logic_vector (15 DOWNTO 0);
685 general_settings : OUT std_logic_vector (15 DOWNTO 0);
686 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
687 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
688 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
689 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
690 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
691 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
692 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
693 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
694 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
695 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
696 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
697 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
698 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
699 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
700 new_config : OUT std_logic := '0';
701 config_started : IN std_logic ;
702 config_start_eth : IN std_logic ;
703 config_started_eth : OUT std_logic := '0';
704 config_ready_eth : OUT std_logic := '0';
705 config_started_ack : OUT std_logic := '0';
706 fl_busy : OUT std_logic ;
707 fl_ready : OUT std_logic ;
708 fl_write_ftu : IN std_logic ;
709 fl_started_ftu : OUT std_logic := '0';
710 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
711 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
712 ping_ftu_start : OUT std_logic := '0';
713 ping_ftu_started : IN std_logic ;
714 ping_ftu_ready : IN std_logic ;
715 dd_write_ftu : IN std_logic ;
716 dd_started_ftu : OUT std_logic := '0';
717 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
718 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
719 dd_busy : OUT std_logic ;
720 dd_ready : OUT std_logic ;
721 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
722 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
723 --new stuff
724 dd_block_ready_ftu : IN std_logic;
725 dd_block_start_ack_ftu : OUT std_logic := '0';
726 dd_block_start_ftu : IN std_logic;
727 dd_send : IN std_logic;
728 dd_send_ack : OUT std_logic := '1';
729 dd_send_ready : OUT std_logic := '1';
730 --very new stuff
731 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
732 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
733 ftu_error_send : IN std_logic;
734 ftu_error_send_ack : OUT std_logic := '1';
735 ftu_error_send_ready : OUT std_logic := '1';
736 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
737 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
738 trigger_counter_read : OUT std_logic := '0';
739 trigger_counter_valid : IN std_logic;
740 --newest stuff
741 board_id : IN std_logic_vector (63 DOWNTO 0);
742 get_ts_counter : OUT std_logic := '0';
743 get_ts_counter_ready : IN std_logic;
744 get_ts_counter_started : IN std_logic;
745 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
746 get_ot_counter : OUT std_logic := '0';
747 get_ot_counter_ready : IN std_logic;
748 get_ot_counter_started : IN std_logic;
749 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
750 temp_sensor_array : IN sensor_array_type;
751 temp_sensor_ready : IN std_logic;
752 crate_reset : OUT std_logic := '0';
753 crate_reset_ack : IN std_logic;
754 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
755 start_run : OUT std_logic := '0';
756 start_run_ack : IN std_logic;
757 stop_run : OUT std_logic := '0';
758 stop_run_ack : IN std_logic;
759 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
760 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
761 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0')
762 );
763 end component;
764
765-- component counter_dummy IS
766-- PORT(
767-- clk : IN std_logic;
768-- get_counter : IN std_logic;
769-- get_counter_started : OUT std_logic := '0';
770-- get_counter_ready : OUT std_logic := '0';
771-- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
772-- );
773-- end component;
774
775 component Timing_counter is
776 port(
777 clk : in STD_LOGIC; -- 50 MHz system clock
778 enable : in STD_LOGIC; -- enable counter
779 reset : in Std_LOGIC; -- reset counter
780 read_counter : in STD_LOGIC; -- read counter
781 reading_started : out STD_LOGIC;
782 reading_valid : out STD_LOGIC; -- counter reading at output ready
783 counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0)
784 );
785 end component;
786
787
788begin
789
790-- -- IBUFG: Single-ended global clock input buffer
791-- -- Spartan-3A
792-- -- Xilinx HDL Language Template, version 11.4
793
794-- IBUFG_inst : IBUFG
795-- generic map (
796-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
797-- -- "0"-"16"
798-- IOSTANDARD => "DEFAULT")
799-- port map (
800-- O => clk_buf_sig, -- Clock buffer output
801-- I => clk -- Clock buffer input (connect directly to top-level port)
802-- );
803
804-- Inst_FTM_clk_gen : FTM_clk_gen
805-- port map(
806-- clk => clk_buf_sig,
807-- rst => reset_sig,
808-- clk_1 => clk_1M_sig,
809-- clk_50 => clk_50M_sig,
810-- clk_250 => clk_250M_sig,
811-- clk_250_ps => clk_250M_ps_sig,
812-- ready => clk_ready_sig
813-- );
814
815 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
816 port map(
817 clk => clk,
818 rst => reset_sig,
819 clk_1 => clk_1M_sig,
820 clk_50 => clk_50M_sig,
821 clk_250 => clk_250M_sig,
822 clk_250_ps => clk_250M_ps_sig,
823 ready => clk_ready_sig
824 );
825
826 Inst_FTM_dna_gen : FTM_dna_gen
827 port map(
828 clk => clk_50M_sig,
829 start => dna_start_sig,
830 dna => dna_sig,
831 ready => dna_ready_sig
832 );
833
834 --differential output buffer for trigger signal
835 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
836 port map(
837 O => TRG_p,
838 OB => TRG_n,
839 I => trigger_signal_sig
840 );
841
842 --differential output buffer for trigger signal
843 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
844 port map(
845 O => TIM_Run_p,
846 OB => TIM_Run_n,
847 I => TIM_signal_sig
848 );
849
850 Inst_trigger_manager : trigger_manager
851 port map(
852 --clocks
853 clk_50MHz => clk_50M_sig,
854 clk_250MHz => clk_250M_sig,
855 clk_250MHz_180 => clk_250M_ps_sig,
856 --trigger primitives from FTUs
857 trig_prim_0 => Trig_Prim_A, --crate 0
858 trig_prim_1 => Trig_Prim_B, --crate 1
859 trig_prim_2 => Trig_Prim_C, --crate 2
860 trig_prim_3 => Trig_Prim_D, --crate 3
861 --external signals
862 ext_trig_1 => ext_Trig(1),
863 ext_trig_2 => ext_Trig(2),
864 ext_veto => Veto,
865 FAD_busy_0 => Busy0, --crate 0
866 FAD_busy_1 => Busy1, --crate 1
867 FAD_busy_2 => Busy2, --crate 2
868 FAD_busy_3 => Busy3, --crate 3
869 --control signals from e.g. main control
870 start_run => trigger_start_sig, --enable trigger output
871 stop_run => trigger_stop_sig, --disable trigger output
872 new_config => config_trigger_sig,
873 --settings register (see FTM Firmware Specifications)
874 general_settings => general_settings_sig,
875 LP_and_PED_freq => lp_pt_freq_sig,
876 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
877 maj_coinc_n_phys => coin_n_p_sig,
878 maj_coinc_n_calib => coin_n_c_sig,
879 trigger_delay => trigger_delay_sig,
880 TIM_delay => timemarker_delay_sig,
881 dead_time => dead_time_sig,
882 coinc_window_phys => coin_win_p_sig,
883 coinc_window_calib => coin_win_c_sig,
884 active_FTU_list_0 => ftu_active_cr0_sig,
885 active_FTU_list_1 => ftu_active_cr1_sig,
886 active_FTU_list_2 => ftu_active_cr2_sig,
887 active_FTU_list_3 => ftu_active_cr3_sig,
888 --control signals or information for other entities
889 trigger_ID_read => trigger_ID_read_sig,
890 trig_cnt_copy_read => trigger_counter_read_sig,
891 trigger_ID_ready => trigger_ID_ready_sig,
892 trigger_ID => trigger_ID_sig,
893 trig_cnt_copy => trigger_counter_sig, --counter reading
894 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
895 trigger_active => trigger_active_sig, --phys triggers are enabled/active
896 config_done => config_trigger_done_sig,
897 LP1_pulse => open, --send start signal to light pulser 1
898 LP2_pulse => open, --send start signal to light pulser 2
899 --trigger and time marker output signals to FADs
900 trigger_signal => trigger_signal_sig,
901 TIM_signal => TIM_signal_sig
902 );
903
904 Inst_Clock_cond_interface : Clock_cond_interface
905 port map(
906 clk => clk_50M_sig,
907 CLK_Clk_Cond => CLK_Clk_Cond,
908 LE_Clk_Cond => LE_Clk_Cond,
909 DATA_Clk_Cond => DATA_Clk_Cond,
910 SYNC_Clk_Cond => SYNC_Clk_Cond,
911 LD_Clk_Cond => LD_Clk_Cond,
912 TIM_Sel => TIM_Sel,
913 cc_R0 => cc_R0_sig,
914 cc_R1 => cc_R1_sig,
915 cc_R8 => cc_R8_sig,
916 cc_R9 => cc_R9_sig,
917 cc_R11 => cc_R11_sig,
918 cc_R13 => cc_R13_sig,
919 cc_R14 => cc_R14_sig,
920 cc_R15 => cc_R15_sig,
921 start_config => config_start_cc_sig,
922 config_started => config_started_cc_sig,
923 config_done => config_ready_cc_sig,
924 timemarker_select => general_settings_sig(0)
925 );
926
927 Inst_FTM_central_control : FTM_central_control
928 port map(
929 clk => clk_50M_sig,
930 clk_ready => clk_ready_sig,
931 clk_scaler => clk_1M_sig,
932 new_config => new_config_sig,
933 config_started => config_started_sig,
934 config_started_ack => config_started_ack_sig,
935 config_start_eth => config_start_eth_sig,
936 config_started_eth => config_started_eth_sig,
937 config_ready_eth => config_ready_eth_sig,
938 config_start_ftu => config_start_ftu_sig,
939 config_started_ftu => config_started_ftu_sig,
940 config_ready_ftu => config_ready_ftu_sig,
941 ping_ftu_start => ping_ftu_start_sig,
942 ping_ftu_started => ping_ftu_started_sig,
943 ping_ftu_ready => ping_ftu_ready_sig,
944 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
945 ping_ftu_started_ftu => ping_ftu_started1_sig,
946 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
947 rates_ftu => rates_ftu_start_sig,
948 rates_started_ftu => rates_ftu_started_sig,
949 rates_ready_ftu => rates_ftu_ready_sig,
950 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
951 dd_send => dd_send_sig,
952 dd_send_ack => dd_send_ack_sig,
953 dd_send_ready => dd_send_ready_sig,
954 dd_block_ready_ftu => dd_block_ready_ftu_sig,
955 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
956 dd_block_start_ftu => dd_block_start_ftu_sig,
957 config_start_cc => config_start_cc_sig,
958 config_started_cc => config_started_cc_sig,
959 config_ready_cc => config_ready_cc_sig,
960 config_trigger => config_trigger_sig,
961 config_trigger_done => config_trigger_done_sig,
962 dna_start => dna_start_sig,
963 dna_ready => dna_ready_sig,
964 crate_reset => crate_reset_sig,
965 crate_reset_ack => crate_reset_ack_sig,
966 crate_reset_param => crate_reset_param_sig,
967 start_run => start_run_sig,
968 start_run_ack => start_run_ack_sig,
969 stop_run => stop_run_sig,
970 stop_run_ack => stop_run_ack_sig,
971 current_cc_state => current_cc_state_sig,
972 cc_state_test => cc_state_test_sig,
973 start_run_param => start_run_param_sig,
974 start_run_num_events => start_run_num_events_sig,
975 trigger_start => trigger_start_sig,
976 trigger_stop => trigger_stop_sig,
977 enable_ID_sending => enable_ID_sending_sig,
978 reset_timer => reset_timer_sig,
979 crate_res_0 => crate_res0_sig,
980 crate_res_1 => crate_res1_sig,
981 crate_res_2 => crate_res2_sig,
982 crate_res_3 => crate_res3_sig
983 );
984
985 Inst_FTM_ftu_control : FTM_ftu_control
986 port map(
987 clk_50MHz => clk_50M_sig,
988 rx_en => Bus1_Rx_En,
989 tx_en => Bus1_Tx_En,
990 rx_d_0 => Bus1_RxD_0,
991 tx_d_0 => Bus1_TxD_0,
992 rx_d_1 => Bus1_RxD_1,
993 tx_d_1 => Bus1_TxD_1,
994 rx_d_2 => Bus1_RxD_2,
995 tx_d_2 => Bus1_TxD_2,
996 rx_d_3 => Bus1_RxD_3,
997 tx_d_3 => Bus1_TxD_3,
998 new_config => config_start_ftu_sig,
999 ping_all => ping_ftu_start_ftu_sig,
1000 read_rates => rates_ftu_start_sig,
1001 read_rates_started => rates_ftu_started_sig,
1002 read_rates_done => rates_ftu_ready_sig,
1003 new_config_started => config_started_ftu_sig,
1004 new_config_done => config_ready_ftu_sig,
1005 ping_all_started => ping_ftu_started1_sig,
1006 ping_all_done => ping_ftu_ready1_sig,
1007 ftu_active_cr0 => ftu_active_cr0_sig,
1008 ftu_active_cr1 => ftu_active_cr1_sig,
1009 ftu_active_cr2 => ftu_active_cr2_sig,
1010 ftu_active_cr3 => ftu_active_cr3_sig,
1011 ftu_error_calls => ftu_error_calls_sig,
1012 ftu_error_data => ftu_error_data_sig,
1013 ftu_error_send => ftu_error_send_sig,
1014 ftu_error_send_ack => ftu_error_send_ack_sig,
1015 ftu_error_send_ready=> ftu_error_send_ready_sig,
1016 static_RAM_busy => sd_busy_sig,
1017 static_RAM_started => sd_started_ftu_sig,
1018 static_RAM_ready => sd_ready_sig,
1019 data_static_RAM => sd_data_out_ftu_sig,
1020 read_static_RAM => sd_read_ftu_sig,
1021 addr_static_RAM => sd_addr_ftu_sig,
1022 dynamic_RAM_busy => dd_busy_sig,
1023 dynamic_RAM_started => dd_started_ftu_sig,
1024 dynamic_RAM_ready => dd_ready_sig,
1025 data_dynamic_RAM => dd_data_sig,
1026 write_dynamic_RAM => dd_write_sig,
1027 addr_dynamic_RAM => dd_addr_sig,
1028 FTUlist_RAM_busy => fl_busy_sig,
1029 FTUlist_RAM_started => fl_started_ftu_sig,
1030 FTUlist_RAM_ready => fl_ready_sig,
1031 data_FTUlist_RAM => fl_data_sig,
1032 write_FTUlist_RAM => fl_write_sig,
1033 addr_FTUlist_RAM => fl_addr_sig
1034 );
1035
1036 Inst_FTM_fad_broadcast : FTM_fad_broadcast
1037 port map(
1038 clk_50MHz => clk_50M_sig,
1039 rx_en => Bus2_Rx_En,
1040 tx_en => Bus2_Tx_En,
1041 rx_d_0 => Bus2_RxD_0,
1042 tx_d_0 => Bus2_TxD_0,
1043 rx_d_1 => Bus2_RxD_1,
1044 tx_d_1 => Bus2_TxD_1,
1045 rx_d_2 => Bus2_RxD_2,
1046 tx_d_2 => Bus2_TxD_2,
1047 rx_d_3 => Bus2_RxD_3,
1048 tx_d_3 => Bus2_TxD_3,
1049 enable_ID_sending => enable_ID_sending_sig,
1050 TIM_source => general_settings_sig(0),
1051 LP_settings => "0000",
1052 trigger_ID_ready => trigger_ID_ready_sig,
1053 trigger_ID => trigger_ID_sig,
1054 trigger_ID_read => trigger_ID_read_sig
1055 );
1056
1057 Inst_ethernet_modul : ethernet_modul
1058 port map(
1059 wiz_reset => W_RES,
1060 wiz_addr => W_A,
1061 wiz_data => W_D,
1062 wiz_cs => W_CS,
1063 wiz_wr => W_WR,
1064 wiz_rd => W_RD,
1065 wiz_int => W_INT,
1066 clk => clk_50M_sig,
1067 sd_ready => sd_ready_sig,
1068 sd_busy => sd_busy_sig,
1069 led => led_sig,
1070 sd_read_ftu => sd_read_ftu_sig,
1071 sd_started_ftu => sd_started_ftu_sig,
1072 cc_R0 => cc_R0_sig,
1073 cc_R1 => cc_R1_sig,
1074 cc_R11 => cc_R11_sig,
1075 cc_R13 => cc_R13_sig,
1076 cc_R14 => cc_R14_sig,
1077 cc_R15 => cc_R15_sig,
1078 cc_R8 => cc_R8_sig,
1079 cc_R9 => cc_R9_sig,
1080 coin_n_c => coin_n_c_sig,
1081 coin_n_p => coin_n_p_sig,
1082 dead_time => dead_time_sig,
1083 general_settings => general_settings_sig,
1084 lp1_amplitude => lp1_amplitude_sig,
1085 lp1_delay => lp1_delay_sig,
1086 lp2_amplitude => lp2_amplitude_sig,
1087 lp2_delay => lp2_delay_sig,
1088 lp_pt_freq => lp_pt_freq_sig,
1089 lp_pt_ratio => lp_pt_ratio_sig,
1090 timemarker_delay => timemarker_delay_sig,
1091 trigger_delay => trigger_delay_sig,
1092 sd_addr_ftu => sd_addr_ftu_sig,
1093 sd_data_out_ftu => sd_data_out_ftu_sig,
1094 ftu_active_cr0 => ftu_active_cr0_sig,
1095 ftu_active_cr1 => ftu_active_cr1_sig,
1096 ftu_active_cr2 => ftu_active_cr2_sig,
1097 ftu_active_cr3 => ftu_active_cr3_sig,
1098 new_config => new_config_sig,
1099 config_started => config_started_sig,
1100 config_start_eth => config_start_eth_sig,
1101 config_started_eth => config_started_eth_sig,
1102 config_ready_eth => config_ready_eth_sig,
1103 config_started_ack => config_started_ack_sig,
1104 fl_busy => fl_busy_sig,
1105 fl_ready => fl_ready_sig,
1106 fl_write_ftu => fl_write_sig,
1107 fl_started_ftu => fl_started_ftu_sig,
1108 fl_addr_ftu => fl_addr_sig,
1109 fl_data_in_ftu => fl_data_sig,
1110 ping_ftu_start => ping_ftu_start_sig,
1111 ping_ftu_started => ping_ftu_started_sig,
1112 ping_ftu_ready => ping_ftu_ready_sig,
1113 dd_write_ftu => dd_write_sig,
1114 dd_started_ftu => dd_started_ftu_sig,
1115 dd_data_in_ftu => dd_data_sig,
1116 dd_addr_ftu => dd_addr_sig,
1117 dd_busy => dd_busy_sig,
1118 dd_ready => dd_ready_sig,
1119 coin_win_c => coin_win_c_sig,
1120 coin_win_p => coin_win_p_sig,
1121 --new stuff
1122 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1123 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1124 dd_block_start_ftu => dd_block_start_ftu_sig,
1125 dd_send => dd_send_sig,
1126 dd_send_ack => dd_send_ack_sig,
1127 dd_send_ready => dd_send_ready_sig,
1128 --very new stuff
1129 ftu_error_calls => ftu_error_calls_sig,
1130 ftu_error_data => ftu_error_data_sig,
1131 ftu_error_send => ftu_error_send_sig,
1132 ftu_error_send_ack => ftu_error_send_ack_sig,
1133 ftu_error_send_ready => ftu_error_send_ready_sig,
1134 prescaling_FTU01 => prescaling_FTU01_sig,
1135 trigger_counter => trigger_counter_sig,
1136 trigger_counter_read => trigger_counter_read_sig,
1137 trigger_counter_valid => trigger_counter_valid_sig,
1138 --newest stuff
1139 board_id => dna_sig,
1140 get_ts_counter => get_ts_counter_sig,
1141 get_ts_counter_ready => get_ts_counter_ready_sig,
1142 get_ts_counter_started => get_ts_counter_started_sig,
1143 timestamp_counter => timestamp_counter_sig,
1144 get_ot_counter => get_ot_counter_sig,
1145 get_ot_counter_ready => get_ot_counter_ready_sig,
1146 get_ot_counter_started => get_ot_counter_started_sig,
1147 on_time_counter => on_time_counter_sig,
1148 temp_sensor_array => (35, 45, 55, 65),
1149 temp_sensor_ready => '1',
1150 crate_reset => crate_reset_sig,
1151 crate_reset_ack => crate_reset_ack_sig,
1152 crate_reset_param => crate_reset_param_sig,
1153 start_run => start_run_sig,
1154 start_run_ack => start_run_ack_sig,
1155 stop_run => stop_run_sig,
1156 stop_run_ack => stop_run_ack_sig,
1157 current_cc_state => current_cc_state_sig,
1158 start_run_param => start_run_param_sig,
1159 start_run_num_events => start_run_num_events_sig
1160 );
1161
1162-- Inst_counter_dummy_ts : counter_dummy
1163-- port map(
1164-- clk => clk_50M_sig,
1165-- get_counter => get_ts_counter_sig,
1166-- get_counter_started => get_ts_counter_started_sig,
1167-- get_counter_ready => get_ts_counter_ready_sig,
1168-- counter => timestamp_counter_sig
1169-- );
1170
1171-- Inst_counter_dummy_ot : counter_dummy
1172-- port map(
1173-- clk => clk_50M_sig,
1174-- get_counter => get_ot_counter_sig,
1175-- get_counter_started => get_ot_counter_started_sig,
1176-- get_counter_ready => get_ot_counter_ready_sig,
1177-- counter => on_time_counter_sig
1178-- );
1179
1180 Inst_Timing_counter_ts : Timing_counter
1181 port map(
1182 clk => clk_50M_sig,
1183 enable => '1',
1184 reset => reset_timer_sig,
1185 read_counter => get_ts_counter_sig,
1186 reading_started => get_ts_counter_started_sig,
1187 reading_valid => get_ts_counter_ready_sig,
1188 counter_reading => timestamp_counter_sig
1189 );
1190
1191 Inst_Timing_counter_ot : Timing_counter
1192 port map(
1193 clk => clk_50M_sig,
1194 enable => trigger_active_sig,
1195 reset => reset_timer_sig,
1196 read_counter => get_ot_counter_sig,
1197 reading_started => get_ot_counter_started_sig,
1198 reading_valid => get_ot_counter_ready_sig,
1199 counter_reading => on_time_counter_sig
1200 );
1201
1202 LED_red <= led_sig(3 downto 0);
1203 LED_ye <= led_sig(5 downto 4);
1204 LED_gn <= led_sig(7 downto 6);
1205
1206 TP(32 downto 8) <= (others => '0');
1207 --TP(8) <= clk_50M_sig;
1208 TP( 7 downto 0) <= cc_state_test_sig;
1209
1210 Crate_Res0 <= crate_res0_sig;
1211 Crate_Res1 <= crate_res1_sig;
1212 Crate_Res2 <= crate_res2_sig;
1213 Crate_Res3 <= crate_res3_sig;
1214
1215end Behavioral;
1216
1217
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