source: firmware/FTM/FTM_top_tb.vhd@ 10094

Last change on this file since 10094 was 10067, checked in by weitzel, 14 years ago
Skeleton of FTM_top and FTM_top_tb added
File size: 16.6 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08.12.2010
6-- Design Name:
7-- Module Name: FTM_top_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for FTM firmware
12--
13-- VHDL Test Bench Created by ISE for module: FTM_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_top_tb is
37end FTU_top_tb;
38
39architecture behavior of FTU_top_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTM_top
44 port(
45
46 -- Clock
47 clk : IN STD_LOGIC; -- external clock from oscillator U47
48
49 -- connection to the WIZnet W5300 ethernet controller
50 -------------------------------------------------------------------------------
51 -- W5300 data bus
52 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
53
54 -- W5300 address bus
55 W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
56 -- the W5300 is operated in the
57 -- 16-bit mode
58
59 -- W5300 control signals
60 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
61 -- W_CS is also routed to testpoint JP7
62 W_CS : out STD_LOGIC; -- W5300 chip select
63 W_INT : IN STD_LOGIC; -- interrupt
64 W_RD : out STD_LOGIC; -- read
65 W_WR : out STD_LOGIC; -- write
66 W_RES : out STD_LOGIC; -- reset W5300 chip
67
68 -- W5300 buffer ready indicator
69 W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
70
71 -- testpoints (T18) associated with the W5300
72 W_T : inout STD_LOGIC_VECTOR(3 downto 0);
73
74
75 -- SPI Interface
76 -- connection to the EEPROM U36 (AL25L016M) and
77 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
78 -------------------------------------------------------------------------------
79 S_CLK : out STD_LOGIC; -- SPI clock
80
81 -- EEPROM
82 -- MOSI : out STD_LOGIC; -- master out slave in
83 -- MISO : in STD_LOGIC; -- master in slave out
84 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
85
86 -- temperature sensors U45, U46, U48 and U49
87 SIO : inout STD_LOGIC; -- serial IO
88 TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
89
90
91 -- Trigger primitives inputs
92 -------------------------------------------------------------------------------
93 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
94 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
95 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
96 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
97
98
99 -- NIM inputs
100 ------------------------------------------------------------------------------
101 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
102 Veto : in STD_LOGIC; -- trigger veto input
103 NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
104
105 -- alternative external clock input for FPGA
106 NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -------------------------------------------------------------------------------
118 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
119 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
120 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
121
122 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
123 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
124
125
126 -- various RS-485 Interfaces
127 -------------------------------------------------------------------------------
128 -- Bus 1: FTU slow control
129 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
130 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
131
132 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
133 Bus1_TxD_0 : out STD_LOGIC;
134
135 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
136 Bus1_TxD_1 : out STD_LOGIC;
137
138 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
139 Bus1_TxD_2 : out STD_LOGIC;
140
141 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
142 Bus1_TxD_3 : out STD_LOGIC;
143
144
145 -- Bus 2: Trigger-ID to FAD boards
146 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
147 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
148
149 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
150 Bus2_TxD_0 : out STD_LOGIC;
151
152 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
153 Bus2_TxD_1 : out STD_LOGIC;
154
155 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
156 Bus2_TxD_2 : out STD_LOGIC;
157
158 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
159 Bus2_TxD_3 : out STD_LOGIC;
160
161
162 -- auxiliary access
163 -- Aux_Rx_D : in STD_LOGIC;
164 -- Aux_Tx_D : out STD_LOGIC;
165 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
166 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
167
168
169 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
170 -- TrID_Rx_D : in STD_LOGIC;
171 -- TrID_Tx_D : out STD_LOGIC;
172
173
174 -- Crate-Resets
175 -------------------------------------------------------------------------------
176 Crate_Res0 : out STD_LOGIC;
177 Crate_Res1 : out STD_LOGIC;
178 Crate_Res2 : out STD_LOGIC;
179 Crate_Res3 : out STD_LOGIC;
180
181
182 -- Busy signals from the FAD boards
183 -------------------------------------------------------------------------------
184 Busy0 : in STD_LOGIC;
185 Busy1 : in STD_LOGIC;
186 Busy2 : in STD_LOGIC;
187 Busy3 : in STD_LOGIC;
188
189
190 -- NIM outputs
191 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
192 -------------------------------------------------------------------------------
193 -- calibration
194 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
195 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
196 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
197 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
198
199 -- auxiliarry / spare NIM outputs
200 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
201 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
202 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
203 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
204
205
206 -- fast control signal outputs
207 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
208 -------------------------------------------------------------------------------
209 RES_p : out STD_LOGIC; -- RES+ Reset
210 RES_n : out STD_LOGIC; -- RES-
211
212 TRG_p : out STD_LOGIC; -- TRG+ Trigger
213 TRG_n : out STD_LOGIC; -- TRG-
214
215 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
216 TIM_Run_n : out STD_LOGIC; -- TIM_Run-
217 TIM_Sel : out STD_LOGIC; -- Time Marker selector
218
219 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
220
221
222 -- LVDS calibration outputs
223 -------------------------------------------------------------------------------
224 -- to connector J13
225 -- for light pulsar in the mirror dish
226 Cal_0_p : out STD_LOGIC;
227 Cal_0_n : out STD_LOGIC;
228 Cal_1_p : out STD_LOGIC;
229 Cal_1_n : out STD_LOGIC;
230 Cal_2_p : out STD_LOGIC;
231 Cal_2_n : out STD_LOGIC;
232 Cal_3_p : out STD_LOGIC;
233 Cal_3_n : out STD_LOGIC;
234
235 -- to connector J12
236 -- for light pulsar inside shutter
237 Cal_4_p : out STD_LOGIC;
238 Cal_4_n : out STD_LOGIC;
239 Cal_5_p : out STD_LOGIC;
240 Cal_5_n : out STD_LOGIC;
241 Cal_6_p : out STD_LOGIC;
242 Cal_6_n : out STD_LOGIC;
243 Cal_7_p : out STD_LOGIC;
244 Cal_7_n : out STD_LOGIC
245
246
247 -- Testpoints
248 -------------------------------------------------------------------------------
249 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
250 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
251
252 -- Board ID - inputs
253 -- local board-ID "solder programmable"
254 -- all on 'input only' pins
255 -------------------------------------------------------------------------------
256 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
257
258 );
259 end component;
260
261 --Inputs
262 signal clk_sig : STD_LOGIC := '0';
263 signal W_INT_sig : STD_LOGIC := '0';
264 signal W_BRDY_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
265 signal Trig_Prim_A_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
266 signal Trig_Prim_B_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
267 signal Trig_Prim_C_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
268 signal Trig_Prim_D_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
269 signal ext_Trig_sig : STD_LOGIC_VECTOR(2 downto 1) := (others => '0');
270 signal Veto_sig : STD_LOGIC := '0';
271 signal NIM_In_sig : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
272 signal NIM_In3_GCLK_sig : STD_LOGIC := '0';
273 signal LD_Clk_Cond_sig : STD_LOGIC := '1';
274 signal Bus1_RxD_0_sig : STD_LOGIC := '1';
275 signal Bus1_RxD_1_sig : STD_LOGIC := '1';
276 signal Bus1_RxD_2_sig : STD_LOGIC := '1';
277 signal Bus1_RxD_3_sig : STD_LOGIC := '1';
278 signal Bus2_RxD_0_sig : STD_LOGIC := '1';
279 signal Bus2_RxD_1_sig : STD_LOGIC := '1';
280 signal Bus2_RxD_2_sig : STD_LOGIC := '1';
281 signal Bus2_RxD_3_sig : STD_LOGIC := '1';
282 signal Busy0_sig : STD_LOGIC := '0';
283 signal Busy1_sig : STD_LOGIC := '0';
284 signal Busy2_sig : STD_LOGIC := '0';
285 signal Busy3_sig : STD_LOGIC := '0';
286
287 --Input/Output Pins
288 signal W_D_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
289 signal W_T_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
290 signal SIO_sig : STD_LOGIC := '0';
291
292 --Outputs
293 signal W_A_sig : STD_LOGIC_VECTOR(9 downto 1);
294 signal W_CS_sig : STD_LOGIC;
295 signal W_RD_sig : STD_LOGIC;
296 signal W_WR_sig : STD_LOGIC;
297 signal W_RES_sig : STD_LOGIC;
298 signal S_CLK_sig : STD_LOGIC;
299 signal TS_CS_sig : STD_LOGIC_VECTOR(3 downto 0);
300 signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0);
301 signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0);
302 signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0);
303 signal CLK_Clk_Cond_sig : STD_LOGIC;
304 signal LE_Clk_Cond_sig : STD_LOGIC;
305 signal DATA_Clk_Cond_sig : STD_LOGIC;
306 signal SYNC_Clk_Cond_sig : STD_LOGIC;
307 signal Bus1_Tx_En_sig : STD_LOGIC;
308 signal Bus1_Rx_En_sig : STD_LOGIC;
309 signal Bus1_TxD_0_sig : STD_LOGIC;
310 signal Bus1_TxD_1_sig : STD_LOGIC;
311 signal Bus1_TxD_2_sig : STD_LOGIC;
312 signal Bus1_TxD_3_sig : STD_LOGIC;
313 signal Bus2_Tx_En_sig : STD_LOGIC;
314 signal Bus2_Rx_En_sig : STD_LOGIC;
315 signal Bus2_TxD_0_sig : STD_LOGIC;
316 signal Bus2_TxD_1_sig : STD_LOGIC;
317 signal Bus2_TxD_2_sig : STD_LOGIC;
318 signal Bus2_TxD_3_sig : STD_LOGIC;
319 signal Crate_Res0_sig : STD_LOGIC;
320 signal Crate_Res1_sig : STD_LOGIC;
321 signal Crate_Res2_sig : STD_LOGIC;
322 signal Crate_Res3_sig : STD_LOGIC;
323 signal RES_p_sig : STD_LOGIC;
324 signal RES_n_sig : STD_LOGIC;
325 signal TRG_p_sig : STD_LOGIC;
326 signal TRG_n_sig : STD_LOGIC;
327 signal TIM_Run_p_sig : STD_LOGIC;
328 signal TIM_Run_n_sig : STD_LOGIC;
329 signal TIM_Sel_sig : STD_LOGIC;
330 signal Cal_0_p_sig : STD_LOGIC;
331 signal Cal_0_n_sig : STD_LOGIC;
332 signal Cal_1_p_sig : STD_LOGIC;
333 signal Cal_1_n_sig : STD_LOGIC;
334 signal Cal_2_p_sig : STD_LOGIC;
335 signal Cal_2_n_sig : STD_LOGIC;
336 signal Cal_3_p_sig : STD_LOGIC;
337 signal Cal_3_n_sig : STD_LOGIC;
338 signal Cal_4_p_sig : STD_LOGIC;
339 signal Cal_4_n_sig : STD_LOGIC;
340 signal Cal_5_p_sig : STD_LOGIC;
341 signal Cal_5_n_sig : STD_LOGIC;
342 signal Cal_6_p_sig : STD_LOGIC;
343 signal Cal_6_n_sig : STD_LOGIC;
344 signal Cal_7_p_sig : STD_LOGIC;
345 signal Cal_7_n_sig : STD_LOGIC;
346
347 -- Clock period definitions
348 constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47
349
350begin
351
352 -- Instantiate the Unit Under Test (UUT)
353 uut: FTM_top
354 port map(
355 clk =>clk_sig,
356 W_D =>W_D_sig,
357 W_A =>W_A_sig,
358 W_CS =>W_CS_sig,
359 W_INT =>W_INT_sig,
360 W_RD =>W_RD_sig,
361 W_WR =>W_WR_sig,
362 W_RES =>W_RES_sig,
363 W_BRDY =>W_BRDY_sig,
364 W_T =>W_T_sig,
365 S_CLK =>S_CLK_sig,
366 SIO =>SIO_sig,
367 TS_CS =>TS_CS_sig,
368 Trig_Prim_A =>Trig_Prim_A_sig,
369 Trig_Prim_B =>Trig_Prim_B_sig,
370 Trig_Prim_C =>Trig_Prim_C_sig,
371 Trig_Prim_D =>Trig_Prim_D_sig,
372 ext_Trig =>ext_Trig_sig,
373 Veto =>Veto_sig,
374 NIM_In =>NIM_In_sig,
375 NIM_In3_GCLK =>NIM_In3_GCLK_sig,
376 LED_red =>LED_red_sig,
377 LED_ye =>LED_ye_sig,
378 LED_gn =>LED_gn_sig,
379 CLK_Clk_Cond =>CLK_Clk_Cond_sig,
380 LE_Clk_Cond =>LE_Clk_Cond_sig,
381 DATA_Clk_Cond =>DATA_Clk_Cond_sig,
382 SYNC_Clk_Cond =>SYNC_Clk_Cond_sig,
383 LD_Clk_Cond =>LD_Clk_Cond_sig,
384 Bus1_Tx_En =>Bus1_Tx_En_sig,
385 Bus1_Rx_En =>Bus1_Rx_En_sig,
386 Bus1_RxD_0 =>Bus1_RxD_0_sig,
387 Bus1_TxD_0 =>Bus1_TxD_0_sig,
388 Bus1_RxD_1 =>Bus1_RxD_1_sig,
389 Bus1_TxD_1 =>Bus1_TxD_1_sig,
390 Bus1_RxD_2 =>Bus1_RxD_2_sig,
391 Bus1_TxD_2 =>Bus1_TxD_2_sig,
392 Bus1_RxD_3 =>Bus1_RxD_3_sig,
393 Bus1_TxD_3 =>Bus1_TxD_3_sig,
394 Bus2_Tx_En =>Bus2_Tx_En_sig,
395 Bus2_Rx_En =>Bus2_Rx_En_sig,
396 Bus2_RxD_0 =>Bus2_RxD_0_sig,
397 Bus2_TxD_0 =>Bus2_TxD_0_sig,
398 Bus2_RxD_1 =>Bus2_RxD_1_sig,
399 Bus2_TxD_1 =>Bus2_TxD_1_sig,
400 Bus2_RxD_2 =>Bus2_RxD_2_sig,
401 Bus2_TxD_2 =>Bus2_TxD_2_sig,
402 Bus2_RxD_3 =>Bus2_RxD_3_sig,
403 Bus2_TxD_3 =>Bus2_TxD_3_sig,
404 Crate_Res0 =>Crate_Res0_sig,
405 Crate_Res1 =>Crate_Res1_sig,
406 Crate_Res2 =>Crate_Res2_sig,
407 Crate_Res3 =>Crate_Res3_sig,
408 Busy0 =>Busy0_sig,
409 Busy1 =>Busy1_sig,
410 Busy2 =>Busy2_sig,
411 Busy3 =>Busy3_sig,
412 RES_p =>RES_p_sig,
413 RES_n =>RES_n_sig,
414 TRG_p =>TRG_p_sig,
415 TRG_n =>TRG_n_sig,
416 TIM_Run_p =>TIM_Run_p_sig,
417 TIM_Run_n =>TIM_Run_n_sig,
418 TIM_Sel =>TIM_Sel_sig,
419 Cal_0_p =>Cal_0_p_sig,
420 Cal_0_n =>Cal_0_n_sig,
421 Cal_1_p =>Cal_1_p_sig,
422 Cal_1_n =>Cal_1_n_sig,
423 Cal_2_p =>Cal_2_p_sig,
424 Cal_2_n =>Cal_2_n_sig,
425 Cal_3_p =>Cal_3_p_sig,
426 Cal_3_n =>Cal_3_n_sig,
427 Cal_4_p =>Cal_4_p_sig,
428 Cal_4_n =>Cal_4_n_sig,
429 Cal_5_p =>Cal_5_p_sig,
430 Cal_5_n =>Cal_5_n_sig,
431 Cal_6_p =>Cal_6_p_sig,
432 Cal_6_n =>Cal_6_n_sig,
433 Cal_7_p =>Cal_7_p_sig,
434 Cal_7_n =>Cal_7_n_sig
435 );
436
437 -- Stimulus process for clock
438 clk_proc: process
439 begin
440 clk_sig <= '0';
441 wait for clk_period/2;
442 clk_sig <= '1';
443 wait for clk_period/2;
444 end process clk_proc;
445
446end;
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