1 | -------------------------------------------------------------------------------- |
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2 | -- Company: ETH Zurich, Institute for Particle Physics |
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3 | -- Engineer: Q. Weitzel, P. Vogler |
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4 | -- |
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5 | -- Create Date: 08.12.2010 |
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6 | -- Design Name: |
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7 | -- Module Name: FTM_top_tb.vhd |
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8 | -- Project Name: |
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9 | -- Target Device: |
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10 | -- Tool versions: |
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11 | -- Description: Testbench for FTM firmware |
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12 | -- |
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13 | -- VHDL Test Bench Created by ISE for module: FTM_top |
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14 | -- |
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15 | -- Dependencies: |
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16 | -- |
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17 | -- Revision: |
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18 | -- Revision 0.01 - File Created |
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19 | -- Additional Comments: |
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20 | -- |
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21 | -- Notes: |
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22 | -- This testbench has been automatically generated using types std_logic and |
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23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends |
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24 | -- that these types always be used for the top-level I/O of a design in order |
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25 | -- to guarantee that the testbench will bind correctly to the post-implementation |
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26 | -- simulation model. |
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27 | -------------------------------------------------------------------------------- |
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28 | library IEEE; |
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29 | use IEEE.STD_LOGIC_1164.ALL; |
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30 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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31 | use IEEE.NUMERIC_STD.ALL; |
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32 | |
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33 | library UNISIM; |
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34 | use UNISIM.VComponents.all; |
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35 | |
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36 | entity FTM_top_tb is |
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37 | end FTM_top_tb; |
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38 | |
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39 | architecture behavior of FTM_top_tb is |
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40 | |
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41 | -- Component Declaration for the Unit Under Test (UUT) |
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42 | |
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43 | component FTM_top |
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44 | port( |
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45 | |
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46 | -- Clock |
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47 | clk : IN STD_LOGIC; -- external clock from oscillator U47 |
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48 | |
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49 | -- connection to the WIZnet W5300 ethernet controller |
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50 | ------------------------------------------------------------------------------- |
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51 | -- W5300 data bus |
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52 | W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300 |
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53 | |
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54 | -- W5300 address bus |
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55 | W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because |
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56 | -- the W5300 is operated in the |
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57 | -- 16-bit mode |
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58 | -- -> W_A<0> assigned to unconnected pin |
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59 | |
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60 | -- W5300 control signals |
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61 | -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 |
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62 | -- W_CS is also routed to testpoint JP7 |
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63 | W_CS : out STD_LOGIC; -- W5300 chip select |
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64 | W_INT : IN STD_LOGIC; -- interrupt |
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65 | W_RD : out STD_LOGIC; -- read |
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66 | W_WR : out STD_LOGIC; -- write |
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67 | W_RES : out STD_LOGIC; -- reset W5300 chip |
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68 | |
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69 | -- W5300 buffer ready indicator |
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70 | -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); |
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71 | |
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72 | -- testpoints (T18) associated with the W5300 |
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73 | -- W_T : inout STD_LOGIC_VECTOR(3 downto 0); |
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74 | |
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75 | |
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76 | -- SPI Interface |
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77 | -- connection to the EEPROM U36 (AL25L016M) and |
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78 | -- temperature sensors U45, U46, U48 and U49 (all MAX6662) |
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79 | ------------------------------------------------------------------------------- |
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80 | -- S_CLK : out STD_LOGIC; -- SPI clock |
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81 | |
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82 | -- EEPROM |
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83 | -- MOSI : out STD_LOGIC; -- master out slave in |
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84 | -- MISO : in STD_LOGIC; -- master in slave out |
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85 | -- EE_CS : out STD_LOGIC; -- EEPROM chip select |
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86 | |
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87 | -- temperature sensors U45, U46, U48 and U49 |
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88 | -- SIO : inout STD_LOGIC; -- serial IO |
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89 | -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select |
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90 | |
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91 | |
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92 | -- Trigger primitives inputs |
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93 | ------------------------------------------------------------------------------- |
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94 | -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 |
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95 | -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 |
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96 | -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 |
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97 | -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 |
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98 | |
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99 | |
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100 | -- NIM inputs |
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101 | ------------------------------------------------------------------------------ |
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102 | -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input |
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103 | -- Veto : in STD_LOGIC; -- trigger veto input |
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104 | -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs |
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105 | |
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106 | -- alternative external clock input for FPGA |
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107 | -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available |
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108 | |
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109 | |
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110 | -- LEDs |
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111 | ------------------------------------------------------------------------------- |
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112 | LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red |
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113 | LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow |
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114 | LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green |
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115 | |
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116 | |
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117 | -- Clock conditioner LMK03000 |
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118 | ------------------------------------------------------------------------------- |
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119 | CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock |
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120 | LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable |
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121 | DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data |
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122 | |
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123 | SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization |
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124 | LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for |
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125 | |
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126 | |
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127 | -- various RS-485 Interfaces |
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128 | ------------------------------------------------------------------------------- |
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129 | -- Bus 1: FTU slow control |
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130 | Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable |
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131 | Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable |
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132 | |
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133 | Bus1_RxD_0 : in STD_LOGIC; -- crate 0 |
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134 | Bus1_TxD_0 : out STD_LOGIC; |
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135 | |
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136 | Bus1_RxD_1 : in STD_LOGIC; -- crate 1 |
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137 | Bus1_TxD_1 : out STD_LOGIC; |
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138 | |
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139 | Bus1_RxD_2 : in STD_LOGIC; -- crate 2 |
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140 | Bus1_TxD_2 : out STD_LOGIC; |
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141 | |
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142 | Bus1_RxD_3 : in STD_LOGIC; -- crate 3 |
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143 | Bus1_TxD_3 : out STD_LOGIC |
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144 | |
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145 | |
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146 | -- Bus 2: Trigger-ID to FAD boards |
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147 | -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable |
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148 | -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable |
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149 | |
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150 | -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 |
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151 | -- Bus2_TxD_0 : out STD_LOGIC; |
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152 | |
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153 | -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 |
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154 | -- Bus2_TxD_1 : out STD_LOGIC; |
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155 | |
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156 | -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 |
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157 | -- Bus2_TxD_2 : out STD_LOGIC; |
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158 | |
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159 | -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 |
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160 | -- Bus2_TxD_3 : out STD_LOGIC; |
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161 | |
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162 | |
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163 | -- auxiliary access |
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164 | -- Aux_Rx_D : in STD_LOGIC; |
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165 | -- Aux_Tx_D : out STD_LOGIC; |
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166 | -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable |
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167 | -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID |
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168 | |
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169 | |
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170 | -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) |
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171 | -- TrID_Rx_D : in STD_LOGIC; |
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172 | -- TrID_Tx_D : out STD_LOGIC; |
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173 | |
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174 | |
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175 | -- Crate-Resets |
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176 | ------------------------------------------------------------------------------- |
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177 | -- Crate_Res0 : out STD_LOGIC; |
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178 | -- Crate_Res1 : out STD_LOGIC; |
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179 | -- Crate_Res2 : out STD_LOGIC; |
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180 | -- Crate_Res3 : out STD_LOGIC; |
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181 | |
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182 | |
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183 | -- Busy signals from the FAD boards |
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184 | ------------------------------------------------------------------------------- |
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185 | -- Busy0 : in STD_LOGIC; |
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186 | -- Busy1 : in STD_LOGIC; |
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187 | -- Busy2 : in STD_LOGIC; |
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188 | -- Busy3 : in STD_LOGIC; |
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189 | |
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190 | |
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191 | -- NIM outputs |
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192 | -- LVDS output at the FPGA followed by LVDS to NIM conversion stage |
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193 | ------------------------------------------------------------------------------- |
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194 | -- calibration |
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195 | -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+ |
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196 | -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1- |
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197 | -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+ |
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198 | -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2- |
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199 | |
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200 | -- auxiliarry / spare NIM outputs |
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201 | -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+ |
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202 | -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0- |
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203 | -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+ |
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204 | -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1- |
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205 | |
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206 | |
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207 | -- fast control signal outputs |
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208 | -- LVDS output at the FPGA followed by LVDS to NIM conversion stage |
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209 | ------------------------------------------------------------------------------- |
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210 | -- RES_p : out STD_LOGIC; -- RES+ Reset |
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211 | -- RES_n : out STD_LOGIC; -- RES- |
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212 | |
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213 | -- TRG_p : out STD_LOGIC; -- TRG+ Trigger |
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214 | -- TRG_n : out STD_LOGIC; -- TRG- |
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215 | |
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216 | -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker |
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217 | -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- |
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218 | -- TIM_Sel : out STD_LOGIC; -- Time Marker selector |
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219 | |
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220 | -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA |
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221 | |
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222 | |
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223 | -- LVDS calibration outputs |
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224 | ------------------------------------------------------------------------------- |
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225 | -- to connector J13 |
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226 | -- for light pulsar in the mirror dish |
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227 | -- Cal_0_p : out STD_LOGIC; |
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228 | -- Cal_0_n : out STD_LOGIC; |
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229 | -- Cal_1_p : out STD_LOGIC; |
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230 | -- Cal_1_n : out STD_LOGIC; |
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231 | -- Cal_2_p : out STD_LOGIC; |
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232 | -- Cal_2_n : out STD_LOGIC; |
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233 | -- Cal_3_p : out STD_LOGIC; |
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234 | -- Cal_3_n : out STD_LOGIC; |
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235 | |
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236 | -- to connector J12 |
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237 | -- for light pulsar inside shutter |
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238 | -- Cal_4_p : out STD_LOGIC; |
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239 | -- Cal_4_n : out STD_LOGIC; |
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240 | -- Cal_5_p : out STD_LOGIC; |
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241 | -- Cal_5_n : out STD_LOGIC; |
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242 | -- Cal_6_p : out STD_LOGIC; |
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243 | -- Cal_6_n : out STD_LOGIC; |
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244 | -- Cal_7_p : out STD_LOGIC; |
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245 | -- Cal_7_n : out STD_LOGIC |
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246 | |
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247 | |
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248 | -- Testpoints |
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249 | ------------------------------------------------------------------------------- |
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250 | -- TP : inout STD_LOGIC_VECTOR(32 downto 0); |
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251 | -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only |
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252 | |
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253 | -- Board ID - inputs |
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254 | -- local board-ID "solder programmable" |
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255 | -- all on 'input only' pins |
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256 | ------------------------------------------------------------------------------- |
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257 | -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only |
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258 | |
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259 | ); |
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260 | end component; |
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261 | |
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262 | --Inputs |
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263 | signal clk_sig : STD_LOGIC := '0'; |
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264 | signal W_INT_sig : STD_LOGIC := '0'; |
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265 | signal W_BRDY_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); |
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266 | signal Trig_Prim_A_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0'); |
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267 | signal Trig_Prim_B_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0'); |
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268 | signal Trig_Prim_C_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0'); |
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269 | signal Trig_Prim_D_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0'); |
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270 | signal ext_Trig_sig : STD_LOGIC_VECTOR(2 downto 1) := (others => '0'); |
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271 | signal Veto_sig : STD_LOGIC := '0'; |
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272 | signal NIM_In_sig : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); |
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273 | signal NIM_In3_GCLK_sig : STD_LOGIC := '0'; |
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274 | signal LD_Clk_Cond_sig : STD_LOGIC := '1'; |
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275 | signal Bus1_RxD_0_sig : STD_LOGIC := '1'; |
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276 | signal Bus1_RxD_1_sig : STD_LOGIC := '1'; |
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277 | signal Bus1_RxD_2_sig : STD_LOGIC := '1'; |
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278 | signal Bus1_RxD_3_sig : STD_LOGIC := '1'; |
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279 | signal Bus2_RxD_0_sig : STD_LOGIC := '1'; |
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280 | signal Bus2_RxD_1_sig : STD_LOGIC := '1'; |
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281 | signal Bus2_RxD_2_sig : STD_LOGIC := '1'; |
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282 | signal Bus2_RxD_3_sig : STD_LOGIC := '1'; |
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283 | signal Busy0_sig : STD_LOGIC := '0'; |
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284 | signal Busy1_sig : STD_LOGIC := '0'; |
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285 | signal Busy2_sig : STD_LOGIC := '0'; |
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286 | signal Busy3_sig : STD_LOGIC := '0'; |
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287 | |
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288 | --Input/Output Pins |
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289 | signal W_D_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); |
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290 | signal W_T_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); |
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291 | signal SIO_sig : STD_LOGIC := '0'; |
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292 | |
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293 | --Outputs |
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294 | signal W_A_sig : STD_LOGIC_VECTOR(9 downto 0); |
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295 | signal W_CS_sig : STD_LOGIC; |
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296 | signal W_RD_sig : STD_LOGIC; |
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297 | signal W_WR_sig : STD_LOGIC; |
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298 | signal W_RES_sig : STD_LOGIC; |
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299 | signal S_CLK_sig : STD_LOGIC; |
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300 | signal TS_CS_sig : STD_LOGIC_VECTOR(3 downto 0); |
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301 | signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0); |
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302 | signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0); |
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303 | signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0); |
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304 | signal CLK_Clk_Cond_sig : STD_LOGIC; |
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305 | signal LE_Clk_Cond_sig : STD_LOGIC; |
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306 | signal DATA_Clk_Cond_sig : STD_LOGIC; |
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307 | signal SYNC_Clk_Cond_sig : STD_LOGIC; |
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308 | signal Bus1_Tx_En_sig : STD_LOGIC; |
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309 | signal Bus1_Rx_En_sig : STD_LOGIC; |
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310 | signal Bus1_TxD_0_sig : STD_LOGIC; |
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311 | signal Bus1_TxD_1_sig : STD_LOGIC; |
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312 | signal Bus1_TxD_2_sig : STD_LOGIC; |
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313 | signal Bus1_TxD_3_sig : STD_LOGIC; |
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314 | signal Bus2_Tx_En_sig : STD_LOGIC; |
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315 | signal Bus2_Rx_En_sig : STD_LOGIC; |
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316 | signal Bus2_TxD_0_sig : STD_LOGIC; |
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317 | signal Bus2_TxD_1_sig : STD_LOGIC; |
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318 | signal Bus2_TxD_2_sig : STD_LOGIC; |
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319 | signal Bus2_TxD_3_sig : STD_LOGIC; |
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320 | signal Crate_Res0_sig : STD_LOGIC; |
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321 | signal Crate_Res1_sig : STD_LOGIC; |
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322 | signal Crate_Res2_sig : STD_LOGIC; |
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323 | signal Crate_Res3_sig : STD_LOGIC; |
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324 | signal RES_p_sig : STD_LOGIC; |
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325 | signal RES_n_sig : STD_LOGIC; |
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326 | signal TRG_p_sig : STD_LOGIC; |
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327 | signal TRG_n_sig : STD_LOGIC; |
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328 | signal TIM_Run_p_sig : STD_LOGIC; |
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329 | signal TIM_Run_n_sig : STD_LOGIC; |
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330 | signal TIM_Sel_sig : STD_LOGIC; |
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331 | signal Cal_0_p_sig : STD_LOGIC; |
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332 | signal Cal_0_n_sig : STD_LOGIC; |
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333 | signal Cal_1_p_sig : STD_LOGIC; |
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334 | signal Cal_1_n_sig : STD_LOGIC; |
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335 | signal Cal_2_p_sig : STD_LOGIC; |
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336 | signal Cal_2_n_sig : STD_LOGIC; |
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337 | signal Cal_3_p_sig : STD_LOGIC; |
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338 | signal Cal_3_n_sig : STD_LOGIC; |
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339 | signal Cal_4_p_sig : STD_LOGIC; |
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340 | signal Cal_4_n_sig : STD_LOGIC; |
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341 | signal Cal_5_p_sig : STD_LOGIC; |
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342 | signal Cal_5_n_sig : STD_LOGIC; |
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343 | signal Cal_6_p_sig : STD_LOGIC; |
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344 | signal Cal_6_n_sig : STD_LOGIC; |
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345 | signal Cal_7_p_sig : STD_LOGIC; |
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346 | signal Cal_7_n_sig : STD_LOGIC; |
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347 | |
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348 | -- Clock period definitions |
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349 | constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 |
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350 | constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate |
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351 | |
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352 | begin |
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353 | |
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354 | -- Instantiate the Unit Under Test (UUT) |
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355 | uut: FTM_top |
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356 | port map( |
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357 | clk => clk_sig, |
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358 | W_D => W_D_sig, |
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359 | W_A => W_A_sig, |
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360 | W_CS => W_CS_sig, |
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361 | W_INT => W_INT_sig, |
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362 | W_RD => W_RD_sig, |
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363 | W_WR => W_WR_sig, |
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364 | W_RES => W_RES_sig, |
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365 | -- W_BRDY => W_BRDY_sig, |
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366 | -- W_T => W_T_sig, |
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367 | -- S_CLK => S_CLK_sig, |
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368 | -- SIO => SIO_sig, |
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369 | -- TS_CS => TS_CS_sig, |
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370 | -- Trig_Prim_A => Trig_Prim_A_sig, |
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371 | -- Trig_Prim_B => Trig_Prim_B_sig, |
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372 | -- Trig_Prim_C => Trig_Prim_C_sig, |
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373 | -- Trig_Prim_D => Trig_Prim_D_sig, |
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374 | -- ext_Trig => ext_Trig_sig, |
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375 | -- Veto => Veto_sig, |
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376 | -- NIM_In => NIM_In_sig, |
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377 | -- NIM_In3_GCLK => NIM_In3_GCLK_sig, |
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378 | LED_red => LED_red_sig, |
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379 | LED_ye => LED_ye_sig, |
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380 | LED_gn => LED_gn_sig, |
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381 | CLK_Clk_Cond => CLK_Clk_Cond_sig, |
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382 | LE_Clk_Cond => LE_Clk_Cond_sig, |
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383 | DATA_Clk_Cond => DATA_Clk_Cond_sig, |
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384 | SYNC_Clk_Cond => SYNC_Clk_Cond_sig, |
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385 | LD_Clk_Cond => LD_Clk_Cond_sig, |
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386 | Bus1_Tx_En => Bus1_Tx_En_sig, |
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387 | Bus1_Rx_En => Bus1_Rx_En_sig, |
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388 | Bus1_RxD_0 => Bus1_RxD_0_sig, |
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389 | Bus1_TxD_0 => Bus1_TxD_0_sig, |
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390 | Bus1_RxD_1 => Bus1_RxD_1_sig, |
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391 | Bus1_TxD_1 => Bus1_TxD_1_sig, |
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392 | Bus1_RxD_2 => Bus1_RxD_2_sig, |
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393 | Bus1_TxD_2 => Bus1_TxD_2_sig, |
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394 | Bus1_RxD_3 => Bus1_RxD_3_sig, |
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395 | Bus1_TxD_3 => Bus1_TxD_3_sig |
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396 | -- Bus2_Tx_En => Bus2_Tx_En_sig, |
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397 | -- Bus2_Rx_En => Bus2_Rx_En_sig, |
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398 | -- Bus2_RxD_0 => Bus2_RxD_0_sig, |
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399 | -- Bus2_TxD_0 => Bus2_TxD_0_sig, |
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400 | -- Bus2_RxD_1 => Bus2_RxD_1_sig, |
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401 | -- Bus2_TxD_1 => Bus2_TxD_1_sig, |
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402 | -- Bus2_RxD_2 => Bus2_RxD_2_sig, |
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403 | -- Bus2_TxD_2 => Bus2_TxD_2_sig, |
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404 | -- Bus2_RxD_3 => Bus2_RxD_3_sig, |
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405 | -- Bus2_TxD_3 => Bus2_TxD_3_sig, |
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406 | -- Crate_Res0 => Crate_Res0_sig, |
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407 | -- Crate_Res1 => Crate_Res1_sig, |
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408 | -- Crate_Res2 => Crate_Res2_sig, |
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409 | -- Crate_Res3 => Crate_Res3_sig, |
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410 | -- Busy0 => Busy0_sig, |
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411 | -- Busy1 => Busy1_sig, |
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412 | -- Busy2 => Busy2_sig, |
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413 | -- Busy3 => Busy3_sig, |
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414 | -- RES_p => RES_p_sig, |
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415 | -- RES_n => RES_n_sig, |
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416 | -- TRG_p => TRG_p_sig, |
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417 | -- TRG_n => TRG_n_sig, |
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418 | -- TIM_Run_p => TIM_Run_p_sig, |
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419 | -- TIM_Run_n => TIM_Run_n_sig, |
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420 | -- TIM_Sel => TIM_Sel_sig, |
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421 | -- Cal_0_p => Cal_0_p_sig, |
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422 | -- Cal_0_n => Cal_0_n_sig, |
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423 | -- Cal_1_p => Cal_1_p_sig, |
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424 | -- Cal_1_n => Cal_1_n_sig, |
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425 | -- Cal_2_p => Cal_2_p_sig, |
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426 | -- Cal_2_n => Cal_2_n_sig, |
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427 | -- Cal_3_p => Cal_3_p_sig, |
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428 | -- Cal_3_n => Cal_3_n_sig, |
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429 | -- Cal_4_p => Cal_4_p_sig, |
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430 | -- Cal_4_n => Cal_4_n_sig, |
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431 | -- Cal_5_p => Cal_5_p_sig, |
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432 | -- Cal_5_n => Cal_5_n_sig, |
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433 | -- Cal_6_p => Cal_6_p_sig, |
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434 | -- Cal_6_n => Cal_6_n_sig, |
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435 | -- Cal_7_p => Cal_7_p_sig, |
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436 | -- Cal_7_n => Cal_7_n_sig |
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437 | ); |
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438 | |
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439 | -- Stimulus process for clock |
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440 | clk_proc: process |
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441 | begin |
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442 | clk_sig <= '0'; |
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443 | wait for clk_period/2; |
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444 | clk_sig <= '1'; |
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445 | wait for clk_period/2; |
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446 | end process clk_proc; |
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447 | |
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448 | -- Stimulus process for RS485 of crate 0 |
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449 | rs485_0_proc: process |
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450 | |
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451 | procedure assign_rs485_0 (data: std_logic_vector(7 downto 0)) is |
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452 | begin |
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453 | Bus1_RxD_0_sig <= '0'; --start bit |
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454 | wait for baud_rate_period; |
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455 | Bus1_RxD_0_sig <= data(0); --bit 0 |
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456 | wait for baud_rate_period; |
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457 | Bus1_RxD_0_sig <= data(1); --bit 1 |
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458 | wait for baud_rate_period; |
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459 | Bus1_RxD_0_sig <= data(2); --bit 2 |
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460 | wait for baud_rate_period; |
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461 | Bus1_RxD_0_sig <= data(3); --bit 3 |
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462 | wait for baud_rate_period; |
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463 | Bus1_RxD_0_sig <= data(4); --bit 4 |
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464 | wait for baud_rate_period; |
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465 | Bus1_RxD_0_sig <= data(5); --bit 5 |
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466 | wait for baud_rate_period; |
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467 | Bus1_RxD_0_sig <= data(6); --bit 6 |
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468 | wait for baud_rate_period; |
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469 | Bus1_RxD_0_sig <= data(7); --bit 7 |
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470 | wait for baud_rate_period; |
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471 | Bus1_RxD_0_sig <= '1'; --stop bit |
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472 | wait for baud_rate_period; |
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473 | Bus1_RxD_0_sig <= '1'; --stop bit |
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474 | wait for baud_rate_period; |
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475 | end assign_rs485_0; |
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476 | |
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477 | begin |
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478 | --------------------------------------------------------------------------- |
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479 | -- time of FTU answer |
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480 | --------------------------------------------------------------------------- |
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481 | wait for 2ms; |
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482 | --------------------------------------------------------------------------- |
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483 | -- data package of FTU answer (28 byte) |
---|
484 | --------------------------------------------------------------------------- |
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485 | assign_rs485_0(X"40"); --start delimiter |
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486 | wait for 0us; |
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487 | assign_rs485_0(X"C0"); --FTM address |
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488 | wait for 0ns; |
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489 | assign_rs485_0(X"00"); --FTU address |
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490 | wait for 0ns; |
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491 | assign_rs485_0(X"01"); --FTM firmware ID |
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492 | wait for 0ns; |
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493 | assign_rs485_0(X"05"); --instruction |
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494 | wait for 0us; |
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495 | assign_rs485_0(X"00"); --data byte 01 |
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496 | wait for 0ns; |
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497 | assign_rs485_0(X"00"); --data byte 02 |
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498 | wait for 0ns; |
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499 | assign_rs485_0(X"00"); --data byte 03 |
---|
500 | wait for 0ns; |
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501 | assign_rs485_0(X"00"); --data byte 04 |
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502 | wait for 0ns; |
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503 | assign_rs485_0(X"00"); --data byte 05 |
---|
504 | wait for 0ns; |
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505 | assign_rs485_0(X"00"); --data byte 06 |
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506 | wait for 0ns; |
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507 | assign_rs485_0(X"00"); --data byte 07 |
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508 | wait for 0ns; |
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509 | assign_rs485_0(X"00"); --data byte 08 |
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510 | wait for 0ns; |
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511 | assign_rs485_0(X"00"); --data byte 09 |
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512 | wait for 0ns; |
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513 | assign_rs485_0(X"00"); --data byte 10 |
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514 | wait for 0ns; |
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515 | assign_rs485_0(X"00"); --data byte 11 |
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516 | wait for 0ns; |
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517 | assign_rs485_0(X"00"); --data byte 12 |
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518 | wait for 0ns; |
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519 | assign_rs485_0(X"00"); --data byte 13 |
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520 | wait for 0ns; |
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521 | assign_rs485_0(X"00"); --data byte 14 |
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522 | wait for 0ns; |
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523 | assign_rs485_0(X"00"); --data byte 15 |
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524 | wait for 0ns; |
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525 | assign_rs485_0(X"00"); --data byte 16 |
---|
526 | wait for 0ns; |
---|
527 | assign_rs485_0(X"00"); --data byte 17 |
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528 | wait for 0ns; |
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529 | assign_rs485_0(X"00"); --data byte 18 |
---|
530 | wait for 0ns; |
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531 | assign_rs485_0(X"00"); --data byte 19 |
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532 | wait for 0ns; |
---|
533 | assign_rs485_0(X"00"); --data byte 20 |
---|
534 | wait for 0ns; |
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535 | assign_rs485_0(X"00"); --data byte 21 |
---|
536 | wait for 0ns; |
---|
537 | assign_rs485_0(X"00"); --CRC error counter (not used) |
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538 | wait for 0ns; |
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539 | --assign_rs485_0(X"9E"); --check sum for rates |
---|
540 | assign_rs485_0(X"A5"); --check sum for ping |
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541 | --------------------------------------------------------------------------- |
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542 | -- don't forget final wait! |
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543 | --------------------------------------------------------------------------- |
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544 | wait; |
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545 | |
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546 | end process rs485_0_proc; |
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547 | |
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548 | end; |
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